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nov 2013 rev 2 1/391 UM0434 e200z3 powerpc core reference manual introduction the primary objective of this user?s manual is to describe the functionality of the e200z3 embedded microprocessor core for software and hardware developers. this book is intended as a companion to the eref: a programmer's reference manual for freescale book e processors (hereafter referred to as eref ). book e is a powerpc? architecture definition for embedded processors that ensures binary compatibility with the user-ins truction set architecture (u isa) portion of the powerpc architecture as it was jointly developed by apple, ibm, and motorola (referred to as the aim architecture). this document distinguishes among the three levels of the architectural and implementation definition, as follows: the book e architecture?book e defines a set of user-level instructions and registers that are drawn from the user instruction set architecture (uisa) portion of the aim definition powerpc architecture. book e also includes numerous supervisor-level registers and instructions as they were defined in the aim version of the powerpc architecture for th e virtual environment architec ture (vea) and the operating environment architecture (oea). because the operating system resources (such as the mmu and interrupts) defined by book e differ greatly from those defined by the aim architecture, book e introduces many new registers and instructions. freescale book e implementation standards (eis)?in many cases, the book e architecture definition provides a general framework, leaving specific details up to the implementation. to ensure consistency among its book e implementations, freescale has defined implementation standards that provide an additional layer of architecture between book e and the actual devices. e200z3 implementation details?each processor typically defines instructions, registers, register fields, and other aspects that are more detailed than either the book e definition or the eis. this book describes all of the instructions and registers implemented on the e200z3, including those defined by book e and by the eis, as we ll as those that are e200z3-specific. information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. as with any technical documentation, it is the readers? responsibility to be su re they are using the most rece nt version of the documentation. www.st.com
table of contents UM0434 2/391 table of contents 1 organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.1 bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.2 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3 audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1 terminology conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2 acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 e200z3 core complex overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 overview of the e200z3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2.1 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4 vle apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.5 interrupts and exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.5.1 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.5.2 interrupt classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5.3 interrupt types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5.4 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.6 microarchitecture summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.6.1 instruction unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6.2 integer unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6.3 load/store unit (lsu) features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6.4 memory management unit (mmu) features . . . . . . . . . . . . . . . . . . . . . . 34 3.6.5 system bus (core complex interface) features . . . . . . . . . . . . . . . . . . . . 35 3.6.6 nexus3 module features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.7 legacy support of powerpc architecture . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.7.1 instruction set compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.7.2 memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.7.3 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.7.4 memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
UM0434 table of contents 3/391 3.7.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.7.6 little-endian mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4 register model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.1 powerpc book e registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2 e200z3 - specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3 e200z3-specific device control registers . . . . . . . . . . . . . . . . . . . . . . . . 43 4.4 processor control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.4.1 machine state register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.4.2 processor id register (pir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.4.3 processor version register (pvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.4.4 system version register (svr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.5 registers for integer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.5.1 general purpose registers (gprs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.5.2 integer exception register (xer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6 registers for branch operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6.1 condition register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6.2 count register (ctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.6.3 link register (lr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.7 spe and spfp apu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.7.1 signal processing/embedded floating-point status and control register (spefscr) 52 4.7.2 accumulator (acc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.8 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.8.1 interrupt registers defined by book e . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.9 exception syndrome register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.9.1 vle mode instruction syndrome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.9.2 misaligned instruction fetch syndrome . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.9.3 precise external termination error syndrome . . . . . . . . . . . . . . . . . . . . . 61 4.9.4 e200z3 specific interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.10 software use sprs (sprg0?sprg7 and usprg0) . . . . . . . . . . . . . . . 63 4.11 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.11.1 timer control register (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.11.2 timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.11.3 time base (tbu and tbl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.11.4 decrementer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
table of contents UM0434 4/391 4.11.5 decrementer auto-reload register (decar) . . . . . . . . . . . . . . . . . . . . . 69 4.12 debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.12.1 debug address and value registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.12.2 debug counter register (dbcnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.12.3 debug control and status registers (dbcr0?dbcr3) . . . . . . . . . . . . . 71 4.12.4 debug status register (dbsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.13 hardware implementation dependent registers . . . . . . . . . . . . . . . . . . . . 84 4.13.1 hardware implementation dependent register 0 (hid0) . . . . . . . . . . . . 84 4.13.2 hardware implementation dependent register 1 (hid1) . . . . . . . . . . . . 86 4.14 branch target buffer (btb) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.14.1 branch unit control and status register (bucsr) . . . . . . . . . . . . . . . . . 87 4.15 l1 cache configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.15.1 l1 cache configuration register 0 (l1cfg0) . . . . . . . . . . . . . . . . . . . . . 88 4.16 mmu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.16.1 mmu control and status register 0 (mmucsr0) . . . . . . . . . . . . . . . . . . 88 4.16.2 mmu configuration register (mmucfg) . . . . . . . . . . . . . . . . . . . . . . . . 89 4.16.3 tlb configuration registers (tlb n cfg) . . . . . . . . . . . . . . . . . . . . . . . . 90 4.16.4 mmu assist registers (mas0?mas4, mas6) . . . . . . . . . . . . . . . . . . . . 91 4.16.5 process id register (pid0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.17 support for fast context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.17.1 context control register (ctxcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.18 spr register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.18.1 invalid spr references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.18.2 synchronization requirements for sprs . . . . . . . . . . . . . . . . . . . . . . . . 98 4.18.3 special purpose register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.18.4 reset settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.19 parallel signature unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.19.1 parallel signature control register (pscr) . . . . . . . . . . . . . . . . . . . . . . 104 4.19.2 parallel signature status register (pssr) . . . . . . . . . . . . . . . . . . . . . . 105 4.19.3 parallel signature high register (pshr) . . . . . . . . . . . . . . . . . . . . . . . . 105 4.19.4 parallel signature low register (pslr) . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.19.5 parallel signature counter register (psctr) . . . . . . . . . . . . . . . . . . . . 106 4.19.6 parallel signature update high register (psuhr) . . . . . . . . . . . . . . . . 106 4.19.7 parallel signature update low register (psulr) . . . . . . . . . . . . . . . . . 107 5 instruction model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
UM0434 table of contents 5/391 5.1 operand conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.1.1 data organization in memory and data transfers . . . . . . . . . . . . . . . . . 108 5.1.2 alignment and misaligned accesses . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.1.3 e200z3 floating-point implementation . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.2 unsupported instructions and instruction fo rms . . . . . . . . . . . . . . . . . . . 109 5.3 optionally supported instructions and in struction forms . . . . . . . . . . . . 109 5.4 implementation-specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.5 booke instruction extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.6 memory access alignment support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.7 memory synchronization and reservation instructions . . . . . . . . . . . . . . 111 5.8 branch prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.9 interruption of instructions by interrupt requests . . . . . . . . . . . . . . . . . . 112 5.10 e200z3-specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.10.1 integer select apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.10.2 debug apu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.10.3 spe apu instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.10.4 embedded vector and scalar single precision floating point apu instructions 120 5.11 unimplemented sprs and read only sprs . . . . . . . . . . . . . . . . . . . . . . 122 5.12 invalid instruction forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.13 instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.13.1 instruction index sorted by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.13.2 instruction index sorted by opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 6 interrupts and exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.2 e200z3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 6.3 exception syndrome register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.4 machine state register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.4.1 machine check syndrome register (mcsr) . . . . . . . . . . . . . . . . . . . . . 166 6.5 interrupt vector offset registers (ivorn) . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.6 interrupt definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.6.1 critical input interrupt (ivor0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.6.2 machine check interrupt (ivor1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.6.3 data storage interrupt (ivor2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
table of contents UM0434 6/391 6.6.4 instruction storage interrupt (ivor3) . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6.6.5 external input interrupt (ivor4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 6.6.6 alignment interrupt (ivor5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.6.7 program interrupt (ivor6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.6.8 floating-point unavailable interrupt (ivor7) . . . . . . . . . . . . . . . . . . . . 175 6.6.9 system call interrupt (ivor8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.6.10 auxiliary processor unavailable interrupt (ivor9) . . . . . . . . . . . . . . . . 176 6.6.11 decrementer interrupt (ivor10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.6.12 fixed-interval timer interrupt (ivor11) . . . . . . . . . . . . . . . . . . . . . . . . 177 6.6.13 watchdog timer interrupt (ivor12) . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 6.6.14 data tlb error interrupt (ivor13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 6.6.15 instruction tlb error interrupt (ivor14) . . . . . . . . . . . . . . . . . . . . . . . 179 6.6.16 debug interrupt (ivor15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 6.6.17 system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 6.6.18 spe apu unavailable interrupt (ivor32) . . . . . . . . . . . . . . . . . . . . . . 183 6.6.19 spe floating-point data interrupt (ivor33) . . . . . . . . . . . . . . . . . . . . 184 6.6.20 spe floating-point round in terrupt (ivor34) . . . . . . . . . . . . . . . . . . . 185 6.7 exception recognition and priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.7.1 interrupt priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 6.8 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 6.8.1 enabling and disabling exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 6.8.2 returning from an interrupt handler . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.9 process switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 7 memory management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 7.1.1 mmu features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 7.1.2 tlb entry maintenance features summary . . . . . . . . . . . . . . . . . . . . . 192 7.2 effective to real address translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 7.2.1 effective addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 7.2.2 address spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 7.2.3 virtual addresses and process id . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 7.2.4 translation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 7.2.5 permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 7.3 translation lookaside buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 7.3.1 iprot invalidation protection in tlb1 . . . . . . . . . . . . . . . . . . . . . . . . . 198
UM0434 table of contents 7/391 7.3.2 replacement algorithm for tlb1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 7.3.3 the g bit (of wimge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 7.3.4 tlb entry field summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 7.4 software interface and tlb instructions . . . . . . . . . . . . . . . . . . . . . . . . . 200 7.5 tlb operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 7.5.1 translation reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.5.2 reading the tlb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.5.3 writing the tlb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.5.4 searching the tlb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.5.5 tlb coherency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.5.6 tlb miss exception update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.5.7 tlb load on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.6 mmu configuration and control registers . . . . . . . . . . . . . . . . . . . . . . . . 203 7.6.1 mmu configuration register (mmucfg) . . . . . . . . . . . . . . . . . . . . . . . 204 7.6.2 tlb0 and tlb1 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . 204 7.6.3 data exception address register (dear) . . . . . . . . . . . . . . . . . . . . . . . 204 7.6.4 mmu control and status register 0 (mmucsr0) . . . . . . . . . . . . . . . . . 204 7.6.5 mmu assist registers (mas) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 7.7 effect of hardware debug on mmu operation . . . . . . . . . . . . . . . . . . . . . 205 8 instruction pipeline and execut ion timing . . . . . . . . . . . . . . . . . . . . . 206 8.1 overview of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 8.1.1 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 8.1.2 instruction unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 8.1.3 branch unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 8.1.4 instruction decode unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 8.1.5 exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 8.2 execution units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 8.2.1 integer execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 8.2.2 load/store unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 8.3 instruction pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.3.1 description of pipeline stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 8.3.2 instruction buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 8.3.3 single-cycle instruction pipeline operation . . . . . . . . . . . . . . . . . . . . . 212 8.3.4 basic load and store instruction pipeline operation . . . . . . . . . . . . . . . 212 8.3.5 change-of-flow instruction pipeline operation . . . . . . . . . . . . . . . . . . 213
table of contents UM0434 8/391 8.3.6 basic multi-cycle instruction pipeline operation . . . . . . . . . . . . . . . . . 214 8.3.7 additional examples of instruction pipeline operation for load & store . 214 8.3.8 move to/from spr instruction pipeline operation . . . . . . . . . . . . . . . . . 215 8.4 stalls caused by accessing sprs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 8.5 instruction serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 8.6 interrupt recognition and exception processing . . . . . . . . . . . . . . . . . . . 218 8.7 instruction timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 8.7.1 spe and embedded fl oating-point instruction timing . . . . . . . . . . . . . 226 8.8 operand placement on performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 9 external core complex interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 9.2 signal index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 9.3 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 9.3.1 processor state signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 9.3.2 jtag id signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 9.4 internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 9.5 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 9.5.1 processor instruction/data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . 265 9.5.2 burst accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 9.5.3 address retraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 9.5.4 address retraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 9.5.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 9.5.6 interrupt interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 10 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.1.1 power management signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 10.1.2 power management control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 10.1.3 software considerations for power management . . . . . . . . . . . . . . . . . 294 10.1.4 debug considerations for power management . . . . . . . . . . . . . . . . . . 295 11 debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 11.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 11.2.1 software debug facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
UM0434 table of contents 9/391 11.2.2 additional debug facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 11.2.3 hardware debug facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 11.3 debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 11.4 software debug events and exceptions . . . . . . . . . . . . . . . . . . . . . . . . . 299 11.5 external debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 11.5.1 once introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 11.5.2 jtag/once signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 11.5.3 once internal interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 11.5.4 once interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 11.5.5 once controller and serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . 310 11.5.6 access to debug resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 11.5.7 methods for entering debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 11.5.8 cpu status and control scan chain register (cpuscr) . . . . . . . . . . . 319 11.5.9 instruction address fifo buffer (pc fifo) . . . . . . . . . . . . . . . . . . . . . 324 11.5.10 reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 11.6 watchpoint support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 11.7 mmu and cache operation during debug . . . . . . . . . . . . . . . . . . . . . . . . 327 11.8 enabling, using, and exiting external debug mode: example . . . . . . . . . 327 12 nexus3 module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 12.1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 12.1.2 terms and definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 12.1.3 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 12.2 enabling nexus3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 12.3 tcodes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 12.4 nexus3 programmer?s model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 12.4.1 client select control register (csc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 12.4.2 port configuration register (pcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 12.4.3 development control register 1, 2 (dc1, dc2) . . . . . . . . . . . . . . . . . . 339 12.4.4 development status register (ds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 12.4.5 read/write access control/status register (rwcs) . . . . . . . . . . . . . . 341 12.4.6 read/write access data register (rwd) . . . . . . . . . . . . . . . . . . . . . . . 342 12.4.7 read/write access address register (rwa) . . . . . . . . . . . . . . . . . . . . 344 12.4.8 watchpoint trigger register (wt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 12.4.9 data trace control register (dtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
table of contents UM0434 10/391 12.4.10 data trace start address 1 and 2 registers (dtsa1 and dtsa2) . . . . 347 12.4.11 data trace end address registers 1 and 2 (dtea1 and dtea2) . . . . . 347 12.5 nexus3 register access through jtag/once . . . . . . . . . . . . . . . . . . . . 348 12.6 ownership trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 12.6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 12.6.2 ownership trace messaging (otm) . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.6.3 otm error messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.6.4 otm flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 12.7 program trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 12.7.1 branch trace messaging (btm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 12.7.2 btm message formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 12.7.3 btm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 12.7.4 program trace timing diagrams (2 mdo/1 mseo configuration) . . . . 359 12.8 data trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 12.8.1 data trace messaging (dtm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 12.8.2 dtm message formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 12.8.3 dtm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 12.8.4 data trace timing diagrams (8 mdo/2 mseo configuration) . . . . . . . 365 12.9 watchpoint support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 12.9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 12.9.2 watchpoint messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 12.9.3 watchpoint error message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 12.9.4 watchpoint timing diagram (2 mdo/1 mseo configuration) . . . . . . . . 367 12.10 nexus3 read/write access to memory-mapped resources . . . . . . . . . . 367 12.10.1 single write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 12.10.2 block write access (non-burst mode) . . . . . . . . . . . . . . . . . . . . . . . . . 368 12.10.3 block write access (burst mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 12.10.4 single read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 12.10.5 block read access (non-burst mode) . . . . . . . . . . . . . . . . . . . . . . . . . 370 12.10.6 block read access (burst mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 12.10.7 error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 12.11 nexus3 pin interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 12.11.1 pins implemented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 12.11.2 pin protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 12.12 rules for output messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 12.13 auxiliary port arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
UM0434 table of contents 11/391 12.14 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 12.15 ieee 1149.1 (jtag) rd/wr sequences . . . . . . . . . . . . . . . . . . . . . . . . 379 12.15.1 jtag sequence for accessing internal nexus registers . . . . . . . . . . . . 379 12.15.2 jtag sequence for read access of memory-mapped resources . . . . . 379 12.15.3 jtag sequence for write access of memory-mapped resources . . . . . 380 13 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
list of tables UM0434 12/391 list of tables table 1. terminology conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 2. acronyms and abbreviated terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 table 3. scalar and vector embedded floating-point apu instructions. . . . . . . . . . . . . . . . . . . . . . . 28 table 4. interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5. exceptions and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 6. machine state register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 7. msr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 8. processor id register (pir). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 9. pir field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 10. processor version register (pvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 11. pvr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 12. svr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 13. integer exception register (xer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 14. xer field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 15. condition register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 16. bi operand settings for cr fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 17. cr0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 18. cr setting for compare instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 19. count register (ctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 20. link register (lr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 21. signal processing and embedded floating point status and control register (spefscr) . 52 table 22. spefscr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 23. save/restore register 0 (srr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 24. save/restore register 1 (srr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 25. critical save/restore register 0 (csrr0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 26. critical save/restore register 1 (csrr1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 27. data exception address register (dear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 28. interrupt vector prefix register (ivpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 29. ivpr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 30. interrupt vector offset registers (ivor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 31. ivor field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 32. ivor assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 33. exception syndrome register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 table 34. esr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 35. debug save/restore register 0 (dsrr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 36. debug save/restore register 1 (dsrr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 37. machine check syndrome register (mcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 38. mcsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 39. software use sprs (sprg0?sprg7 and usprg0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 40. timer control register (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 41. tcr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 42. timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 43. timer status register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 44. time base upper/lower registers (tbu/tbl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 45. decrementer register (dec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 46. decrementer auto-reload register (decar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 47. instruction address compare registers (iac1?iac4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 48. data address compare registers (dac1?dac2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
UM0434 list of tables 13/391 table 49. dbcnt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 50. dbcr0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 51. dbcr0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 52. debug control register 1 (dbcr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 53. dbcr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 54. dbcr2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 55. dbcr3 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 56. dbcr3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 57. dbsr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 58. dbsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 59. hardware implementation dependent register 0 (hid0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 60. hid0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 61. hardware implementation dependent register 1 (hid1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 62. hid1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 63. branch unit control and status register (bucsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 64. branch unit control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 65. mmu control and status register 0 (mmucsr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 66. mmucsr0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 67. mmu configuration register 1 (mmucfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 68. mmucfg field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 69. tlb configuration register 0 (tlb0cfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 70. tlb0cfg field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 71. tlb configuration register 1 (tlb1cfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 72. tlb1cfg field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 73. mas register 0 (mas0) format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 74. mas0 - mmu read/write and replacement control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 75. mmu assist register 1 (mas1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 76. mas1 - descriptor context and configuration control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 77. mmu assist register 2 (mas2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 78. mas2 - epn and page attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 79. mmu assist register 3 (mas3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 80. mas3 - rpn and access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 81. mmu assist register 4 (mas4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 82. mas4 - hardware replacement assist configuration register . . . . . . . . . . . . . . . . . . . . . . . 95 table 83. mmu assist register 6 (mas6)). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 84. mas6 - tlb search context register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 table 85. process id register (pid0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 86. context control register (ctxcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 87. system response to invalid spr reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 88. additional synchronization requirements for sprs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 89. special purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 90. reset settings for e200z3 resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 table 91. parallel signature control register (pscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 92. pscr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 93. parallel signature status register (pssr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 table 94. pssr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 95. parallel signature high register (pshr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 table 96. parallel signature low register (pslr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 06 table 97. parallel signature counter register (psctr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 98. parallel signature update high register (psuhr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 99. parallel signature update low register (psulr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 100. list of unsupported instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
list of tables UM0434 14/391 table 101. list of optionally supported instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 102. implementation-specific instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 103. memory synchronization and reservation instructions e200z3 specific details. . . . . . . . . 111 table 104. spe apu vector multiply instru ction mnemonic structure . . . . . . . . . . . . . . . . . . . . . . . . 113 table 105. mnemonic extensions for multiply-accumulate instructions . . . . . . . . . . . . . . . . . . . . . . . 113 table 106. spe apu vector instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 107. vector and scalar spfp apu floating-point instructions . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 108. embedded floating-point apu options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 109. invalid instruction forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 110. instructions sorted by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 111. instructions sorted by opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 112. full instruction listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 113. interrupt classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 114. exceptions and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 115. exception syndrome register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 table 116. esr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 117. processor state definition of msr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 118. msr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 119. machine check syndrome register (mcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 120. mcsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 121. ivpr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 122. ivpr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 123. ivor register fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 124. ivor assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 125. critical input interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 126. machine check interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 0 table 127. data storage interrupt register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 128. isi exceptions and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 129. instruction storage interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 72 table 130. external input interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 131. alignment interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 132. program interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 133. floating-point unavailable interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 134. system call interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 135. decrementer interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 77 table 136. fixed-interval timer interrupt register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 77 table 137. watchdog timer interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 table 138. data tlb error interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 79 table 139. instruction tlb error interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 140. debug exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 141. debug interrupt register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 142. tsr watchdog timer reset status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 143. dbsr most recent reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 144. system reset register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 145. spe unavailable interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 table 146. spe floating-point dat a interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 147. spe floating-point round interrupt regist er settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 148. e200z3 exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 149. msr setting due to interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 150. tlb maintenance programming model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 151. page size (for e200z3 core) and epn field comparison . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 152. tlb entry bit fields for e200z3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
UM0434 list of tables 15/391 table 153. tlbivax ea bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 154. tlb entry 0 values after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 155. mmu assist registers summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 156. mmu assist register field updates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 157. pipeline stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 158. instruction timing by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 159. timing for integer simple instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table 160. spe load and store instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 161. spe complex in teger instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 table 162. spe vector fl oating-point instruction timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 table 163. scalar spe floating-poi nt instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 table 164. performance effects of storage operand placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 table 165. interface signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 table 166. processor clock signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 table 167. descriptions of signals related to reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 table 168. descriptions of signals for the address and data buses . . . . . . . . . . . . . . . . . . . . . . . . . . 243 table 169. descriptions of transfer attribute signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 table 170. descriptions of signals for byte lane specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 table 171. byte strobe assertion for transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 table 172. big-and little-endian storage (64-bit gpr cont ains ?a b c d e f g h?) . . . . . . . . . . . . . 248 table 173. descriptions of signals for transfer control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 table 174. descriptions of master id configuration signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 table 175. descriptions of interrupt signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 table 176. descriptions of timer facility signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 table 177. descriptions of processor reservation signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 table 178. descriptions of miscellaneous processor signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 table 179. descriptions of processor state signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 55 table 180. descriptions of power management control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 table 181. descriptions of debug events signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 57 table 182. core debug/emulation support signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 table 183. descriptions of debug/emulation (nexus 1/ once) support signals . . . . . . . . . . . . . . . . 259 table 184. core development support (nexus3) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 table 185. jtag primary interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 table 186. descriptions of jtag interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 60 table 187. jtag register id fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 table 188. jtag id register inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 table 189. descriptions of jtag id signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 table 190. internal signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 table 191. power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 table 192. descriptions of timer facilit y and power management signals . . . . . . . . . . . . . . . . . . . . . 293 table 193. power management control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 table 194. debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 table 195. debug event descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 table 196. jtag/once primary interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 table 197. once internal interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 table 198. once interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 table 199. once status register (osr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 table 200. osr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 table 201. ocmd fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 table 202. ocmd field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 table 203. once control register fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 table 204. once control register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
list of tables UM0434 16/391 table 205. once register access requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 table 206. methods for entering debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 19 table 207. control state register (ctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 table 208. ctl field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 table 209. watchpoint output signal assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 table 210. terms and definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 table 211. public tcodes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 table 212. error code encodings (tcode = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 table 213. resource code encodings (tcode = 27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 table 214. event code encodings (tcode = 33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 table 215. data trace size encodings (tcode = 5, 6, 13, or 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 table 216. nexus3 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 table 217. client select control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 table 218. csc field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 table 219. port configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 table 220. pcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 table 221. development control register 1 (dc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 table 222. dc1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 table 223. development control register 2 (dc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 0 table 224. dc2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 table 225. development status register (ds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 table 226. ds field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 table 227. read write access control/status register (rwcs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 table 228. rwcs field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 table 229. read/write access status bit encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 table 230. read/write access data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 table 231. rwd data placement for transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 43 table 232. rwd byte lane data placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 table 233. read/write access address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 table 234. watchpoint trigger register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 table 235. wt field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 table 236. data trace control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 table 237. dtc field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 table 238. data trace start address registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 table 239. data trace end address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 table 240. data trace?address range options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 table 241. nexus3 register access through jtag/once (example) . . . . . . . . . . . . . . . . . . . . . . . . 348 table 242. nexus register example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 table 243. ownership trace message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 49 table 244. error message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 table 245. indirect branch message sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 table 246. direct branch message sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 table 247. indirect branch message (history) format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 table 248. indirect branch message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 table 249. direct branch message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 table 250. rcode encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 table 251. debug status message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 table 252. program correlation message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 table 253. error message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 table 254. direct/indirect branch with synchronization message format . . . . . . . . . . . . . . . . . . . . . . 356 table 255. indirect branch history with synchronization message format . . . . . . . . . . . . . . . . . . . . . 356 table 256. program trace exception summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6
UM0434 list of tables 17/391 table 257. relative address generation and re-creation example . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 table 258. data write message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 table 259. data read message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 table 260. error message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 table 261. data write/read with synchronization message format . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 table 262. data trace exception summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 table 263. e200z3 bus cycle cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 table 264. watchpoint message format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 table 265. watchpoint source encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 table 266. error message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 table 267. single write access field settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 table 268. single read access parameter settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 table 269. error message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 table 270. jtag pins for nexus3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 table 271. nexus3 auxiliary pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 table 272. nexus port arbitration signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 table 273. mseo pin(s) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 table 274. mdo request encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 table 275. indirect branch message example (2 mdo/1 mseo). . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 table 276. indirect branch message example (8 mdo/2 mseo). . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 table 277. direct branch message example (2 mdo/1 mseo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 table 278. direct branch message example (8 mdo / 2 mseo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 table 279. data write message example (8 mdo/1 mseo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 table 280. data write message example (8 mdo/2 mseo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 table 281. accessing internal nexus3 registers through jtag/once. . . . . . . . . . . . . . . . . . . . . . . . 379 table 282. accessing memory-mapped resources (reads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 table 283. accessing memory-mapped resources (writes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 table 284. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
list of figures UM0434 18/391 list of figures figure 1. e200z3 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 2. e200z3 programmer?s model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 3. e200z3 programmer?s model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 4. system version register (svr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 5. relationship of timer facilities to the time base. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 figure 6. parallel signature unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 7. effective to real address translation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 94 figure 8. virtual address and tlb-entry compare process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 9. granting of access permission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 10. e200z3 tlb1 organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 figure 11. victim selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 figure 12. e200z3 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 figure 13. pipeline diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 figure 14. instruction buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 figure 15. branch target buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 16. basic pipeline flow, single-cycle instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 17. a load followed by a dependent add instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 18. back-to-back load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 19. a load followed by a dependent store instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 20. basic pipeline flow, branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 figure 21. basic pipeline flow, branch speculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 14 figure 22. basic pipeline flow, multi-cycle instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 figure 23. pipelined load/store instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 figure 24. pipelined load/store instructions with wait-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 figure 25. mtspr, mfspr instruction execution?(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 figure 26. mtmysr, wrtee, wrteei instruction execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 figure 27. dcr, mmu mtspr, mfspr, and mmu management instruction execution . . . . . . . . . . . . . 217 figure 28. interrupt recognition and handler instruction execution . . . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 29. interrupt recog. & handler instruction exe-load/store in progress . . . . . . . . . . . . . . . . . . . 219 figure 30. interrupt recog. & handler instruction exe-multi-cycle instruction abort . . . . . . . . . . . . . . 220 figure 31. core signal groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 figure 32. example external jtag register design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 figure 33. basic read transfer?single-cycle reads, full pipelining . . . . . . . . . . . . . . . . . . . . . . . . . 267 figure 34. read with wait-state, single-cycle reads, full pipelining . . . . . . . . . . . . . . . . . . . . . . . . . 268 figure 35. basic write transfers?single-cycle writes, full pipelining . . . . . . . . . . . . . . . . . . . . . . . . 269 figure 36. write with wait-state, single-cycle writes, full pipelining . . . . . . . . . . . . . . . . . . . . . . . . . 270 figure 37. single-cycle reads, single-cycle write, full pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 figure 38. single-cycle read, write, read?full pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 figure 39. multiple-cycle reads with wait-state, single-cycle writes, full pipelining. . . . . . . . . . . . . 273 figure 40. multi-cycle read with wait-state, single -cycle write, read with wa it-state, full pipelining274 figure 41. misaligned read, read, full pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 figure 42. misaligned write, write, full pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 figure 43. misaligned write, single cycle read transfer, full pipelining . . . . . . . . . . . . . . . . . . . . . . . . 277 figure 44. burst read transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 figure 45. burst read with wait-state transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 figure 46. burst write transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 figure 47. burst write with wait-state transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 figure 48. burst read transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
UM0434 list of figures 19/391 figure 49. burst read with wait-state transfer, retraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 figure 50. burst write transfers, single-beat burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 figure 51. read transfer with wait-state, address retraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 figure 52. burst read with wait-state transfer, retraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 figure 53. read and write transfers: instruction read with error, data read, write, full pipelining . . . 284 figure 54. data read with error, data write retracted, instruction read, full pipelining . . . . . . . . . . . . 285 figure 55. misaligned write with error, data write retracted, burst read substituted, full pipelining . . 286 figure 56. burst read with error termination, burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 figure 57. read transfer with wait-state, address retraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 figure 58. burst read with wait-state transfer, retraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 figure 59. wakeup control signal (p_wakeup). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 89 figure 60. interrupt interface input signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 figure 61. interrupt pending operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 figure 62. interrupt acknowledge operation case 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 figure 63. interrupt acknowledge operation case 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 figure 64. power management state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 figure 65. core debug resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 figure 66. core debug resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 figure 67. once tap controller and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 06 figure 68. once controller as an fsm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 figure 69. once controller and serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 figure 70. cpu scan chain register (cpuscr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 figure 71. once pc fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 figure 72. nexus3 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 figure 73. resource full message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 figure 74. program trace?indirect branch message (traditional) . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 figure 75. program trace?indirect branch message (history) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 figure 76. program trace?direct branch (traditional) and error messages. . . . . . . . . . . . . . . . . . . . 360 figure 77. program trace?indirect branch with synchronization message . . . . . . . . . . . . . . . . . . . 360 figure 78. data trace?data write message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 65 figure 79. data trace?data read with synchronization message . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 figure 80. error message (data trace only encoded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 figure 81. watchpoint message and watchpoint error message . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 figure 82. state diagram for single pin mseo transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 figure 83. dual-pin mseo transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
organization UM0434 20/391 1 organization following is a summary and a brief description of the major sections of this manual: chapter 3: e200z3 core complex overview on page 24 ,? provides a general description of e200z3 functionality. chapter 4: register model on page 38 ,? is useful for software engineers who need to understand the programming model for the three programming environments and the functionality of each register. chapter 5: instruction model on page 108 ,? provides an overview of the addressing modes and a description of the instructions. instructions are organized by function. chapter 6: interrupts and exceptions on page 160 ,? describes how the e200z3 implements the interrupt model as it is defined by the book e architecture. chapter 7: memory management unit on page 192 ,? provides specific hardware and software details regarding the e200z3 mmu implementation. chapter 8: instruction pipeline and execution timing on page 206 ,? describes how instructions are fetched, decoded, issued, executed, completed, and how instruction results are presented to the processor and memory system. tables are provided that indicate latency and throughput for each of the instructions supported by the e200z3. chapter 9: external core complex interfaces on page 235 ,? describes those aspects of the ccb that are configurable or that provide status information through the programming interface. it provides a glossary of signals mentioned throughout the book to offer a clearer understanding of how the core is integrated as part of a larger device. chapter 10: power management on page 292 ,? describes the power management facilities as they are defined by book e and implemented in the e200z3 core. chapter 11: debug support on page 296 ,? describes the debug facilities as they are defined by book e and implemented in the e200z3 core. chapter 12: nexus3 module on page 329 ,? describes the e200z3 nexus3 module, which provides real-time deve lopment capabilities for e200z3 processors in compliance with the ieee-isto nexus 5001-2003 standard. this book also includes an index. 1.1 bibliography the following documentation, published by morgan-kaufmann publishers, 340 pine street, sixth floor, san francisco, ca, provides useful information about the powerpc architecture and computer architecture in general: the powerpc architecture: a specification for a new family of risc processors , second edition, by international business machines, inc. for updates to the specification, see http://www.austin.ibm.com/tech/ppc-chg.html computer architecture: a quantitative approach , third edition, by john l. hennessy and david a. patterson. computer organization and design: the hardware/software interface , second edition, david a. patterson and john l. hennessy. note: it is assumed that the reader underst ands operating systems, microprocessor system design, and the basic princi ples of risc processing.
UM0434 conventions 21/391 2 conventions this document uses the following notational conventions: 2.1 terminology conventions table 1 lists certain terms used in this manual that differ from the architecture terminology conventions. cleared/set when a bit takes the value zero, it is said to be cleared; when it takes a value of one, it is said to be set. mnemonics instruction mnemonics are shown in lowercase bold . italics italics indicate variable command parameters, for example, bcctr x. book titles in text are set in italics. internal signals are set in italics, for example, qual bg . 0x0 prefix to denote hexadecimal number 0b0 prefix to denote binary number r a, r b instruction syntax used to identify a source gpr r d instruction syntax used to identify a destination gpr reg[field] abbreviations for registers are shown in uppercase text. specific bits, fields, or ranges appear in brackets. for example, msr[le] refers to the little-endian mode enable bit in the machine state register. x in some contexts, such as signal encodings, an unitalicized x indicates a don?t care. x an italicized x indicates an alphanumeric variable. n an italicized n indicates a numeric variable. ? not logical operator & and logical operator | or logical operator table 1. terminology conventions architecture specification this manual change bit changed bit extended mnemonics simplified mnemonics out of order memory accesses s peculative memory accesses privileged mode (or privileged state) supervisor level problem mode (or problem state) user level reference bit referenced bit relocation translation storage (locations) memory storage (the act of) access
conventions UM0434 22/391 2.2 acronyms and abbreviations table 2 contains acronyms and abbreviations that are used in this document. table 2. acronyms and abbreviated terms term meaning cr condition register ctr count register dcr data control register dtlb data translation lookaside buffer ea effective address ecc error checking and correction fpr floating-point register gpr general-purpose register ieee institute of el ectrical and electronics engineers itlb instruction translation lookaside buffer l2 secondary cache lifo last-in-first-out lr link register lru least recently used lsb least-significant byte lsb least-significant bit mmu memory management unit msb most-significant byte msb most-significant bit msr machine state register nan not a number nia next instruction address no-op no operation pte page table entry risc reduced instruction set computing rtl register transfer language simm signed immediate value spr special-purpose register tlb translation lookaside buffer uimm unsigned immediate value uisa user instruction set architecture va virtual address vle variable-length encoding xer register used primarily for indicating conditions such as carries and overflows for integer operations
e200z3 core complex overview UM0434 24/391 3 e200z3 core complex overview this chapter provides an overview of the powerpc? e200z3 microprocessor core. it includes the following: an overview of the book e version of the powerpc architecture features as implemented in this core a summary of the core feature set an overview of the programming model an overview of interrupts and exception handling a summary of instruction pipeline and flow a description of the memory-management architecture high-level details of the e200z3 core memory and coherency model a summary of the book e arch itecture compatibilit y and migration from the original version of the powerpc architecture as it is defined by apple, ibm, (referred to as the aim version of the powerpc architecture) information regarding e200z3 features that are defined by the book e implementation standards (eis) 3.1 overview of the e200z3 the e200z3 processor family is a set of cpu cores that are low-cost implementations of the powerpc book e architecture. e200z3 processors are designed for deeply embedded control applications th at require low-cost solutions rather than maximum performance. the e200z3 core implements the variable-length encoding (vle) apu, providing improved code density. see the eref for more information about the vle extension. figure 1. e200z3 block diagram instruction bus interface unit software-managed unified memory unit mas registers 32 gprs (64-bit) xer cr 4-, 16-, 64-, 256-kbyte; execution units sprs integer + x unit spe apu + x unit embedded + x scalar fpu embedded + x vector fpu load/store branch unit write-back stage tw o / fo u r instructions 32 64 n address data control additional features ?once/nexus 1/nexus 3 control logic ? amba ahb- lite bus + l1 unified mmu unit ctr lr single-instruction, in-order dispatch single-instruction, in-order write back ? ? ? 16-entry fully associative tlb ea calc four-cycle, single-path execute stage with overlapped execution and fetch unit branch processing unit instruction/control unit instruction buffer (7 instructions) decode 8-entry branch stage + ea calc two-cycle fetch stage program counter target buffer data bus interface unit 32 64 n address data control optional extension vle apu execute stage feed forwarding
UM0434 e200z3 core complex overview 25/391 the e200z3 is a single-issue, 32-bit, book e?compliant design with 64-bit, general-purpose registers (gprs). a signal processing extension (spe) apu and embedded vector and scalar floating-point apus are provided to support real-time integer and single-precision embedded floating- point operations using the gprs. the e200z3 does not support book e floating-point instructions in hardware but traps them so they can be emulated by software. all arithmetic instructions that execute in the core operate on data in the gprs, which have been extended to 64 bits to support vector instructions defined by the spe and embedded vector floating-point apus. these instructions operate on a vector pair of 16- or 32-bit data types and deliver vector and scalar results. the e200z3 contains a memory management unit (mmu) and a nexus class 3+ module. the e200z3 platform is specified in such a way that functional units can be added or removed. the e200z3 can be configured with a powerful vectored interrupt controller and one or more ip slave interfaces, as well as support for configured memory units. 3.1.1 features key features of the e200z3 are summarized as follows: single-issue, 32-bit book e?compliant core implementation of the vle apu for reduced code footprint in-order execution and retirement precise interrupt handling branch processing unit (bpu) ? dedicated branch address calculation adder ? branch target prefetching using an eight-entry branch target buffer (btb) branch acceleration using branch lookahead instruction buffer ? load/store unit (lsu) ? 31-cycle load latency ? fully pipelined ? big- and little-endian support on a per-page basis ? misaligned access support ? zero load-to-use pipeline bubbles power management ? low-power design?extensive clock gating ? power-saving modes: doze, nap, sleep ? dynamic power management of execution units, caches, and mmus amba? (advanced microcontroller bus architecture) ahb (advanced high- performance bus)-lite 64-bit system bus mmu with 16-entry, fully associative tlb and multiple page-size support signal processing extensio n (spe) apu supporting int eger operations using both halves of the 64-bit gprs single-precision embedded scalar floating-point apu single-precision embedded vector floating-po int apu that uses both halves of the 64- bit gprs
e200z3 core complex overview UM0434 26/391 nexus class 3+ real-time development unit e200z3-specific debug interrupt. the e200z3 implements the debug interrupt as defined in book e with the following changes: ? when the debug apu is enabled (hid0[dapuen] = 1), debug is no longer a critical interrupt, but uses dsrr0 and dsrr1 for saving machine state on context switch. ? the return from debug interrupt (rfdi) instruction supports the debug apu save/restore registers (dsrr0 and dsrr1). ? a critical interrupt taken debug event allows critical interrupts to generate a debug event. a critical interrupt return debug event allows debug events to be generated for rfci instructions. testability ? synthesizable, full muxd scan design ? abist/mbist for optional memory arrays testability ? synthesizable, full muxd scan design ? abist/mbist for optional memory arrays 3.2 programming model this section describes the register model, instruction model, and the interrupt model as they are defined by book e, eis, and the e200z3 implementation. 3.2.1 register set figure 2 shows the e200z3 register set, indicating which registers are accessible in supervisor mode and which are accessible in user mode. the number to the left of the special-purpose registers (sprs) is the decimal number used in the instruction syntax to access the register. (for example, the integer exception register (xer) is spr 1.) gprs are accessed through instruction operands. access to other registers can be explicit (by using instructions for that purpose such as the move to special purpose register ( mtspr ) and move from special purpose register ( mfspr ) instructions) or implicit as part of the execution of an instruction. some registers are accessed both explicitly and implicitly.
UM0434 e200z3 core complex overview 27/391 figure 2. e200z3 programmer?s model 1. the 64-bit registers are accessed by the spe as separate 32-bit regist ers by spe instructions. only spe vector instructions can access the upper word. 2. usprg0 is a separate physi cal register from sprg0. 3. eis specific registers not part of the book e architecture. 4. ivor9 (handles auxiliary processo r unavailable interupt) is defined by the eis but not supported by the e200z3. 5. e200z3 specific registers may not be supported by other powerpc processors. 3.3 instruction set the e200z3 implements the following instructions: the book e instruction set for 32-bit implemen tations. this is composed primarily of the user-level instructions defined by the powerpc user instruction set architecture user-level registers general-purpose registers instruction on-accessible registers user general spr (read/write) 0 31 32 63 0 31 32 63 32 63 user spr general 0 (upper) gpr0 1 (lower) general- purpose registers cr condition register spr 256 usprg0 2 gpr1 spr 9 ctr count register general sprs (read-only) gpr2 spr 8 lr link register spr 260 sprg4 spr general registers 4?7 gpr31 spr 261 sprg5 spr 1 xer integer exception register spr 262 sprg 6 l1 cache (read-only) spr 512 spefscr 3 sp/embedded fp status/control register spr 263 sprg 7 l1 cache configuration register 0 spr 515 l1cfg0 3 acc 3 accumulator time-base registers (read-only) spr 268 tbl time base lower/upper spr 269 tbu supervisor-level registers interrupt registers configuration registers 32 63 32 63 32 63 spr 63 ivpr interrupt vector prefix register spr 400 ivor0 interrupt vector offset registers 0?15 4 msr machine state register spr 401 ivor1 spr 26 srr0 save/restore registers 0/1 spr 1023 svr 3 system version register spr 27 srr1 spr 415 ivor15 spr 286 pir processor id register spr 58 csrr0 critical srr 0/1 processor version register spr 528 ivor32 3 interrupt vector offset registers 32?34 spr 287 pvr spr 59 csrr1 spr 529 ivor33 3 spr 574 dsrr0 3 debug interrupt srr 0/1 spr 530 ivor34 3 timer/decrementer registers spr 575 dsrr1 3 exception syndrome register spr 22 dec decrementer spr 62 esr mmu control and status (read/write) decrementer auto-reload register mmu control and status register 0 spr 54 decar spr 572 mcsr 3 machine check syndrome register spr 1012 mmucsr0 3 spr 284 tbl time base lower/upper spr 61 dear data exception address register spr 624 mas0 3 mmu assist registers 0?4 and 6 spr 285 tbu spr 625 mas1 3 debug registers spr 626 mas2 3 spr 340 tcr timer control register spr 627 mas3 3 spr 308 dbcr0 debug control registers 0?3 spr 336 tsr timer status register spr 628 mas4 3 spr 309 dbcr1 spr 630 mas6 3 miscellaneous registers spr 310 dbcr2 process id register 0 spr 561 dbcr3 spr 48 pid0 spr 1008 hid0 3 hardware implementation dependent 0?1 spr 1009 hid1 3 spr 304 dbsr debug status register mmu control and status (read only) spr 1013 bucsr 5 branch control and status register spr 562 dbcnt 5 debug count register spr 1015 mmucfg 3 mmu configuration spr 272?279 sprg0?7 general sprs 0?7 spr 312 iac1 instruction address compare registers 1?4 spr 688 tlb0cfg 3 tlb configuration 0/1 spr 313 iac2 spr 689 tlb1cfg 3 context control (read/write) spr 314 iac3 context control register parallel signature unit registers 5 spr 560 ctxcr 5 spr 315 iac4 data address compare registers 1 and 2 dcr 272 pscr ps control spr 316 dac1 dcr 273 pssr ps status spr 317 dac2 dcr 274 pshr ps high dcr 275 pslr ps low dcr 276 psctr ps counter dcr 277 psuhr ps update high dcr 278 psulr ps update low
e200z3 core complex overview UM0434 28/391 (uisa). the e200z3 does not include the book e floating-point, load string, or store string instructions. the e200z3 supports the following eis-defined instructions: ? integer select apu. this apu consists of the integer select instruction ( isel ), which functions as an if-then-else statement that selects between two source registers by comparison to a cr bit. this instruction eliminates conditional branches, takes fewer clock cycles than the equivalent coding, and reduces the code footprint. ? debug apu. this apu defines the return from debug interrupt instruction ( rfdi ). ? spe apu vector instructions. new vector instructions are defined that view the 64- bit gprs as being composed of a vector of two 32-bit elements (some of the instructions also read or write 16-bit elements). some scalar instructions are defined for dsp that produce a 64-bit scalar result. ? the embedded floating-point apus provide single-precision scalar and vector floating-point instructions. scalar floating-point instructions use only the lower 32 bits of the gprs for single-precision floating-point calculations. table 3 lists embedded floating-point instructions. ? e200z3 implements eight additional (four scalar and four vector) floating-point apu instructions. table 3. scalar and vector embedded floating-point apu instructions instruction mnemonic syntax scalar vector convert floating point from signed fraction efscfsf evfscfsf r d ,r b convert floating point from signed integer efscfsi evfscfsi r d ,r b convert floating point from unsigned fraction efscfuf evfscfuf r d ,r b convert floating point from unsigned integer efscfui evfscfui r d ,r b convert floating point to signed fraction efsctsf evfsctsf r d ,r b convert floating point to signed integer efsctsi evfsctsi r d ,r b convert floating point to signed integer with round toward zero efsctsiz evfsctsiz r d ,r b convert floating point to unsigned fraction efsctuf evfsctuf r d ,r b convert floating point to unsigned integer efsctui evfsctui r d ,r b convert floating point to unsigned integer with round toward zero efsctuiz evfsctuiz r d ,r b floating-point absolute value efsabs evfsabs r d ,r a floating-point add efsadd evfsadd r d ,r a ,r b floating-point compare equal efscmpeq evfscmpeq cr d ,r a ,r b floating-point compare greater than efscmpgt evfscmpgt cr d ,r a ,r b floating-point compare less than efscmplt evfscmplt cr d ,r a ,r b floating-point divide efsdiv evfsdiv r d ,r a ,r b floating-point multiply efsmul evfsmul r d ,r a ,r b floating-point negate efsneg evfsneg r d ,r a
UM0434 e200z3 core complex overview 29/391 3.4 vle apu this section describes the extensions to the book e instructions to support the powerpc vle apu. rfci , rfdi , rfi do not mask bit 62 of csrr0, dsrr0, or srr0. the destination address is [d,c]srr0[32?62] || 0b0. bclr , bclrl , bcctr , bcctrl do not mask bit 62 of the lr or ctr. the destination address is [lr, ctr][32?62] || 0b0. 3.5 interrupts and exception handling the core supports an extended exception h andling model, with neste d interrupt capability and extensive interrupt vector programmability. the following sections define the interrupt model, including an overview of interrupt handling as implemented on the e200z3 core, a brief description of the interrupt classes, and an overview of the registers involved in the processes. 3.5.1 interrupt handling in general, interrupt processing begins with an exception that occurs due to external conditions, errors, or program execution problems. when an exception occurs, the processor checks whether interrupt processing is enabled for that particular exception. if enabled, the interrupt causes the state of the processor to be saved in the appropriate registers and prepares to begin execution of the handler located at the associated vector address for that particular exception. once the handler is executing, the implementation may need to check bits in the exception syndrome register (esr), the machine check syndrome register (mcsr), or the signal processing and embedde d floating-point stat us and control regist er (spefscr), depending on the exception type, to verify the specific cause of the exception and take appropriate action. the core complex supports the interrupts described in section 3.5.4 . floating-point negative absolute value efsnabs evfsnabs r d ,r a floating-point subtract efssub evfssub r d ,r a ,r b floating-point test equal efststeq evfststeq cr d ,r a ,r b floating-point test greater than efststgt evfststgt cr d ,r a ,r b floating-point test less than efststlt evfststlt cr d ,r a ,r b floating-point single-precision multiply-add efsmadd evfsmadd r d ,r a ,r b floating-point single-precision negative multiply-add efsnmadd evfsnmadd r d ,r a ,r b floating-point single-precision multiply-subtract efsmsub evfsmsub r d ,r a ,r b floating-point single-precision negative multiply-subtract efsnmsub evfsnmsub r d ,r a ,r b table 3. scalar and vector embedded floating-point apu instructions (continued) instruction mnemonic syntax scalar vector
e200z3 core complex overview UM0434 30/391 3.5.2 interrupt classes all interrupts may be categorized as asynch ronous/synchronous and critical/noncritical. asynchronous interrupts (such as machine check, critical input, and external interrupts) are caused by events that are independent of instruction execution. for asynchronous interrupts, the address reported in a save/restore register is the address of the instruction that would have executed next had the asynchronous interrupt not occurred. synchronous interrupts are those that are caused directly by the execution or attempted execution of instructions. synchronous inputs are further divided into precise and imprecise types. ? synchronous precise interrupts are those that precisely indicate the address of the instruction causing the exception that generated the interrupt or, in some cases, the address of the immediately following instruction. the interrupt type and status bits allow determination of which of the two instructions has been addressed in the appropriate save/restore register. ? synchronous imprecise interrupts are those that may indicate the address of the instruction causing the exception that generated the interrupt, or some instruction after the instruction causing the interrupt. if the interrupt was caused by either the context synchronizing mechanism or the execution synchronizing mechanism, the address in the appropriate save/restore register is the address of the interrupt- forcing instruction. if the interrupt was not caused by either of those mechanisms, the address in the save/restore register is the last instruction to start execution and may not have completed. no instruction following the instruction in the save/restore register has executed. 3.5.3 interrupt types the e200z3 core processes all interrupts as either debug, critical, or noncritical types. separate control and status register sets are provided for each type of interrupt. the core handles interrupts from these three categories in the following order of priority: 1. debug interrupt?the eis defines a separate set of resources for the debug interrupt. the debug save and restore registers (dsrr0/dsrr1) are used to save state when a debug interrupt is taken; the rfdi instruction restores state when interrupt handling completes.the debug enable bit, hid0[dapue n], determines what interrupt is taken when a debug exception occurs, as follows: ? if dapuen = 0, the debug interrupt is disabled. debug interrupts use the critical interrupt resources: csrr0/csrr1 and rfci ; rfdi is treated as an illegal instruction. dclree, dclrce, ciclrde , and mcclrde settings are ignored and are assumed to be ones. ? if dapuen = 1, the debug apu is enabled. debug interrupts use dsrr0/dsrr1 for saving state, and rfdi is available for returning from a debug interrupt. 2. noncritical interrupts?first-level interrupts that allow the processor to change program flow to handle conditions generated by external signals, errors, or unusual conditions arising from program execution or from programmable timer events. these interrupts are largely identical to those defined by the oea portion of the powerpc architecture. they use the save and restore registers (srr0/srr1) to save state when they are taken, and they use the rfi instruction to restore state. asynchronous noncritical interrupts can be masked by the external interrupt enable bit, msr[ee]. 3. critical interrupts?critical interrupts can be taken during a noncritical interrupt or during regular program flow. they use the critical save and restore registers
UM0434 e200z3 core complex overview 31/391 (csrr0/csrr1) to save state when they are taken, and they use the rfci instruction to restore state. these interrupts can be masked by the critical enable bit, msr[ce]. book e defines the critical input, watchdog timer, and machine check interrupts as critical interrupts, but the e200z3 core defines a third set of resources for the debug interrupt, as described in table 4 . all interrupts except debug interrupts are ordered within the two categories of noncritical and critical, such that only one interrupt of each category is reported, and when it is processed (taken), no program state is lost. because save/restore register pairs are serially reusable, program state may be lost when an unordered interrupt is taken. 3.5.4 interrupt registers table 4. interrupt registers register description noncritical interrupt registers srr0 save/restore register 0?stores the address of the instruction causing the exception or the address of the instruction that will execute after the rfi instruction. srr1 save/restore register 1?saves machine stat e on noncritical interrupts and restores machine state after an rfi instruction is executed. critical interrupt registers csrr0 critical save/restore register 0?on critical interrupts, stores either the address of the instruction causing the exception or the address of the instruction that executes after the rfci . csrr1 critical save/restore register 1?saves machin e state on critical in terrupts and restores machine state after an rfci instruction is executed. debug interrupt registers dsrr0 debug save/restore register 0?used to stor e the address of the instruction that will execute after an rfdi instruction is executed. dsrr1 debug save/restore register 1?stores mach ine state on debug interrupts and restores machine state after an rfdi instruction is executed. syndrome registers mcsr machine check syndrome register?saves machine check syndrome information on machine check interrupts. esr exception syndrome register?provides a syndro me to differentiate among the different kinds of exceptions that generate the same in terrupt type. upon generation of a specific exception type, the associated bits ar e set and all other bits are cleared. spe apu interrupt registers spefscr signal processing and embedded floating-point status and control register?provides interrupt control and status as well as various condition bits associated with the operations performed by the spe apu. other interrupt registers
e200z3 core complex overview UM0434 32/391 each interrupt has an associated interrupt vector address, obtained by concatenating ivpr[32?47] with the address index in the associated ivor (that is, ivpr[32? 47]||ivor n [48?59] || 0b0000). the resulting address is that of the instruction to be executed when that interrupt occurs. ivpr and ivor values are indeterminate on reset and must be initialized by the system software using mtspr . table 4 lists ivor registers implemented on the e200z3 core and the associated interrupts. 3.6 microarchitecture summary the e200z3 processor has a four-stage pipeline for instruction execution. 1. instruction fetch 2. instruction decode/register file read/effective address calculation 3. execute/memory access 4. register writeback these stages are pipelined, allowing single-clock instruction throughput for most instructions. dear data exception address register?contains th e address that was referenced by a load, store, or cache management instruction that caused an alignment, data tlb miss, or data storage interrupt. ivpr ivors together, ivpr[32?47] || ivor n [48?59] || 0b0000 define the address of an interrupt- processing routine. see tab le 5 and 6, ?interrupts and exceptions ,? for more information. table 5. exceptions and conditions ivorn interrupt type ivorn interrupt type none (1) 1. vector to [ p_rstbase[0:19] ]||0xffc. system reset (not an interrupt) 10 decrementer 0 (2) 2. autovectored external and critical input interrupts use this ivor. vectored interrupts supply an interr upt vector offset directly. critical input 11 fixed-interval timer 1 machine check 12 watchdog timer 2 data storage 13 data tlb error 3 instruction storage 14 instruction tlb error 4 2 external input 15 debug 5 alignment 6?31 reserved 6 program 32 spe unavailable 7 floating-point unavaila ble 33 spe data exception 8 system call 34 spe round exception 9 apu unavailable table 4. interrupt registers (continued) register description
UM0434 e200z3 core complex overview 33/391 the integer execution unit consists of a 32-bit arithmetic unit, a logic unit, a 32-bit barrel shifter, a mask-insertion unit, a condition register manipulation unit, a count-leading-zeros unit, a 32
e200z3 core complex overview UM0434 34/391 3.6.1 instruction unit features the e200z3 instruction unit implements the following: 64-bit fetch path that supports fetching of two 32-bit or up to four 16-bit vle apu instructions per clock instruction buffer that holds up to seven sequential instructions dedicated pc (program counter) incrementer supporting instruction fetches branch processing unit with dedicated branch address adder and branch target buffer (btb) supporting single-cycle execution of successfully predicted branches target instruction buffer that holds up to two prefetched branch target instructions 3.6.2 integer unit features the integer unit supports single-cycle execution of most integer instructions: 32-bit au for arithmetic and comparison operations 32-bit lu for logical operations 32-bit priority encoder for count-leading-zeros function 32-bit single-cycle barrel shifter for static shifts and rotates 32-bit mask unit for data masking and insertion divider logic for signed and unsigned divide in 6?16 clocks with minimized execution timing 32
UM0434 e200z3 core complex overview 35/391 3.6.5 system bus (core com plex interface) features the features of the core complex interface are as follows: independent instruction and data buses advanced microcontroller bus architecture (amba) and advanced high-performance bus (ahb2.v6)-lite protocol 32-bit address bus plus attributes and control on each bus instruction interface has 64-bit read data bus data interface has separate unidirectional 64-bit read data bus and 64-bit write data bus pipelined, in-order accesses for both buses. 3.6.6 nexus3 module features the nexus3 module provides real-time develo pment capabilities for e200z3 processors in compliance with the ieee-isto nexus 5001 -2003 standard. this module provides development support capabilitie s without requiring the use of address and da ta pins for internal visibility. a portion of the pin interface (the jtag port) is shared with the once/nexus1 unit. the ieee-isto 5001-2003 sta ndard defines an exte nsible auxiliary port, which is used in conjunction with the jtag port in e200z3 processors. 3.7 legacy support of powerpc architecture this section provides an overvi ew of the architectural differ ences and compatibilities of the e200z3 core compared with the aim powerpc architecture. the two levels of the e200z3 core programming environment are as follows: user level?this defines the base user-level instruction set, registers, data types, memory conventions, and the memory and programming models seen by application programmers. supervisor level?this defines supervisor-l evel resources typically required by an operating system, the memory management model, supervisor-level registers, and the exception model. in general, the e200z3 core supports the user-l evel architecture from the classic powerpc architecture. the following sections are intended to highlight the main differences. for specific implementation details refer to the relevant chapter. 3.7.1 instruction set compatibility the following sections describe the user and supervisor instruction sets. user instruction set the e200z3 core executes legacy user-mode binaries and object files except for the following: the e200z3 core supports vector and scalar single-precision floating-point operations as apus. these instructions have different encoding than the aim definition of the powerpc architecture. additionally, the e200z3 core uses gprs for floating-point
e200z3 core complex overview UM0434 36/391 operations, rather than the fprs defined by the uisa. most porting of floating-point operations can be ha ndled by recompiling. string instructions are not implemented on the e200z3 core; therefore, trap emulation must be provided to ensu re backward compatibility. supervisor instruction set the supervisor-mode instruction set defined by the aim version of the powerpc architecture is compatible with the e200z3 core with the following exceptions: the mmu architecture is different, so some tlb manipulation instructions have different semantics. instructions that support bats and segment registers are not implemented. 3.7.2 memory subsystem both book e and the aim version of the powerpc architecture provide separate instruction and data memory resources. the e200z3 core provides additional cache control features, including cache locking. 3.7.3 interrupt handling exception handling is generally the same as that defined in the aim version of the powerpc architecture for the e200z3 core, with the following differences: book e defines a new critical interrupt, prov iding an interrupt ne sting. the critical interrupt includes critical input and watchdog timer time-out inputs. the debug interrupt differs from the book e and from the aim definition. it defines the return from debug interrupt instruction, rfdi , and two debug save/restore registers, dsrr0 and dsrr1. book e processors can use ivpr and the ivor s to set exception vectors individually, but they can be set to the address offsets defined in the oea to provide compatibility. unlike the aim version of the powerpc architecture, book e does not define a reset vector; execution begins at a fixed virtual address, 0xffff_fffc. the e200z3 allows this to be hard-wired to any page. some book e and e200z3 core-specific sprs are different from those defined in the aim version of the powerpc architecture, particularly those related to mmu functions. much of this information has been moved to the new exception syndrome register (esr). timer services are generally compatible. however, book e defines a decrementer auto-reload feature, and two critical-type interrupts?the fixed-interval timer and the watchdog timer interrupts?all of which are implemented in the e200z3 core. see chapter 3.5 for overview of interrupts and exception handling capabilities. 3.7.4 memory management the e200z3 core implements a straightforward virtual address space that complies with the book e mmu definition, which eliminates segment registers and block address translation resources. book e defines resources for multiple, variable page sizes that can be configured in a single implementation. tlb management is provided with new instructions and sprs.
UM0434 e200z3 core complex overview 37/391 3.7.5 reset book e?compliant cores do not share a common reset vector with the aim version of the powerpc architecture. instead, at reset, fe tching begins at address 0xffff_fffc. in addition to the book e reset definition, the eis and e200z3 core define specific aspects of the mmu page translation and protection mechanisms. unlike the aim version of the powerpc core, as soon as instruction fetching begins, the e200z3 core is in virtual mode with a hardware-initialized tlb entry. 3.7.6 little-endian mode unlike the aim version of the powerpc architecture, where little-endian mode is controlled on a system basis, book e allows control of byte ordering on a memory-page basis. in addition, the little-endian mode used in book e is true little-endian byte ordering (byte invariance).
register model UM0434 38/391 4 register model this chapter describes the registers of the e200z3 core. it includes an overview of registers defined by the book e architecture, highlighting differences in how these registers are implemented in the e200z3 core, and it describes the e200z3-specific registers in detail. full descriptions of the architecture-defined register set are provided in the eref . the book e architecture defines register-to-register operations for all computational instructions. source data for these instructions is accessed from the on-chip registers or as immediate values embedded in the opcode. the three-register instruction format allows specification of a target register distinct from the two source registers, thus preserving the original data for use by other instructions. data is transferred between memory and registers with explicit load and st ore instructions only. the e200z3 extends the general-purpose registers (gprs) to 64 bits to support spe apu operations. powerpc book e instructions operate on the lower 32 bits of the gprs only, and the upper 32 bits are unaffected by these in structions. spe vector in structions operate on the entire 64-bit register. the spe apu defines load and store instructions for transferring 64-bit values to/from memory. figure 3 shows the complete e200z3 register set, indicating which registers are accessible in supervisor mode and which in user mode. the number to the left of the special-purpose registers (sprs) is the decimal number used in the instruction syntax to access the register. for example, the integer exception register (xer) is spr 1. gprs are accessed through instruction operands. access to other registers can be explicit, using instructions such as move to special-purpose register ( mtspr ) and move from special-purpose register ( mfspr ), or implicit as part of the execution of an instruction. some registers are accessed bo th explicitly and implicitly.
UM0434 register model 39/391 figure 3. e200z3 programmer?s model 6. the 64-bit registers are accessed by the spe as separate 32-bit regist ers by spe instructions. only spe vector instructions can access the upper word. 7. usprg0 is a separate physi cal register from sprg0. 8. eis specific registers not part of the book e architecture. 9. ivor9 (handles auxiliary processo r unavailable interupt) is defined by the eis but not supported by the e200z3. 10. e200z3 specific registers may not be supported by other powerpc processors. 4.1 powerpc book e registers the e200z3 supports most of the registers defined by book e architecture. notable exceptions are the floating-point registers fpr0?fpr31 and the fpscr. the e200z3 does not support the book e floating-point architecture in hardware. the gprs are extended to 64 bits. the book e registers in the e200z3 are as follows: user-level registers general-purpose registers instruction on-accessible registers user general spr (read/write) 0 31 32 63 0 31 32 63 32 63 user spr general 0 (upper) gpr0 1 (lower) general- purpose registers cr condition register spr 256 usprg0 2 gpr1 spr 9 ctr count register general sprs (read-only) gpr2 spr 8 lr link register spr 260 sprg4 spr general registers 4?7 gpr31 spr 261 sprg5 spr 1 xer integer exception register spr 262 sprg 6 l1 cache (read-only) spr 512 spefscr 3 sp/embedded fp status/control register spr 263 sprg 7 l1 cache configuration register 0 spr 515 l1cfg0 3 acc 3 accumulator time-base registers (read-only) spr 268 tbl time base lower/upper spr 269 tbu supervisor-level registers interrupt registers configuration registers 32 63 32 63 32 63 spr 63 ivpr interrupt vector prefix register spr 400 ivor0 interrupt vector offset registers 0?15 4 msr machine state register spr 401 ivor1 spr 26 srr0 save/restore registers 0/1 spr 1023 svr 3 system version register spr 27 srr1 spr 415 ivor15 spr 286 pir processor id register spr 58 csrr0 critical srr 0/1 processor version register spr 528 ivor32 3 interrupt vector offset registers 32?34 spr 287 pvr spr 59 csrr1 spr 529 ivor33 3 spr 574 dsrr0 3 debug interrupt srr 0/1 spr 530 ivor34 3 timer/decrementer registers spr 575 dsrr1 3 exception syndrome register spr 22 dec decrementer spr 62 esr mmu control and status (read/write) decrementer auto-reload register mmu control and status register 0 spr 54 decar spr 572 mcsr 3 machine check syndrome register spr 1012 mmucsr0 3 spr 284 tbl time base lower/upper spr 61 dear data exception address register spr 624 mas0 3 mmu assist registers 0?4 and 6 spr 285 tbu spr 625 mas1 3 debug registers spr 626 mas2 3 spr 340 tcr timer control register spr 627 mas3 3 spr 308 dbcr0 debug control registers 0?3 spr 336 tsr timer status register spr 628 mas4 3 spr 309 dbcr1 spr 630 mas6 3 miscellaneous registers spr 310 dbcr2 process id register 0 spr 561 dbcr3 spr 48 pid0 spr 1008 hid0 3 hardware implementation dependent 0?1 spr 1009 hid1 3 spr 304 dbsr debug status register mmu control and status (read only) spr 1013 bucsr 5 branch control and status register spr 562 dbcnt 5 debug count register spr 1015 mmucfg 3 mmu configuration spr 272?279 sprg0?7 general sprs 0?7 spr 312 iac1 instruction address compare registers 1?4 spr 688 tlb0cfg 3 tlb configuration 0/1 spr 313 iac2 spr 689 tlb1cfg 3 context control (read/write) spr 314 iac3 context control register parallel signature unit registers 5 spr 560 ctxcr 5 spr 315 iac4 data address compare registers 1 and 2 dcr 272 pscr ps control spr 316 dac1 dcr 273 pssr ps status spr 317 dac2 dcr 274 pshr ps high dcr 275 pslr ps low dcr 276 psctr ps counter dcr 277 psuhr ps update high dcr 278 psulr ps update low
register model UM0434 40/391 user-level registers, which are accessible to all software with either user or supervisor privileges: ? general-purpose registers (gprs). thirty-two 64-bit gprs (gpr0?gpr31) serve as data source or destination registers for integer instructions and provide data to generate addresses. powerpc book e instructions affect only the lower 32 bits of the gprs. spe apu instructions operate on the entire 64 -bit register. ? condition register (cr). eight 4-bit fields, cr0?cr7, reflect results of certain arithmetic operations and provide a mechanism for testing and branching. the remaining user-level registers are sprs. in the powerpc architecture, the mtspr and mfspr instructions are for accessing sprs. ? integer exception register (xer). indicates overflow and carries for integer operations. ? link register (lr). provides the branch target address for the branch conditional to link register ( bclr , bclrl ) instructions and holds the address of the instruction that follows a branch and link instruction, typically for linking to subroutines. ? count register (ctr). holds a loop count that can be decremented during execution of appropriately coded branch instructions. ctr also provides the branch target address for the branch conditional to count register ( bcctr , bcctrl ) instructions. ? the time base facility (tb) consists of tw o 32-bit registers, time base upper (tbu) and time base lower (tbl). user-level software can read (but not write) to these two registers. ? sprg4?sprg7. software-use special- purpose registers (sprgs). sprg4? sprg7 are read only by user-level software. the e200z3 does not allow user- mode access to sprg3. book e defines such access as implementation- dependent. ? usprg0. user-software-use spr usprg0, which is read-write accessible to user-level software. supervisor-level registers, which are control and status registers accessible to supervisor- level software. an operating system might use these registers for configuration, exception handling, and other operating system functions: processor control registers ? machine state register (msr). defines the state of the processor. the msr can be modified by the move to machine state register ( mtmsr ), system call ( sc ), and return from interrupt ( rfi , rfci , rfdi) instructions. it can be read by the move from machine state register ( mfmsr) instruction. when an interrupt occurs, the contents of the msr are saved to one of the machine state save/restore registers (srr1, csrr1, dsrr1). ? processor version register (pvr). a read-only register that identifies the version (model) and revision level of the powerpc processor. ? processor identification register (pir). a read-only register to distinguish the processor from other processors in the system. storage control registers ? process id register (pid0, also referred to as pid). indicates the current process or task identifier. the mmu uses it as an extension to the effective address, and the external nexus 2 module uses it for ownership trace message generation. powerpc book e allows multiple pids ; the e200z3 implements only one. interrupt registers
UM0434 register model 41/391 ? data exception address register (dear). after most data storage interrupts (dsis), or on an alignment interrupt or data tlb interrupt, dear is set to the effective address (ea) generated by the faulting instruction. ? sprg0?sprg7, usprg0. for software use. see section 4.10: software use sprs (sprg0?sprg7 and usprg0) on page 63 ,? for details on these registers. the e200z3 does not allow user-mode access to the sprg3 register. book e defines access to sprg3 as implementation-dependent. ? exception syndrome register (esr). a syndrome to differentiate between the different kinds of exceptions that can generate the same interrupt. ? interrupt vector prefix register (ivpr) and interrupt-specific interrupt vector offset registers (ivors). provide the address of the interrupt handler for different classes of interrupts. ? save/restore register 0 (srr0). saves machine state on a non-critical interrupt and contains the address of the instruction at which execution resumes when an rfi instruction executes at the end of a non-critical-class interrupt handler routine. ? save/restore register 1 (srr1). saves machine state from the msr on non-critical interrupts and restores machine state when rfi executes. ? critical save/restore register 0 (csrr0). saves machine state on a critical interrupt and contains the address of the instruction at which execution resumes when an rfci instruction executes at the end of a critical-class interrupt handler routine. ? critical save/restore register 1 (csrr1). saves machine state from the msr on critical interrupts and restores machine state when rfci executes. debug facility registers ? debug control registers (dbcr0?dbcr2). provide control for enabling and configuring debug events. ? debug status register (dbsr). contains debug event status. ? instruction address compare registers (iac1?iac4). contain addresses and/or masks to specify instruction address compare debug events. ? data address compare registers (dac1?dac2). contain addresses and/or masks to specify data address compare debug events. note: the e200z3 does not implement data value compare registers (dvc1 and dvc2). timer registers ? time base (tb). maintains the time of day and operates interval timers. the tb consists of two 32-bit registers, time base upper (tbu) and time base lower (tbl). only supervisor level software can write to the time base registers, but both user and supervisor level software can read them. ? decrementer register (dec). a 32-bit decrementing counter for causing a decrementer exception after a programmable delay. ? decrementer auto-reload (decar). supports the auto-reload feature of the decrementer. ? timer control register (tcr). controls the decrementer, fixed interval timer, and watchdog timer options. ? timer status register (tsr). contains status on timer events and the most recent watchdog-timer-initiated processor reset.
register model UM0434 42/391 4.2 e200z3 - specific registers book e allows implementation-specific register s. those in the e200z3 core are as follows: user-level registers, which are accessible to all software with either user or supervisor privileges: ? signal processing/embedded floating-point status and control register (spefscr). contains all in teger and floating-point exception signal bits, exception summary bits, exception enable bits, and rounding control bits for compliance with the ieee 754 standard. ? l1 cache configuration register (l1cfg0). a read-only register that allows software to query the configuration of the l1 cache. for the e200z3, this register returns all zeros. ? the eis-defined accumulator, wh ich is part of the spe apu. see section 4.7.2: accumulator (acc) on page 55 .? supervisor-level registers, which are defined in the e200z3 in addition to the book e registers described in section 4.1: powerpc book e registers on page 39 : ? configuration registers?hardware implementation-dependent registers 0 and 1 (hid0 and hid1). control various processor and system functions. ? exception handling and control registers: ? machine check syndrome register (mcsr). a syndrome to differentiate between the different kinds of conditions that can generate a machine check. ? debug save/restore register 0 (dsrr0). when the debug apu is enabled, dsrr0 saves the address of the instruction at which execution continues when rfdi executes at the end of a debug interrupt handler routine. ? debug save/restore register 1 (dsrr1). when the debug apu is enabled, (hid0[dapuen] = 1), dsrr1 saves machine state from the msr on debug interrupts and restores machine state when rfdi executes. ? debug facility registers ? debug control register 3 (dbcr3). control for debug functions not described in book e ? debug counter register (dbcnt). counter capability for debug functions ? context control registers ? context control register (ctxcr). control for register context selection. ? branch unit control and status register (bucsr). controls operation of the branch target buffer (btb). ? cache registers. this e200z3-specific register may not be supported by other powerpc processors. ? l1 cache configuration register (l1cfg0). a read-only register that allows software to query the configuration of the l1 cache. this register returns all zeros for e200z3 core. ? memory management unit (mmu) registers: ? mmu configuration register (mmucfg). a read-only register that allows software to query the configuration of the mmu. ? mmu assist (mas0?mas4, mas6) registers. the interface to the e200z3 core from the mmu. ? mmu control and status register (mmucsr0). controls mmu invalidation.
UM0434 register model 43/391 ? tlb configuration registers (tlb0cfg and tlb1cfg). read-only registers that allow software to query the configuration of the tlbs. ? system version register (svr). a read-only register that identifies the version (model) and revision level of the system that includes an e200z3 processor. note: although other processors may implement simila r or identical registers, it is not guaranteed that the implementation of e200z3-core-speci fic registers is consistent among powerpc processors. all e200z3 spr definitions comply with the book e definitions. 4.3 e200z3-specific device control registers in addition to the sprs, implementations may also implement one or more device control registers (dcrs). the e200z3 core implements a set of device control registers to perform a parallel signature in the parallel signature unit (psu). these registers may not be supported by other powerpc processors. for details, see chapter 4.19: parallel signature unit registers on page 103 .? 4.4 processor control registers this section discusses machine state, processor id, processor version, and system version registers. 4.4.1 machine stat e register (msr) the msr, shown in figure 6 , defines the state of the processor. chapter 6: interrupts and exceptions ,? describes how the msr is affected by interrupts. table 6. machine state register (msr) msr fields are described in table 7 . 32 36 37 38 39 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 field ? uclespe ? we ce ? ee pr fp me fe0 ? de fe1 ? is ds ? reset all zeros r/w r/w table 7. msr field descriptions bits name description 32?36 ? reserved, should be cleared. 37 ucle user cache lock enable. 0 execution of the cache locking instructions is disabled in user mode (msr[pr] = 1). instead, the data storage interrupt is taken, and ilk or dlk is set in the esr. 1 execution of the cache lock instructions is enabled in user mode.
register model UM0434 44/391 38 spe spe available. 0 execution of spe apu vector instruct ions is disabled. instead, the spe unavailable exception is ta ken, and esr[spe] is set. 1 execution of spe apu vector instructions is enabled. 39?44 ? reserved, should be cleared. 45 we wait state (power management) enable. defined as optional by book e and implemented in the e200z3. 0 power management is disabled. 1 power management is enabled. the pr ocessor can enter a power-saving mode when additional conditions are present. the mode chosen is determined by hid0[doze,nap,sleep] , described in section 4.13.1: hardware implementation dependent register 0 (hid0) .? 46 ce critical interrupt enable 0 critical input and watchdog timer interrupts are disabled. 1 critical input and watchdog timer interrupts are enabled. 47 ? preserved. 48 ee external interrupt enable 0 external input, decrementer, and fixed-interval timer interrupts are disabled. 1 external input, decrementer, and fixed-interval timer interrupts are enabled. 49 pr problem state. 0 the processor is in supervisor mode, ca n execute any instruction, and can access any resource (for example, gprs, all sprs, and the msr). 1 the processor is in user mode, cannot execute any privileged instruction, and cannot access any privileged resource. 50 fp floating-point available. 0 floating-point unit is unavailable. the processor cannot execute floating-point instructions, including floating-point loads, stores, and moves. (an fp unavailable interrupt is generated on attempted execut ion of floating-point instructions). 1 floating-point unit is available. t he processor can execute floating-point instructions. (note that for the e200z3 , the floating-point unit is not supported; an unimplemented operation exception is generated for attempted execution of floating-point instructions when fp is set). 51 me machine check enable. 0 machine check interrupts are disabled. checkstop mode is entered when the p_mcp_b input is recognized asserted or an isi or itlb exception occurs on a fetch of the first instruction of an exception handler. 1 machine check interrupts are enabled. 52 fe0 floating-point exception mode 0 (not used by the e200z3). 53 ? reserved, should be cleared. 54 de debug interrupt enable. 0 debug interrupts are disabled. 1 debug interrupts are enabled if dbcr0[idm] is set. 55 fe1 floating-point exception mode 1 (not used by the e200z3) table 7. msr field descriptions (continued) bits name description
UM0434 register model 45/391 4.4.2 processor id register (pir) the processor id for the cpu core is contained in the processor id register (pir), shown in figure 8 . the contents of pir reflect the hardware input signals to the e200z3 core. pir fields are described in table 9 . 4.4.3 processor versi on register (pvr) the processor version register (pvr), shown in table 10 , contains the processor version number for the cpu core. 56?57 ? reserved, should be cleared. 58 is instruction address space. 0 the processor directs all instruction fe tches to address space 0 (ts = 0 in the relevant tlb entry). 1 the processor directs all instruction fe tches to address space 1 (ts = 1 in the relevant tlb entry). 59 ds data address space. 0 the core directs all data storage accesses to address space 0 (ts = 0 in the relevant tlb entry). 1 the core directs all data storage accesses to address space 1 (ts = 1 in the relevant tlb entry). 60?63 ? reserved, should be cleared. table 7. msr field descriptions (continued) bits name description table 8. processor id register (pir) 32 55 56 63 field ? pid reset 0000_0000_0000_0000_0000_0000 p_cpuid[0:7] r/w read only spr spr 286 table 9. pir field descriptions bits name description 32?55 ? these bits always read as 0. 56?63 pid these bit reflect the values on the p_cpuid[0:7] input signals. table 10. processor version register (pvr) 32 35 36 37 38 43 44 47 48 55 56 59 60 63 field manufacturer id ? type version mbg use major rev mbg id reset 1000 00 01_0001 0010 p_pvrin[16:31] r/w read only spr spr 287
register model UM0434 46/391 the pvr contains fields to specify a particular implementation of an e200z3 family member. interface signals p_pvrin[16:31] provide the contents of bits 48?63. 4.4.4 system version register (svr) the system version register (svr) contains system version information for an e200z3- based soc. svr specifies a particular implementation of an e200z3-based system. 4.5 registers for integer operations this section describes the registers for integer operations. 4.5.1 general purpose registers (gprs) book e implementations provide 32 gprs (gpr0?gpr31) for integer operations. the instruction formats provide 5-bit fields for specifying the gprs for use in executing the instruction. each gpr is a 64-bit register and can contain address and integer data, although all instructions except spe apu vector instructions use and return 32-bit values in gpr bits 32?63. table 11. pvr field descriptions bits name description 32?35 manufacturer id manufacturer id. freescale is 0b1000. 36?37 ? reserved, should be cleared. 38?43 type identifies the processor type. for the e200z3, this field has a value of 0b01_0001. 44?47 version identifies the version of the processor and any optional elements. for e200z3, this field has a value of 0010. 48?55 mbg use distinguishes different system variants; provided by the p_pvrin[16:23] inputs. 56?59 major rev distinguishes different implementations of the version; provided by the p_pvrin[24:27] inputs. 60?63 mbg id provided by the p_pvrin[28:31] input signals. figure 4. system version register (svr) 32 63 field version reset soc-dependent value (determined by p_sysvers[0:31] on the e200z3 core) r/w read only spr spr 1023 table 12. svr field description bits name description 32?63 version distinguishes different system variants, and is provided by the p_sysvers[0:31] inputs.
UM0434 register model 47/391 4.5.2 integer exception register (xer) the xer, shown in table 13 , tracks exception conditions for integer operations. xer fields are described in table 14 . 4.6 registers for branch operations this section describes registers used by book e branch and cr operations. 4.6.1 condition register (cr) cr, shown in table 15 , reflects the result of certain operations and provides a mechanism for testing and branching. table 13. integer exception register (xer) 32 33 34 35 56 57 63 field so ov ca ? number of bytes reset all zeros r/w r/w spr spr 1 table 14. xer field descriptions bits name description 32 so summary overflow. set when an instruction (except mtspr ) sets the overflow bit (ov). so remains set until it is cleared by mtspr[xer] or mcrxr . so is not altered by comp are instructions or other instructions that cannot overflow (except mtspr[xer] and mcrxr ). executing mtspr[xer] with the values 0 for so and 1 for ov clears so and sets ov. 33 ov overflow. x-form add, subtract from, and negate instru ctions with oe=1 set ov if the carry out of bit 32 is not equal to the carry out of bit 33. otherwise, they clear ov to indicate a signed overflow. x-form multiply low word and divide word instruct ions with oe=1 set ov if the result cannot be represented in 32 bits ( mullwo , divwo , and divwuo ) and clear ov otherwise. ov is not altered by compare instructions or other instru ctions that cannot overflow (except mtspr[xer] and mcrxr ). 34 ca carry. add carrying, subtract from carrying, add ex tended, and subtract from extended instructions set ca if there is a carry out of bit 32 and clear it otherwise. ca can be used to indicate unsigned overflow for add and subtract operations that set ca . shift right algebraic word instructions set ca if any 1 bits are shifted out of a negative oper and and clear ca otherwise. compare instructions and instructions that cannot carry (except shift right algebraic word, mtspr[xer] , and mcrxr ) do not affect ca. 35?56 ? reserved, should be cleared. 57?63 numb er of bytes supports emulation of load and store string instructions. specifies the number of bytes to be transferred by a load string indexed or store string indexed instruction.
register model UM0434 48/391 cr bits are grouped into eight 4-bit fields, cr0?cr7, which are set as follows: specified cr fields are set by a move to the cr from a gpr ( mtcrf ). a specified cr field is set by a move to the cr from another cr field ( mcrf ), or from the xer ( mcrxr ). cr0 may be set as the implicit result of an integer instruction. a specified cr field may be set as the result of either an integer or a floating-point compare instruction (including spe and spfp compare instructions). instructions are provided to perform logical operations on individual cr bits and to test individual cr bits. note: book e instructions that access cr bits, such as branch conditional ( bc ), cr logicals, and move to condition register field ( mtcrf ), determine the bit position by adding 32 to the value of the operand. for example, the bi oper and accesses the bit bi + 32, as shown in table 16 . table 15. condition register (cr) 32 35 36 39 40 43 44 47 48 51 52 55 56 59 60 63 field cr 0 cr 1 cr 2 cr 3 cr 4 cr 5 cr 6 cr 7 reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w table 16. bi operand settings for cr fields cr n bits cr bits bi description cr0[0] 32 00000 negative (lt)?set when the result is negative. for spe compare and test instructions: set if the high-order element of r a is equal to the high-order element of r b; cleared otherwise. cr0[1] 33 00001 positive (gt)?set when the result is positive (and not zero). for spe compare and test instructions: set if the low-order element of r a is equal to the low-order element of r b; cleared otherwise. cr0[2] 34 00010 zero (eq)?set when the result is zero . for spe compare and test instructions: set to the or of the result of the compare of the high and low elements. cr0[3] 35 00011 summary overflow (so). copy of xer[so] at the instruction?s completion. for spe compare and test instructions: set to the and of the result of the compare of the high and low elements. cr1[0] 36 00100 negative (lt)?for spe and spfp co mpare and test instructions: set if the high-order element of r a is equal to the high-order element of r b; cleared otherwise. cr1[1] 37 00101 positive (gt)?for spe and spfp co mpare and test instructions: set if the low-order element of r a is equal to the low-order element of r b; cleared otherwise.
UM0434 register model 49/391 cr setting for integer instructions for all integer word instructions with the rc bit defined and set, and for addic. , andi. , and andis. , cr0[32?34] are set by signed comparison of bits 32?63 of the result to zero; cr[35] is copied from the final state of xer[so]. the rc bit is not defined for double-word integer operations. if (target_register) 32?63 < 0 then c 0b100 else if (target_register) 32?63 > 0 then c 0b010 else c 0b001 cr0 c || xer so the value of any undefined portion of the result is undefined, and the value placed into the first three bits of cr0 is undefined. cr 0 bits are interpreted as described in table 17 . cr1[2] 38 00110 zero (eq)?for spe and spfp com pare and test instructions: set to the or of the result of the compare of the high and low elements. cr1[3] 39 00111 summary overflow (so)?for spe and spfp compare and test instructions: set to the and of the result of the compare of the high and low elements. cr n [0] 40 44 48 52 56 60 01000 01100 10000 10100 11000 11100 less than (lt) for integer compare instructions: r a < simm or r b (signed comparison) or r a < uimm or r b (unsigned comparison). for spe and spfp compare and test instructions: set if the high-order element of r a = the high-order element of r b; cleared otherwise. cr n [1] 41 45 49 53 57 61 01001 01101 10001 10101 11001 11101 greater than (gt) for integer compare instructions: r a > simm or r b (signed comparison) or r a > uimm or r b (unsigned comparison). for spe and spfp compare and test instructions: set if the low-order element of r a = the low-order element of r b; cleared otherwise. cr n [2] 42 46 50 54 58 62 01010 01110 10010 10110 11010 11110 equal (eq) for integer compare instructions: r a = simm, uimm, or r b. for spe and spfp compare and test instructions: set to the or of the result of the compare of the high and low elements. cr n [3] 43 47 51 55 59 63 01011 01111 10011 10111 11011 11111 summary overflow (so). for integer compare instructions, this is a copy of xer[so] at the completion of the instruction. for spe and spfp vector compare and test instructions: set to the and of the result of the compare of the high and low elements. table 16. bi operand settings for cr fields (continued) cr n bits cr bits bi description
register model UM0434 50/391 note that cr0 may not reflect the true (infinitely precise) result if overflow occurs. for further details, refer to the eref. cr setting for store conditional instructions cr0 is also set by the integer store conditional instruction, stwcx. . see instruction descriptions in chapter 5: instruction model ,? for details on how cr0 is set. cr setting for compare instructions for compare instructions, a cr field specified by th e bi field in the instruction is set to reflect the result of the comparison, as shown in table 18 . a complete description of how the bits are set is given in the eref . table 17. cr0 field descriptions cr bit name description 32 negative (lt) bit 32 of the result is equal to 1. 33 positive (gt) bit 32 of the result is equal to 0 and at least one of bits 33?63 of the result is non- zero. 34 zero (eq) bits 32?63 of the result are equal to 0. 35 summary overflow (so) this is a copy of the final state of xer[so] at the completion of the instruction. table 18. cr setting for compare instructions cr n bit bit expression cr bits bi description book e 0?2 3?4 cr n [0] 4 * cr0 + lt (or lt ) 4 * cr1 + lt 4 * cr2 + lt 4 * cr3 + lt 4 * cr4 + lt 4 * cr5 + lt 4 * cr6 + lt 4 * cr7 + lt 32 36 40 44 48 52 56 60 000 001 010 011 100 101 110 111 00 less than (lt). for integer compare instructions: r a < simm or r b (signed comparison) or r a < uimm or r b (unsigned comparison). cr n [1] 4 * cr0 + gt (or gt ) 4 * cr1 + gt 4 * cr2 + gt 4 * cr3 + gt 4 * cr4 + gt 4 * cr5 + gt 4 * cr6 + gt 4 * cr7 + gt 33 37 41 45 49 53 57 61 000 001 010 011 100 101 110 111 01 greater than (gt). for integer compare instructions: ra > simm or rb (signed comparison) or r a > uimm or r b (unsigned comparison).
UM0434 register model 51/391 4.6.2 count re gister (ctr) ctr can be used to hold a loop count that can be decremented and tested during execution of branch instructions that contain an appropriately encoded bo field. if the ctr value is 0 before it is decremented, it is ?1 afterward. the entire ctr can hold the branch target address for a branch conditional to ctr ( bcctr x ) instruction. 4.6.3 link register (lr) the link register, shown in table 20 , provides the branch target address for the branch conditional to lr instructions, and it holds the return address after branch and link instructions. cr n [2] 4 * cr0 + eq (or eq ) 4 * cr1 + eq 4 * cr2 + eq 4 * cr3 + eq 4 * cr4 + eq 4 * cr5 + eq 4 * cr6 + eq 4 * cr7 + eq 34 38 42 46 50 54 58 62 000 001 010 011 100 101 110 111 10 equal (eq). for integer compare instructions: r a = simm, uimm, or r b. cr n [3] 4 * cr0 + so (or so ) 4 * cr1 + so 4 * cr2 + so 4 * cr3 + so 4 * cr4 + so 4 * cr5 + so 4 * cr6 + so 4 * cr7 + so 35 39 43 47 51 55 59 63 000 001 010 011 100 101 110 111 11 summary overflow (so). for integer compare instructions, this is a copy of xer[so] at in struction completion. table 18. cr setting for compare instructions (continued) cr n bit bit expression cr bits bi description book e 0?2 3?4 table 19. count register (ctr) 32 63 field count value reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 9
register model UM0434 52/391 lr contents are read into a gpr using mfspr . the contents of a gpr can be written to lr using mtspr . lr[62?63] are ignored by bclr instructions. 4.7 spe and spfp apu registers the spe and spfp include the si gnal processing and embedded floating-point status and control register (spefsc r). the spe implements a 64-bit accumulator t hat is described in chapter 4.7.2: accumula tor (acc) on page 55 .? 4.7.1 signal processing/embedded float ing-point status and control register (spefscr) spefscr, shown in table 21 , is used for st atus and control of spe and embedded floating point instructions. table 22 describes spefscr fields. table 20. link register (lr) 32 63 field link address reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 8 table 21. signal processing and embedded floating point status and control register (spefscr) 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 field sovh ovh fgh fxh finvh fdbzh funfh fovfh ? finxs finvs fdbzs funfs fovfs mode reset 0000_0000_0000_0000 r/w r/w 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 field sov ov fg fx finv fdbz funf fovf ? finxe finve fdbze funfe fovfe frmc reset 0000_0000_0000_0000 r/w r/w spr spr 512 high-word error bits status bits enable bits
UM0434 register model 53/391 table 22. spefscr field descriptions bits name description 32 sovh summary integer overflow high. set whenever an instruction sets ovh and remains set until it is cleared by an mtspr specifying the spefscr. 33 ovh integer overflow high. set whenever an integer or fractional spe instruction signals an overflow in the upper half of the result. 34 fgh embedded floating-point guard bit high. for use by the floating-point round exception handler. it is cleared by a floating-point data exception for the high elements. fgh corresponds to the high element result. fgh is cleared by a scalar floating-point instruction. 35 fxh embedded floating-point sticky bit high. supplied fo r use by the floating-point round exception handler. zeroed if a floating-point data e xception occurred for the high elements. fxh corresponds to the high element result. fxh is cleared by a scalar floating point instruction. 36 finvh embedded floating-point invalid operation/input error high. in mode 0, set if the a or b high element operand of a floating-point instruction is infinity, nan, or denorm, or if the operation is a divide and the high element dividend and divisor are both 0. in mode 1, finvh is set on an ieee754 invalid operation (ieee754-1985 sec7.1) in the high element. cleared by a scalar floating-point instruction. 37 fdbzh embedded floating-point divide by zero high. set when a floating-point divide instruction executes with a high element divisor of 0 and the high element dividend is a finite non-zero number. cleared by a scalar floating-point instruction. 38 funfh embedded floating-point underflow high. set when th e execution of a floating-point instruction results in an underflow in the high element. funfh is cleared by a scalar floating-point instruction. 39 fovfh embedded floating-point overflow high. set when th e execution of a floating-point instruction results in an overflow in the high element. cleared by a scalar floating point instruction. 40?41 ? reserved, should be cleared. 42 finxs embedded floating-point inexact sticky flag. set under one of the following conditions: the execution of a floating-point instruction deliv ers an inexact result for either the low or high element and no floating-point data exception is taken for either element a floating-point instruction causes overflow (f ovf=1 or fovfh=1), but floating-point overflow exceptions are disabled (fovfe=0) a floating-point instruction results in underfl ow (funf=1 or funfh=1), but floating-point underflow exceptions are disabled (funfe=0) and no floating-point data exception occurs. finxs remains set until it is cleared by an mtspr specifying spefscr. 43 finvs embedded floating-point invalid operation sticky flag. set when a floating-point instruction sets finvh or finv. finvs remains set until it is cleared by an mtspr instruction specifying spefscr. 44 fdbzs embedded floating-point divide by zero sticky flag. set when a floating-point divide instruction sets fdbzh or fdbz. fdbzs remains set until it is cleared by an mtspr specifying spefscr. 45 funfs embedded floating-point underflow sticky flag. se t when a floating-point instruction sets funfh or funf. funfs remains set until it is cleared by an mtspr specifying spefscr. 46 fovfs embedded floating-point overflow sticky flag. set w hen a floating-point instruction sets fovfh or fovf. fovfs remains set until it is cleared by an mtspr specifying spefscr.
register model UM0434 54/391 47 mode embedded floating-point operating mode. 0 default hardware results operating mode. the e200z3 supports only mode 0. 1 ieee754 hardware results operating mode (not supported by the e200z3 ). controls the operating mode of the embedded floating-point apu. software should read the value of this bit after writing it to determine whether the implementation supports the selected mode. implementations return the value written if the selected mode is s upported. otherwise, the value read indicates the hardware-supported mode. 48 sov summary integer overflow. set when an instruction se ts ov. sov remains set until it is cleared by an mtspr specifying spefscr. 49 ov integer overflow. set whenever an integer or fracti onal spe instruction signal s an overflow in the low element result. 50 fg embedded floating-point guard bit. used by the fl oating-point round exception handler. cleared if a floating-point data exception occurs for t he low elements. corresponds to the low element result. 51 fx embedded floating-point sticky bit. for use by the floating-point round exception handler. fx is cleared if a floating-point data exception occurs for the low elements. fx corresponds to the low element result. 52 finv embedded floating-point invalid operation/input error. in mode 0, finv is set if the a or b low element operand of a floating-point instruction is infi nity, nan, or denorm, or if the operation is a divide and the low element dividend and divisor are both 0. in mode 1, finv is set on an ieee754 invalid operation (i eee754-1985 sec7.1) in the low element. 53 fdbz embedded floating-point divide by zero. set when a floating-point divide instruction executes with a low element divisor of 0 and the low element dividend is a finite non-zero number. 54 funf embedded floating-point underflow. set when the exec ution of a floating-point instruction results in an underflow in the low element. 55 fovf embedded floating-point overflow. set when the execut ion of a floating-point instruction results in an overflow in the low element. 56 ? reserved, should be cleared. 57 finxe embedded floating-point inexact exception enable. if the exception is enabled, a floating-point round exception is taken under one of the following conditions: for both elements, the result of a floating-point instruction does not result in overflow or underflow, and the result for either element is inexact (fg | fx = 1. fgh | fxh =1) the result of a floating-point instruction does resu lt in overflow (fovf=1 or fovfh=1) for either element, but floating-point overflow exceptions are disabled (fovfe=0) the result of a floating-point instruction result s in underflow (funf=1 or funfh=1), but floating- point underflow exceptions are disabled (funfe=0 ), and no floating-point data exception occurs. 0 exception disabled. 1 exception enabled. 58 finve embedded floating-point invalid operation/input error exception enable. 0 exception disabled. 1 exception enabled. a floating-point data exception is taken if finv or finvh is set by a floating- point instruction. table 22. spefscr field descriptions (continued) bits name description
UM0434 register model 55/391 4.7.2 accumulator (acc) the 64-bit architectural accumulator register holds the results of th e multiply accumulate (mac) forms of spe integer inst ructions. the accumulator allo ws back-to-back execution of dependent mac instructions, as in the inner loops of dsp code such as finite impulse response (fir) filters. the accumulator is partially visible to the programmer in that its results do not have to be explicitly read to use them. instead, they are always copied into a 64-bit destination gpr specified as part of the instruction. however, the accumulator must be explicitly initialized when a new mac loop starts. based upon the type of instruction, an accumulator can hold either a single 64-bit value or a vector of two 32-bit elements. the initialize accumulator instruction ( evmra ) initializes the accumulato r. this instruction is described in the eref . 4.8 interrupt registers this section describes the re gisters for interrupt handling. 59 fdbze embedded floating-point divide by zero exception enable. 0 exception disabled. 1 exception enabled. a floating-poi nt data exception is taken if fdbz or fdbzh is set by a floating-point instruction. 60 funfe embedded floating-point underflow exception enable. 0 exception disabled. 1 exception enabled. a floating-poi nt data exception is taken if funf or funfh is set by a floating-point instruction. 61 fovfe embedded floating-point overflow exception enable. 0 exception disabled. 1 exception enabled. if the exception is enabled, a floating-point data exception is taken if fovf or fovfh is set by a fl oating-point instruction. 62?63 frmc embedded floating-point rounding mode control. 00 round to nearest. 01 round toward zero. 10 round toward +infinity. 11 round toward -infinity. table 22. spefscr field descriptions (continued) bits name description
register model UM0434 56/391 4.8.1 interrupt regist ers defined by book e this section describes the following registers and their fields: chapter : save/restore register 0 (srr0) on page 56 ? chapter : save/restore register 1 (srr1) on page 56 ? chapter : critical save/restore register 0 (csrr0) on page 56 ? chapter : critical save/restore register 1 (csrr1) on page 57 ? chapter : data exception address register (dear) on page 57 ? chapter : interrupt vector pr efix register (ivpr) on page 57 ? chapter : interrupt vector offset registers (ivors) on page 58 ? chapter 4.9: exception syndrome register (esr) on page 59 ? save/restore register 0 (srr0) during a non-critical in terrupt, srr0, shown in table 23 , holds the address of the instruction where the interrupted process should resume. the instruction is interrupt-specific, although for instruction-caused exceptions, the address of the instruction typically causes the interrupt. when rfi executes, instruction execution continues at the address in srr0. srr0 and srr1 are not affected by rfci or rfdi . save/restore register 1 (srr1) srr1, shown in table 24 , is used to save and restore machine state during non-critical interrupts. when a non-critical interrupt is taken, msr contents are placed into srr1. when rfi executes, the contents of srr1 are restored into msr. srr1 bits that correspond to reserved msr bits are also reserved. (see chapter 4.4.1: machine state register (msr) ?.) srr0 and srr1 are not affected by rfci or rfdi . reserved msr bits can be altered by rfi , rfci , or rfdi . critical save/restore register 0 (csrr0) csrr0 is used to save and restore machine state during critical interrupts in the same way srr0 is used for non-critical interrupts: to hold the address of th e instruction to which table 23. save/restore register 0 (srr0) 32 63 field next instruction address reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 26 table 24. save/restore register 1 (srr1) 32 63 field msr state information reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 27
UM0434 register model 57/391 control is passed at the end of the interrupt handler. csrr0, shown in table 25 , holds the address of the instruction where the interrupted process should resume. the instruction is interrupt-specific ; for details, see chapter 6: interrupts and exceptions .? wh en rfci executes, instruction execution continues at the address in csrr0. csrr0 and csrr1 are not affected by rfi or rfdi . critical save/restore register 1 (csrr1) csrr1, shown in table 26 , is used to save and restore machine state during critical interrupts. msr contents are placed into csrr1. when rfci executes, the contents of csrr1 are restored into msr. csrr1 bits that correspond to reserved msr bits are also reserved. (see chapter 4.4.1: machine state register (msr) on page 43 .?) csrr0 and csrr1 are not affected by rfi or rfdi . reserved msr bits can be altered by rfi , rfci , or rfdi . data exception address register (dear) dear, shown in table 27 , is loaded with the effective address of a data access (caused by a load, store, or cache management instruction) that results in an alignment, data tlb miss, or data storage interrupt. interrupt vector prefix register (ivpr) the ivpr, shown in figure 28, is used during interrupt processing to determine the starting address for the software interrupt handler. the value contained in the vector offset field of the ivor selected for a particular interrupt type is concatenated with the value in the ivpr to form an instruction address from which execution is to begin. table 25. critical save/restore register 0 (csrr0) 32 63 field next instruction address reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 58 table 26. critical save/restore register 1 (csrr1) 32 63 field msr state information reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 59 table 27. data exception address register (dear) 32 63 field exception address reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 61
register model UM0434 58/391 ivpr fields are defined in table 29 . interrupt vector offset registers (ivors) ivors, shown in table 30 , hold the quad-word index from the base address provided by the ivpr for each interrupt type. the ivor fields are defined in table 31 . spr numbers corresponding to ivor16?ivor31 are reserved. ivor32?ivor47 and ivor60?ivor63 are reserved. spr numbers for ivor32?ivor63 are allocated for implementation-dependent use (ivor32?ivor34 (spr 528?530) are defined by the eis). ivor assignments are shown in table 32 . table 28. interrupt vector prefix register (ivpr) 32 47 48 63 field vector base ? reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 63 table 29. ivpr field descriptions bits name description 32?47 vector base defines the base location of the vector table, aligned to a 64-kbyte boundary. provides the high-order 16 bits of the location of all interrupt handlers. ivpr || ivor n values are concatenated to form the address of the handler in memory. 48?63 ? reserved, should be cleared. table 30. interrupt vector offset registers (ivor) 32 47 48 59 60 61 63 field ? vector offset ? cs reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr (see table 24 .) table 31. ivor field descriptions bits name setting description 32?47 ? reserved, should be cleared. 48?59 vector offset provides a quad-word index from the bas e address provided by the ivpr to locate an interrupt handler. 60 ? reserved, should be cleared. 61?63 cs context selector (e200z3-specific). when multiple hardware contexts are supported, this field is used to select an operating context for the interrupt handler. this value is loaded into the curct x field of the context control register (ctxcr) as part of the interrupt vectoring process. when multiple hardware contexts are not supported, cs is not implemented and is read as zero.
UM0434 register model 59/391 4.9 exception syndro me register (esr) the esr, shown in table 33 , provides a syndrome to distinguish exceptions that can generate the same interrupt type. the e200z3 adds implementation-specific bits to this register. note: esr information is incomp lete, so system software may need to identify the type of instruction that caused the interrupt and exam ine the tlb entry and the esr to identify the exception or exceptions fully. for example, a data storage interrupt can be caused by both a table 32. ivor assignments ivor number spr interrupt type ivor0 400 critical input ivor1 401 machine check ivor2 402 data storage ivor3 403 instruction storage ivor4 404 external input ivor5 405 alignment ivor6 406 program ivor7 407 floating-point unavailable ivor8 408 system call ivor9 409 auxiliary processor unavailable. (defined by the eis but not supported in the e200z3.) ivor10 410 decrementer ivor11 411 fixed-interval timer interrupt ivor12 412 watchdog timer interrupt ivor13 413 data tlb error ivor14 414 instruction tlb error ivor15 415 debug ivor16?ivor31 ? reserved for future architectural use ivor32 528 spe apu unavailable (eis?defined) ivor33 529 spe floating-point data exception (eis?defined) ivor34 530 spe floating-point roun d exception (eis?defined) ivor35?ivor63 ? allocated for implementation-dependent use table 33. exception syndrome register (esr) 32 35 36 37 38 39 40 41 42 43 44 45 46 47 48 55 56 57 58 5 61 62 63 field ? pil ppr ptr fp st ? dlk ilk ap puo bo pie ? spe ? vlemi ? mif xte reset all zeros r/w r/w spr spr 62
register model UM0434 60/391 protection violation exception and a byte-order ing exception. system software must check beyond esr[bo], such as the state of msr[pr] in srr1 and the tlb entry page protection bits, to determine whether a prot ection violation also occurred. the esr fields are described in table 34 . 4.9.1 vle mode inst ruction syndrome esr[vlemi] indicates when an interrupt is caus ed by a vle instruction. this syndrome bit is set on an exception associated with execution or attempted execution of a vle instruction. this bit is upda ted for the interrupt types in table 34 . table 34. esr field descriptions bits name description asso ciated interrupt type 32?35 ? reserved, should be cleared. ? 36 pil illegal instruction exception program 37 ppr privileged instruction exception program 38 ptr trap exception program 39 fp floating-point operation alignmen t, data storage, data tlb, program 40 st store operation alignment, data storage, data tlb 41 ? reserved, should be cleared. ? 42 dlk data cache locking (1) data storage 43 ilk instruction cache locking data storage` 44 ap auxiliary processor operation. (unused in the e200z3) alignment, data storage, data tlb, program 45 puo unimplemented operation exception program 46 bo byte ordering exception data storage 47 pie program imprecise exception. unused in the e200z3 (reserved, should be cleared.) ? 48?55 ? reserved, should be cleared. ? 56 spe spe apu operation spe unavailable, spe fl oating-point data exception, spe floating-p oint round exception, alignment, data storage, data tlb 57 ? reserved, should be cleared. ? 58 vlem i vle mode instruction spe unavailable, spe fl oating-point data exception, spe floating-p oint round exception, data storage, data tlb, instruction storage, alignment, program, and system call 59?61 ? reserved, should be cleared. ? 62 mif misaligned instruction fetch instruction storage, instruction tlb 63 xte external termination error (precise) data storage, instruction storage 1. when optional cache is present. unused on e200z3.
UM0434 register model 61/391 4.9.2 misaligned inst ruction fetch syndrome the esr[mif] bit indicates an instruction storage interrupt caused by an attempt to fetch an instruction from a book e page that is not aligned on a word boundary. the fetch may have been caused by one of the following: execution of a branch to lr instruction with lr[62]=1 a branch to ctr instruction with ctr[62]=1 execution of an rfi or se_rfi instruction with srr0[62]=1 execution of an rfci or se_rfci instruction with csrr0[62]=1 execution of an rfdi or se_rfdi instruction with dsrr0[62]= 1, where the destination address corresponds to an instruction page not marked as a vle page. the esr[mif] bit also indicates an instruction tlb interrupt caused by a tlb miss on the second half of a misaligned 32-bit vle instruction. srr0 points to the first half of the instruction, which resides on the previous page from the miss at page offset 0xffe. the itlb handler may need to note that the miss corresponds to the next page, although mmu mas2 contents correctly reflect the page corresponding to the miss. 4.9.3 precise external termination error syndrome the esr[xte] bit indicates a precise external termination error dsi or isi interrupt caused by an instruction. this syndrome bit is set on an external termination error exception reported in a precise way via a dsi or isi as opposed to a machine check. 4.9.4 e200z3 specific in terrupt registers in addition to the book e-defined interrupt registers, the e200z3 implements dsrr0 and dsrr1 to facilitate handling de bug interrupts and the eis- defined mcsr to facilitate handling machine check interrupts. debug save/restore register 0 (dsrr0) during a debug interrupt, dsrr0, shown in table 35 , holds the address of the instruction where the interrupted process should resume. the instruction is interrupt-specific; see chapter 6.6.16: debug interrupt (ivor15) on page 180 ,? and particularly table 141 . when rfdi executes, instruction execution continues at the address in dsrr0. dsrr0 and dsrr1 are not affected by rfi or rfci . debug save/restore register 1 (dsrr1) dsrr1, shown in table 36 , saves and restores machine state during debug interrupts. msr contents are placed into dsrr1. when rfdi executes, the contents of dsrr1 are restored into msr. dsrr1 bits that correspond to reserved msr bits are also reserved. (see table 35. debug save/restore register 0 (dsrr0) 32 63 field next instruction address reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 574
register model UM0434 62/391 chapter 4.4.1: machine state register (msr) on page 43 .?) dsrr0 and dsrr1 are not affected by rfi or rfci . reserved msr bits can be altered by rfi , rfci , or rfdi . machine check syndrome register (mcsr) when the core complex takes a machine check interrupt, it updates the machine check syndrome register (mcsr) to differentiate between machine check conditions. the mcsr is shown in table 37 . mcsr fields, described in table 38 , indicate whether the source of a machine check condition is recoverable. when an mcsr bit is set, the core complex asserts p_mcp_out for system information. table 36. debug save/restore register 1 (dsrr1) 32 63 field msr state information reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 575 table 37. machine check syndrome register (mcsr) 32 33 34 35 36 37 58 59 60 61 6263 field mcp ? cp_perr cperr excp_er r ? bus_irerr bus_drer r bus_wrer r ? reset all zeros r/w r/w spr spr 572 table 38. mcsr field descriptions bits name description recoverable 32 mcp machine check input signal maybe 33 ? reserved, should be cleared. ? 34 cp_perr cache push parity error unlikely 35 cperr cache parity error precise 36 excp_err isi, itlb, or bus error on first instruction fetch for an exception handler precise 37?58 ? reserved, should be cleared. ? 59 bus_irerr read bus error on instruction fetch unlikely 60 bus_drerr read bus error on data load unlikely 61 bus_wrerr write bus error on buffered store or cache line push unlikely 62?63 ? reserved, should be cleared. ?
UM0434 register model 63/391 4.10 software use sprs (s prg0?sprg7 and usprg0) software use sprs (sprg0 - sprg7 and usprg0, shown in table 39 ) have no defined functionality: sprg0 - sprg2 - accessible only in supervisor mode. sprg3 - written only in supervisor mode. it is readable in supervisor mode, but whether it can be read in user mode depends on the implementation. it is not readable in user mode on th e200z3. sprg4 - sprg7 - written only in supervisor mode. they are readable in supervisor or user mode. usprg0 - accessible in supervisor or user mode. software use sprs are read into a gpr using mfspr and are written using mtspr . 4.11 timer registers the time base (tb), decrementer (dec), fixed-interval timer (fit), and watchdog timer provide timing functions for the system. the re lationship of these timers to each other is shown in figure l . table 39. software use sprs (sprg0?sprg7 and usprg0) 32 63 field software determined information reset undefined on m_por assertion, unchanged on p_reset_b assertion spr r/w sprg0 272 read/write supervisor sprg1 273 read/write supervisor sprg2 274 read/write supervisor sprg3 259 read only user (1) /supervisor 1. user-mode access to sprg3 is defined by book e as implementation-dependent. it is not supported in the e200z3. 275 read/write supervisor sprg4 260 read only user/supervisor 276 read/write supervisor sprg5 261 read only user/supervisor 277 read/write supervisor sprg6 262 read only user/supervisor 278 read/write supervisor sprg7 263 read only user/supervisor 279 read/write supervisor usprg0 256 read/write user/supervisor
register model UM0434 64/391 figure 5. relationship of timer facilities to the time base 1. watchdog timer events based on one of the tb bi ts selected by the book e?defined tcr[wp] concatenated with the eis-defined tcr[wpext] (wpext||wp). 2. fixed-interval timer events based on one of tb bits selected by the book e?defined tcr[fp] concatenated with the eis-defined tcr[fpext] (fpext||fp). the decrementer, updated at the same rate as the tb, signals an exception after a specified period unless one of the following occurs: ? software alters dec in the interim. ? the tb update frequency changes. the dec is typically used as a general-purpose software timer. the time base for the tb and dec is selected by the time base enable (tben) and select time base clock (sel_tbc lk) bits in hid0, as follows: ? if hid0[tben] = 1 and hid0[sel_tbclk] = 0, the time base and decrementer are based on processor clock. ? if hid0[tben] = 1 and hid0[sel_tbclk] = 1, the time base and decrementer are based on the p_tbclk input. software can select one from of four tb bits to signal a fixed-interval interrupt when the bit transitions from 0 to 1. it typically triggers periodic system maintenance functions. bits that can be selected are implementation-dependent. the watchdog timer, also a selected tb bit, signals a critical exception when the selected bit transitions from 0 to 1. it is typically used for system error recovery. if software does not respond in time to the initial interrupt by clearing the associated status bits in the tsr before the next expiration of the watchdog timer interval, a watchdog timer-generated processor reset may result, if so enabled. all timer facilities must be initialized during start-up. 4.11.1 timer control register (tcr) tcr, shown in table 40 , provides control information fo r the cpu timer facilities. the eref describes the tcr in detail. tcr[wrc] functions are implementation-dependent. in addition, the core implements two implem entation-specific fi elds, tcr[wpext] and tcr[fpext]. timer clock time base (incrementer) decrementer event = 0/1 detect 31 decar 0 auto-reload 31 0 tbl 31 0 tbu watchdog timer events based on one of the tb bits selected by the book e?defined tcr[wp] concatenated with the eis-defined tcr[wpext] (wpextiiwp) fixed-interval timer events based on one of tb bits selected by the book e?defined tcr[fp] concatenated with the eis-defined tcr[fpext] (fpextiifp) dec (time base clock) core_tbclk
UM0434 register model 65/391 the tcr fields are described in table 41 . table 40. timer control register (tcr) 323334 35 36 37 3839 40 41 4243 46 47 50 51 63 field wp wrc wie die fp fie are ? wpext fpext ? reset all zeros r/w r/w spr spr 340 table 41. tcr field descriptions bits name description 32?33 wp watchdog timer period, when concatenated with wpext, specifies one of 64 bit locations of the time base used to signal a watchdog timer exception on a transition from 0 to 1. tcr[wpext]||tcr[wp] == 000000 se lects tbu[32] (msb of tbu). tcr[wpext]||tcr[wp] == 111111 sele cts tbl[63] (lsb of tbl). 34?35 wrc watchdog timer reset control. software can set wrc but cannot clear it except by a software- induced reset. after wrc is written to a non-zero value, software can no longer alter it. 00 no watchdog timer reset can occur. 01 force processor checkstop on second time-out of the watchdog timer. 10 assert processor reset output ( p_resetout_b ) on second time-out of watchdog timer. 11 reserved. 36 wie watchdog timer interrupt enable. 0 watchdog timer interrupts disabled. 1 watchdog timer interrupts enabled. 37 die decrementer interrupt enable. 0 decrementer interrupts disabled. 1 decrementer interrupts enabled. 38?39 fp fixed-interval timer peri od. when concatenated wi th fpext, specifies one of 64 bit locations of the time base to signal a fixed-interval timer exception on a transition from 0 to 1. tcr[fpext]||tcr[fp] == 000000 se lects tbu[32] (msb of tbu). tcrfp[ext]||tcr[fp] == 111111 se lects tbl[63] (lsb of tbl). 40 fie fixed-interval interrupt enable. 0 fixed-interval interrupts disabled. 1 fixed-interval interrupts enabled. 41 are auto-reload enable. controls whether the value in decar is reloaded into dec when the dec value reaches 0000_0001. 0 auto-reload disabled. 1 auto-reload enabled. 42 ? reserved, should be cleared. 43?46 wpext watchdog timer period extension (see above description for wp). wpext | wp select one of the 64 tb bits used to signal a watchdog timer exception.
register model UM0434 66/391 4.11.2 timer status register (tsr) tsr, shown in table 42 , provides status information for the cpu timer facilities. eref describes the tsr in detail. tsr[wrs] is defined as implementation-dependent. register fields designated as write-1-to-clear are cleared only by writing ones to them. writing zeros to them has no effect. the tsr fields are described in table 43 . 47?50 fpext fixed-interval timer period extens ion (see description for fp). f pext | fp select one of the 64 tb bits used to signal a fixed-interval timer exception. 51?63 ? reserved, should be cleared. table 41. tcr field descriptions (continued) bits name description table 42. timer status register (tsr) 32 33 34 35 36 37 38 63 field enw wis wrs dis fis ? reset 0b(00||wrs)_0000_0000_0000_0000_0000_0000_0000 r/w read/clear spr spr 336 table 43. timer status register field descriptions bits name description 32 enw enable next watchdog time. when a watchdog timer time-out occurs while wis = 0 and the next watchdog time-out is enabled (enw = 1), a watchdog timer exception is generated and logged by setting wis. this is a watchdog timer first time ou t. a watchdog timer interrupt occurs if enabled by tcr[wie] and msr[ce]. to avoid another watchdog timer interrupt when msr[ce] is reenabled (assuming tcr[wie] is not cleared instead), the interrupt handler must reset tsr[wis] by executing an mtspr , setting wis and any other bits to be cl eared and a 0 in all other bits. the data written to the tsr is not direct data, but is a mask. a 1 causes the bit to be cleared; a 0 has no effect. 0 action on next watchdog timer time-out is to set tsr[enw]. 1 action on next watchdog timer time-out is governed by tsr[wis]. 33 wis watchdog timer interrupt status. see the enw description for details on how wis is used. 0 no watchdog timer event. 1 a watchdog timer event. when msr[ce] = 1 and tcr[wie] = 1, a watchdog timer interrupt is taken. 34?35 wrs watchdog timer reset status. 00 no second time-out of watchdog timer. 01 force processor checkstop on second time-out of watchdog timer. 10 assert processor reset output ( p_resetout_b ) on second time-out of watchdog timer. 11 reserved.
UM0434 register model 67/391 note: the tsr can be read using mfspr r d ,tsr . the tsr cannot be directly written. instead, tsr bits corresponding to 1 bits in gpr( r s) can be cleared using mtspr tsr,r s. 4.11.3 time base (tbu and tbl) the time base (tb), seen in table 44 , is composed of two 32-bit registers, the time base upper (tbu) concatenated on the right with the time base lower (tbl). the time base registers provide timing functions for the system and are enabled by setting hid0[tben]. the decrementer (dec) updates at the same frequency, which is selected in hid0[sel_tbclk]. tb is a volatile resource and must be initialized during start-up. for details, see section 4.11: timer registers on page 63 .? the tb is interpreted as a 64-bit unsigned integer that is periodically incremented. each increment adds 1 to the least-significant bit. t he frequency at which the integer is updated is implementation-dependent. tbl increments until its value becomes 0xffff_ffff (2 32 ? 1). at the next increment, its value becomes 0x0000_0000 and tbu is incremented. this process continues until the tbu value becomes 0xffff_ffff and the tbl value becomes 0xffff_ffff (tb is interpreted as 0xffff_ffff_ffff_ffff (2 64 ? 1)). at the next increment, the tbu value becomes 0x0000_0000 and the tbl value becomes 0x0000_0000. there is no interrupt (or any other indication). the period depends on the driving frequency. for example, if tb is driven by 100 mhz divided by 32, the tb period is as follows: 36 dis decrementer interrupt status. 0 no decrementer event. 1 decrementer event. when msr[ee] = tcr[die] = 1, a decrementer interrupt is taken. 37 fis fixed-interval timer interrupt status. 0 no fixed-interval timer event. 1 fixed-interval timer event. when msr[ee] = 1 and tcr[fie] = 1, a fixed-interval timer interrupt is taken. 38?63 ? reserved, should be cleared. table 43. timer status register field descriptions (continued) bits name description table 44. time base upper/lower registers (tbu/tbl) 32 63 32 63 field tbu tbl reset undefined on m_por assertion, unchanged on p_reset_b assertion undefined on m_por assertion, unchanged on p_reset_b assertion r/w user read/supervisor write user read/supervisor write spr 269 read/285 write 268 read/284 write
register model UM0434 68/391 the tb is implemented to satisfy the following requirements: loading a gpr from the tb has no effect on the accuracy of the tb. storing a gpr to the tb replaces the value in the tb with the value in the gpr. book e does not specify a relationship between the tb update frequency and other frequencies, such as the cpu clock or bus clock. the tb update frequency does not have to be constant. one of the following is required to ensure that system software can keep time of day and operate interval timers: the system provides an (implementation-dependent) interrupt to software when the update frequency of the tb changes and a way to determine the current update frequency. the update frequency of the tb is under the control of system software. note: disabling the tb or making reading the time base privileged prevents the tb from being used to implement a covert channel in a secu re system. if the operat ing system initializes the tb on power-on to some reasonable value and the update frequency of the tb is constant, the tb can be used as a source of val ues that increase at a constant rate, such as for time stamps in trace entries. even if the update frequency is not constant, values read from the tb are monotonically increasing (except when the tb wraps from 2 64 ? 1 to 0). if a trace ent ry is recorded each time the update frequency changes, the sequen ce of tb values can be post-processed to become actual time values. successive readings of the tb may return identical values. the tb is useful for timing reasonably short sequences of code (a few hundred instructions) and for low-overhead time stamps for tracing. 4.11.4 decrementer register dec, shown in table 45 , is a decrementing counter that is enabled by setting hid0[tben]. the decrementer and time base update at the same frequency, which is selected in hid0[sel_tbclk]. it provides way to signal a decrementer interrupt after a specified period unless one of the following occurs: software alters dec in the interim. the tb update frequency changes. dec is typically used as a general-purpose software timer. the decrementer auto-reload register (decar) automatically reloads a programmed value into dec. t tb 2 64 32 100 mhz ----------------------- -
UM0434 register model 69/391 4.11.5 decrementer auto-r eload register (decar) if the auto-reload function is enabled (tcr[are] = 1), the auto-reload value in decar, shown in table 46 , is written to dec when dec decrements from 0x0000_0001 to 0x0000_0000. writing dec with zeros by using an mtspr does not automatically generate a decrementer interrupt. 4.12 debug registers this section describes software-accessible debug registers for use by special debug tools and debug software, not by general application code. software access to these registers is conditioned by the external debug mode control bit (dbcr0[edm]), which can be set by the hardware debug port. if dbcr0[edm] is set, software is prevented from modifying debug register values. execution of an mtspr instruction targeting a debug register does not cause modifications to occur. in addition, since the external debugger hardware may be manipulating debug register values, the state of these registers is not guaranteed to be consistent if read by software with an mfspr instruction other than dbcr0[edm]. 4.12.1 debug address and value registers instruction address compare registers iac1?iac4 hold instruction addresses for comparison. in addition, iac2 and iac4 hold mask information for iac1 and iac3, respectively, when address bit match compare modes are selected. note: during instruction address comparisons, the low-order two address bits of the instruction address and the corresponding iac register are ignored. data address compare registers dac1 and dac2 hold data access addresses for comparison. in addition, dac2 holds mask information for dac1 when address bit match compare mode is selected. instruction address compare registers (iac1?iac4) iac1?iac4, shown in table 47 , hold instruction addresses for comparison. table 46. decrementer auto-reload register (decar) 32 63 field decrementer auto-reload value reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 54 table 47. instruction address compare registers (iac1?iac4) 32 616263 field instruction address ? reset all zeros r/w r/w spr spr 312 (iac1); spr 313 (iac2); spr 314 (iac3); spr 315 (iac4)
register model UM0434 70/391 a debug event can be enabled when there is an attempt to execute an instruction from an address in one of the following contexts: in an iac inside or outside a range specified by iac1 and iac2 inside or outside a range specified by iac3 and iac4 to blocks of addresses specified by the combination of the iac1 and iac2 to blocks of addresses specified by the combination of the iac3 and iac4. because all instruction addresses must be word-aligned, the two low-order bits of the iacs are reserved and do not participate in the comparison with the instruction address. data address compare registers (dac1?dac2) the data address compare 1 register (dac1) and data address compare 2 register (dac2), shown in table 48 , are each 32 bits. a debug event can be enabled by loads, stores, or cache operations to an address specified in either dac1 or dac2, inside or outside a range specified by the dac1 and dac2, or blocks of addresses specified by the combination of the dac1 and dac2. the contents of dac1 or dac2 are compared to the address generated by a data access instruction. 4.12.2 debug counter register (dbcnt) the debug counter register (dbcnt) contains two 16-bit counters (cnt1 and cnt2) that can be configured to operate independently or concatenated into a single 32-bit counter. each counter can be configured to count down (decrement) when one or more count- enabled events occur. the counters operate regardless of whether counters are enabled to generate debug exceptions. when a count value reaches zero, a debug count event is signaled and a debug event can be generated (if enabled). upon reaching zero, the counter is frozen. a debug counter signals an event on the transition from a value of one to a final value of zero. loading a value of zero into the counter prevents the counter from counting. the debug counter is configured by the contents of dbcr3. dbcnt is shown in table 49 . table 48. data address compare registers (dac1?dac2) 32 63 field data address reset all zeros r/w r/w spr spr 316 (dac1); spr 317 (dac2) table 49. dbcnt register 32 47 48 63 field cnt1 cnt2 reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 562
UM0434 register model 71/391 refer to section : debug control register 3 (dbcr3) on page 77 ,? for details on updates to the dbcnt register. there are restrictions on how the dbcnt and dbcr3 register are modified when one or more counters are enabled. 4.12.3 debug control and stat us registers (dbcr0?dbcr3) dbcr0?dbcr3 enable debug events, reset the processor, control timer operation during debug events and set the debug mode of the processor. the debug status register (dbsr) records debug exceptions while internal or external debug mode is enabled. to ensure that any alterations enabling/disabling debug events are effective, the e200z3 requires that a context synchronizing instruction follow an mtspr that updates a dbcr or dbsr. the context synchronizing instruction may or may not be affected by the alteration. typically, an isync is used to create a synchronization boundary beyond which it can be guaranteed that the newly written control values are in effect. for watchpoint generation and counter operation, configuration settings in dbcr1?dbcr3 are used, even though the corresponding events can be disabled (via dbcr0) from setting dbsr flags. debug control register 0 (dbcr0) dbcr0 is used to enable debug modes and cont rols which debug events are allowed to set dbsr flags. the e200z3 adds bits to this register, as shown in table 50 . table 51 provides field definitions for dbcr0. table 50. dbcr0 register 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 field edm idm rst icmp brt irpt trap iac1 iac2 iac3 iac4 dac1 dac2 reset all zeros (1) 1. dbcr0[edm] is affected by j_trst_b or m_por assertion, and while in the test_logic_reset state, but not by p_reset_b . all other bits are reset by processor reset p_reset_b as well as by m_por . r/w r/w 48 49 52 53 54 55 56 57 58 59 62 63 ret ? devt1 devt2 dcnt1 dcnt2 cirpt cret vles ? ft reset all zeros 1 r/w r/w spr spr 308
register model UM0434 72/391 table 51. dbcr0 field descriptions bits name description 32 edm external debug mode. for software, this bit is read-only. software can use edm to determine whether external debug has control over debug registers. the hardware debugger must set edm before other dbcr0 bits (and other debug registers) can be altered. on the initial setting of edm, all other bits are unchanged. edm is writable only through the once port. 0external debug mode is disabled. internal debug events not mapped into external debug events. 1external debug mode is enabled. events do not cause the cpu to vector to interrupt code. software is not permitted to write to debug registers (dbcr0 ? dbcr3, dbsr, dbcnt, iac1 ? iac4, dac1?dac2). note: dbsr status bits should be cleared before external debug mode is disabled to avoid internal imprecise debug interrupts. 33 idm internal debug mode. 0 debug exceptions are disabled. debug events do not affect dbsr. 1 debug exceptions are enabled. enabled deb ug events update the dbsr. if msr[de] = 1, a debug event or the recording of an earlier debug event in the dbsr when msr[de] was cleared causes a debug interrupt. 34?35 rst reset control. 00 no function. 01 reserved. 10 p_resetout_b set by debug reset control. allows exte rnal device to initiate processor reset. 11 reserved. 36 icmp instruction complete debug event enable. 0 icmp debug events are disabled. 1 icmp debug events are enabled. 37 brt branch taken debug event enable. 0 brt debug events are disabled. 1 brt debug events are enabled. 38 irpt interrupt taken debug event enable. 0 irpt debug events are disabled. 1 irpt debug events are enabled. 39 trap trap taken debug event enable. 0 trap debug events are disabled. 1 trap debug events are enabled. 40 iac1 instruction address compare 1 debug event enable. 0 iac1 debug events are disabled. 1 iac1 debug events are enabled. 41 iac2 instruction address compare 2 debug event enable. 0 iac2 debug events are disabled. 1 iac2 debug events are enabled. 42 iac3 instruction address compare 3 debug event enable. 0 iac3 debug events are disabled. 1 iac3 debug events are enabled.
UM0434 register model 73/391 43 iac4 instruction address compare 4 debug event enable. 0 iac4 debug events are disabled. 1 iac4 debug events are enabled. 44?45 dac1 data address compare 1 debug event enable 00 dac1 debug events are disabled. 01 dac1 debug events are enabled only for store - type data storage accesses. 10 dac1 debug events are enabled only for load - type data storage accesses. 11 dac1 debug events are enabled for load - type or store - type data storage accesses. 46?47 dac2 data address compare 2 debug event enable. 00 dac2 debug events are disabled. 01 dac2 debug events are enabled only for store - type data storage accesses. 10 dac2 debug events are enabled only for load - type data storage accesses. 11 dac2 debug events are enabled for load - type or store - type data storage accesses. 48 ret return debug event enable. 0 ret debug events are disabled. 1 ret debug events are enabled. 49?52 ? reserved. 53 devt1 external debug event 1 enable. 0 devt1 debug events are disabled. 1 devt1 debug events are enabled. 54 devt2 external debug event 2 enable. 0 devt2 debug events are disabled. 1 devt2 debug events are enabled. 55 dcnt1 debug counter 1 debug event enable. 0 counter 1 debug events are disabled. 1 counter 1 debug events are enabled. 56 dcnt2 debug counter 2 debug event enable. 0 counter 2 debug events are disabled. 1 counter 2 debug events are enabled. 57 cirpt critical interrupt taken debug event enable. 0 cirpt debug events are disabled. 1 cirpt debug events are enabled. 58 cret critical return debug event enable. 0 cret debug events are disabled. 1 cret debug events are enabled. 59 vles vle status, set if an icmp, brt, trap, ret, cret, iac, or dac debug event occurred on a vle instruction. undefined for irpt, cirpt, devt[1,2], dcnt[1,2], and ude events. 60?62 ? reserved. 63 ft freeze timers on debug event. 0 timebase timers are unaffected by set dbsr bits. 1 disable clocking of timebase timers if any dbsr bit is set (except mrr or cnt1trg). table 51. dbcr0 field descriptions (continued) bits name description
register model UM0434 74/391 debug control register 1 (dbcr1) dbcr1, shown in table 52 , is used to configure instruction address compare operation. table 53 describes debug control register 1 fields. table 52. debug control register 1 (dbcr1) 32 33 34 35 36 37 38 39 40 41 42 47 48 49 50 51 52 53 54 55 56 57 58 63 field iac1usiac1eriac2usiac2eriac12m ? iac3usiac3eriac4usiac4eriac34m ? reset all zeros r/w r/w spr spr 309 table 53. dbcr1 field descriptions bits name description 32?33 iac1us instruction address compare 1 user/supervisor mode. 00 ac1 debug events are not affected by msr[pr]. 01 reserved. 10 ac1 debug events can occur only if msr[pr] = 0 (supervisor mode). 11 ac1 debug events can occur only if msr[pr] = 1 (user mode). 34?35 iac1er instruction address compare 1 effective/real mode. 00 ac1 debug events are based on effective address. 01 unimplemented in the e200z3 (book e real address compare), no match can occur. 10 ac1 debug events are based on effective address and can occur only if msr[is] = 0. 11 ac1 debug events are based on effective address and can occur only if msr[is] = 1. 36?37 iac2us instruction address compare 2 user/supervisor mode. 00 ac2 debug events are not affected by msr[pr]. 01 reserved. 10 ac2 debug events can occur only if msr[pr] = 0 (supervisor mode). 11 ac2 debug events can occur only if msr[pr] = 1 (user mode). 38?39 iac2er instruction address compare 2 effective/real mode. 00 ac2 debug events are based on effective address. 01 unimplemented in the e200z3 (book e real address compare), no match can occur. 10 ac2 debug events are based on effective address and can occur only if msr[is] = 0. 11 ac2 debug events are based on effective address and can occur only if msr[is] = 1.
UM0434 register model 75/391 40?41 iac12m instruction address compare 1/2 mode. 00 exact address compare. iac1 debug events can occur only if the address of the instruction fetch is equal to the value specified in iac1. iac2 debug events can occur only if the address of the instruction fetch is equal to the value specified in iac2. 01 address bit match. iac1 debug events can occu r only if the address of the instruction fetch anded with the contents of iac2 is equal to the contents of iac1 , also anded with the contents of iac2. iac2 debug events do not occur. iac1us and iac1er settings are used. 10 inclusive address range compare. iac1 debug events can occur only if the address of the instruction fetch is greater than or equal to the value specified in iac1 and less than the value specified in iac2. iac2 debug events do not occur. iac1us and iac1er settings are used. 11 exclusive address range compare. iac1 debug events can occur only if the address of the instruction fetch is less than the value specified in iac1 or is greater than or equal to the value specified in iac2. iac2 debug events do not occur. iac1us and iac1er settings are used. 42?47 ? reserved 48?49 iac3us instruction address compare 3 user/supervisor mode. 00 ac3 debug events are not affected by msr[pr]. 01 reserved. 10 ac3 debug events can occur only if msr[pr] = 0 (supervisor mode). 11 ac3 debug events can occur only if msr[pr] = 1 (user mode). 50?51 iac3er instruction address compare 3 effective/real mode. 00 ac3 debug events are based on effective address. 01 unimplemented in the e200z3 (book e real address compare), no match can occur. 10 ac3 debug events are based on effective address and can occur only if msr[is] = 0. 11 ac3 debug events are based on effective address and can occur only if msr[is] = 1. 52?53 iac4us instruction address compare 4 user/supervisor mode. 00 ac4 debug events are not affected by msr[pr]. 01 reserved. 10 iac4 debug events can occur only if msr[pr] = 0 (supervisor mode). 11 iac4 debug events can occur only if msr[pr] = 1 (user mode). 54?55 iac4er instruction address compare 4effective/real mode. 00 ac4 debug events are based on effective address. 01 unimplemented in the e200z3 (book e real address compare), no match can occur. 10 iac4 debug events are based on effective address and can occur only if msr[is] = 0. 11 iac4 debug events are based on effective address and can occur only if msr[is] = 1. table 53. dbcr1 field descriptions (continued) bits name description
register model UM0434 76/391 debug control register 2 (dbcr2) dbcr2, shown below is used to configure data address compare operations. table 54 describes dbcr2 fields. 56?57 iac34m instruction address compare 3/4 mode. 00 exact address compare. iac3 debug events can occur only if the address of the instruction fetch is equal to the value specified in iac3. iac4 debug events can occur only if the address of the instruction fetch is equal to the value specified in iac4. 01 address bit match. iac3 debug events can occu r only if the address of the instruction fetch anded with the contents of iac4 is equal to the contents of iac3 , also anded with the contents of iac4. iac4 debug events do not occur. iac3us and iac3er settings are used. 10 inclusive address range compare. iac3 debug events can occur only if the address of the instruction fetch is greater than or equal to the value specified in iac3 and less than the value specified in iac4. iac4 debug events do not occur. iac3us and iac3er settings are used. 11 exclusive address range compare. iac3 debug events can occur only if the address of the instruction fetch is less than the value specified in iac3 or is greater than or equal to the value specified in iac4. iac4 debug events do not occur. iac3us and iac3er settings are used. 58?63 ? reserved table 53. dbcr1 field descriptions (continued) bits name description 32 33 34 35 36 37 38 39 40 41 42 43 44 63 field dac1us dac1er dac2us dac2er dac12m dac1lnk dac2lnk ? reset all zeros r/w r/w spr spr 310 table 54. dbcr2 field descriptions bits name description 32?33 dac1us data address compare 1 user/supervisor mode. 00 dac1 debug events are not affected by msr[pr]. 01 reserved. 10 dac1 debug events can occur only if msr[pr] = 0 (supervisor mode). 11 dac1 debug events can occur only if msr[pr] = 1 (user mode). 34?35 dac1er data address compare 1 effective/real mode. 00 dac1 debug events are based on effective address. 01 unimplemented in the e200z3 (book e real address compare), no match can occur. 10 dac1 debug events are based on effective address and can occur only if msr[ds] = 0. 11 dac1 debug events are based on effective address and can occur only if msr[ds] = 1. 36?37 dac2us data address compare 2 user/supervisor mode. 00 dac2 debug events are not affected by msr[pr]. 01 reserved 10 dac2 debug events can occur only if msr[pr] = 0 (supervisor mode). 11 dac2 debug events can occur only if msr[pr] = 1 (user mode).
UM0434 register model 77/391 debug control register 3 (dbcr3) dbcr3, shown in table 55 , is an e200z3 implementation-specific register to enable and configure the debug counter and debug counter events. for counter operation, the specific debug events that cause counters to decrement are specified in dbcr3. note: corresponding events do not need to be (and probably should not be) enabled in dbcr0. the iac1?iac4 and dac1?dac2 control fields in dbcr0 are ignored for counter operations and the control fields in dbcr3 determine when counting is enabled. dbcr1 and dbcr2 control fields are also used to determine the configuration of iac1?iac4 and dac1?dac2 operations for counting, even though the setting of bits in dbsr by corresponding events can be disabled via dbcr0. multiple count-enabled events that occur during execution of an instruction typically cause only one decrement of a counter. for example, if more than one iac or dac register hits and is enabled for counting, only one count can occur per counter. during execution of lmw and stmw instructions, multiple dac n hits can occur. if the instruction is not interrupted before completion, a single decrement of a counter occurs. 38?39 dac2er data address compare 2 effective/real mode. 00 dac2 debug events are based on effective address. 01 unimplemented in the e200z3 (book e real address compare), no match can occur. 10 dac2 debug events are based on effective address and can occur only if msr[ds] = 0. 11 dac2 debug events are based on effective address and can occur only if msr[ds] = 1. 40?41 dac12m data address compare 1/2 mode. 00 exact address compare. dac1 debug events can occur only if the address of the data access is equal to the value specified in dac1. dac2 debug events can occur only if the address of the data access is equal to the value specified in dac2. 01 address bit match. dac1 debug events can occur only if the address of the data access anded with the contents of dac2 is equal to the contents of dac1, also anded with the contents of dac2. dac2 debug events do not o ccur. dac1us and dac1er settings are used. 10 inclusive address range compare. dac1 debug events can occur only if the address of the data access is greater than or equal to the value specified in dac1 and less than the value specified in dac2. dac2 debug events do not occur. dac1us and dac1er settings are used. 11 exclusive address range compare. dac1 debu g events can occur only if the address of the data access is less than the value specified in dac1 or is greater than or equal to the value specified in dac2. dac2 debug events do not occur. dac1us and dac1er settings are used. 42 dac1lnk data address compare 1 linked. 0 no effect. 1 dac1 debug events are linked to iac1 debug events. iac1 debug events do not affect dbsr. when linked to iac1, dac1 debug events are conditioned based on whether the instruction also generated an iac1 debug event. 43 dac2lnk data address compare 2 linked 0 no effect. 1dac 2 debug events are linked to iac3 debug events. iac3 debug events do not affect dbsr. when linked to iac3, dac2 debug events are conditioned based on whether the instruction also generated an iac3 debug event. dac2 can only be linked if dac12m specifies exact address compare because dac2 debug events are not generated in the other compare modes. 44?63 ? reserved for data value compare control (not supported by the e200z3). table 54. dbcr2 field descriptions (continued) bits name description
register model UM0434 78/391 note: if the counters operate independently, both may count for the same instruction. the debug counter register (dbcnt) is configured by dbcr3[config] to operate either as separate 16-bit counter 1 and counter 2 or as a combined 32-bit counter (using control bits in dbcr3 for counter 1). counters are enabled when any of their respective count enable event control bits are set and either dbcr0 or dbcr0[edm] is set. counter 1 can be configured to count down on a number of different debug events. counter 2 is also configurable to count down on instruction complete, instruction or data address compare events, and external events. special capability is provided for counter 1 to be triggered to begin counting down by a subset of events (iac1, iac3, dac1r, dac1w, devt1, devt2, and counter 2). when one or more of the counter 1 trigger bits is set (iac1t1, iac3t1, dac1rt1, dac1wt1, devt1t1, devt2t1, cnt2t1), counter 1 is frozen until at least one of the triggering events occurs and is then enabled to begin operation. triggering status for counter 1 is provided in the debug status register. triggering mode is enabled by an mtspr dbcr3 which sets one or more of the trigger enable bits and also enables counter 1. the trigger can be re-armed by clearing the dbsr[cnt1trg] status bit. most combinations of enables do not make sense and should be avoided. for example, if dbcr3[icmp] is set for counter 1, no other count enable should be set for counter 1. conversely, multiple instruction address compare count enables are allowed to be set and can be useful. due to instruction pipelining issues and other constraints, most combinations of events are not supported for event counting. only the following combinations are for use; other combinations are not supported: any combination of iac[1?4] any combination of dac[1?2] including linking any combination of devt[1?2] any combination of irpt and ret limited support is provided for any combination of iac[1?4] with dac[1?2] (linked or unlinked). due to pipelining and detection of iac events early in the pipeline and dac events late in the pipeline, no guarantee is made on the exact instruction boundary that a debug exception is generated when iac and dac events are combined for counting. this also applies when counter 1 is triggered by counter 2, and a combination of iac and dac events is enabled for the counters, even if only one of these types is enabled for a particular counter. in general, when an iac event logically follows a dac even t within several instructions, it cannot be recognized immediately because the dac event may not be generated in the pipeline at the time the iac appears. thus, the counter may not decrement to zero for the iac event until after the instruction with the iac (and perhaps several additional instructions) proceeds down the execution pipeline. the instruction boundary where the debug exception is actually generated typically follows t he iac by up to several instructions. note that the counters operate regardless of whether counters are enabled to generate debug exceptions. if counter 2 is used to trigger counter 1, counter 2 events should not normally be enabled in dbcr0 and are not blocked. note: multiple iac or dac events are not counted during an lmw or stmw instruction, and no count occurs if either is interrupted by a crit ical input or external input interrupt before completion.
UM0434 register model 79/391 table 56 provides field definitions for dbcr3 table 55. dbcr3 register 32 33 34 35 36 37 38 39 field devt1c1 devt2c1 icmpc1 iac1c1 iac2c1 iac3c1 iac4c1 dac1rc1 reset all zeros r/w r/w 40 41 42 43 44 45 46 47 field dac1wc1 dac2rc1 dac2wc1 irptc1 retc1 devt1c2 devt2c2 icmpc2 reset all zeros r/w r/w 48 49 50 51 52 53 54 55 iac1c2 iac2c2 iac3c2 iac4c2 dac1rc2 dac1wc2 dac2rc2 dac2wc2 reset all zeros r/w r/w 56 57 58 59 60 61 62 63 devt1t1 devt2t1 iac1t1 iac3t1 d ac1rt1 dac1wt1 cnt2t1 config reset all zeros r/w r/w spr spr 561 table 56. dbcr3 field descriptions bits name description 32 devt1c1 external debug event 1 count 1 enable. 0 counting devt1 debug events by counter 1 is disabled. 1 counting devt1 debug events by counter 1 is enabled. 33 devt2c1 external debug event 2 count 1 enable. 0 counting devt2 debug events by counter 1 is disabled. 1 counting devt2 debug events by counter 1 is enabled. 34 icmpc1 instruction complete debug event count 1 enable. 0 counting icmp debug events by counter 1 is disabled. 1 counting icmp debug events by counter 1 is enabled. icmp events are masked by msr[de] = 0 when operating in internal debug mode. 35 iac1c1 instruction address compare 1 debug event count 1 enable. 0 counting iac1 debug events by counter 1 is disabled. 1 counting iac1 debug events by counter 1 is enabled. 36 iac2c1 instruction address compare2 debug event count 1 enable. 0 counting iac2 debug events by counter 1 is disabled. 1 counting iac2 debug events by counter 1 is enabled.
register model UM0434 80/391 37 iac3c1 instruction address compare 3 debug event count 1 enable. 0 counting iac3 debug events by counter 1 is disabled. 1 counting iac3 debug events by counter 1 is enabled. 38 iac4c1 instruction address compare 4 debug event count 1 enable. 0 counting iac4 debug events by counter 1 is disabled. 1 counting iac4 debug events by counter 1 is enabled. 39 dac1rc1 data address compare 1 read debug event count 1 enable (1) . 0 counting dac1r debug events by counter 1 is disabled. 1 counting dac1r debug events by counter 1 is enabled. 40 dac1wc1 data address compare 1 write debug event count 1 enable (1) . 0 counting dac1w debug events by counter 1 is disabled. 1 counting dac1w debug events by counter 1 is enabled. 41 dac2rc1 data address compare 2 read debug event count 1 enable (1) . 0 counting dac2r debug events by counter 1 is disabled. 1 counting dac2r debug events by counter 1 is enabled. 42 dac2wc1 data address compare 2 write debug event count 1 enable (1) . 0 counting dac2w debug events by counter 1 is disabled. 1 counting dac2w debug events by counter 1 is enabled. 43 irptc1 interrupt taken debug event count 1 enable. 0 counting irpt debug events by counter 1 is disabled. 1 counting irpt debug events by counter 1 is enabled. 44 retc1 return debug event count 1 enable. 0 counting ret debug events by counter 1 is disabled. 1 counting ret debug events by counter 1 is enabled. 45 devt1c2 external debug event 1 count 2 enable. 0 counting devt1 debug events by counter 2 is disabled. 1 counting devt1 debug events by counter 2 is enabled. 46 devt2c2 external debug event 2 count 2 enable. 0 counting devt2 debug events by counter 2 is disabled. 1 counting devt2 debug events by counter 2 is enabled. 47 icmpc2 instruction complete debug event count 2 enable. 0 counting icmp debug events by counter 2 is disabled. 1 counting icmp debug events by counter 2 is enabled. icmp events are masked by msr[de] = 0 when operating in internal debug mode. 48 iac1c2 instruction address compare 1 debug event count 2 enable. 0 counting iac1 debug events by counter 2 is disabled. 1 counting iac1 debug events by counter 2 is enabled. 49 iac2c2 instruction address compare2 debug event count 2 enable. 0 counting iac2 debug events by counter 2 is disabled. 1 counting iac2 debug events by counter 2 is enabled. table 56. dbcr3 field descriptions (continued) bits name description
UM0434 register model 81/391 50 iac3c2 instruction address compare 3 debug event count 2 enable. 0 counting iac3 debug events by counter 2 is disabled. 1 counting iac3 debug events by counter 2 is enabled. 51 iac4c2 instruction address compare 4 debug event count 2 enable. 0 counting iac4 debug events by counter 2 is disabled. 1 counting iac4 debug events by counter 2 is enabled. 52 dac1rc2 data address compare 1 read debug event count 2 enable (1) . 0 counting dac1r debug events by counter 2 is disabled. 1 counting dac1r debug events by counter 2 is enabled. 53 dac1wc2 data address compare 1 write debug event count 2 enable (1) . 0 counting dac1w debug events by counter 2 is disabled. 1 counting dac1w debug events by counter 2 is enabled. 54 dac2rc2 data address compare 2 read debug event count 2 enable (1) . 0 counting dac2r debug events by counter 2 is disabled. 1 counting dac2r debug events by counter 2 is enabled. 55 dac2wc2 data address compare 2 write debug event count 2 enable (1) . 0 counting dac2w debug events by counter 2 is disabled. 1 counting dac2w debug events by counter 2 is enabled. 56 devt1t1 external debug event 1 trigger counter 1 enable. 0 no effect. 1 a devt1 debug event triggers counter 1 operation. 57 devt2t1 external debug event 2 trigger counter 1 enable. 0 no effect. 1 a devt2 debug event triggers counter 1 operation. 58 iac1t1 instruction address compare 1 trigger counter 1 enable. 0 no effect. 1 an iac1 debug event triggers counter 1 operation. 59 iac3t1 instruction address compare 3 trigger counter 1 enable. 0 no effect. 1 an iac3 debug event triggers counter 1 operation. 60 dac1rt1 data address compare 1 read trigger counter 1 enable. 0 no effect. 1 a dac1r debug event triggers counter 1 operation. 61 dac1wt1 data address compare 1 write trigger counter 1 enable. 0 no effect. 1 a dac1w debug event triggers counter 1 operation. table 56. dbcr3 field descriptions (continued) bits name description
register model UM0434 82/391 perform updates to dbcr0, dbsr, dbcr3, an d dbcnt carefully if the counters are enabled for counting icmp events. an instructio n that updates the counters or control over the counters can cause one or more counter events (dcnt1 , dcnt2, cnt1trg), even if the result of the instruction is to modify the counter value or control value to a state where counter events are not expected. this is due to the pipelined nature of the counter and control operation. for dbcnt, if a counter is enabled to count icmp events, msr[de] = 1, and the counter value is 1 before execution of an mtspr that loads the counter with a different value, a counter event is generated after the mtspr completes, even though the counter is loaded with a new value. when the mtspr finishes executing, a debug event is posted, but the counter holds the newly written value. the new counter value is assigned at the completion of an mtspr that modifies a counter, regardless of whether a debug event is generated based on the old counter value. to avoid this, modify dbcnt and dbcr3 only when there is no po ssibility of a counter-related debug event on the mtspr . for dbcr3, if a counter is enabled to count icmp events, msr[de] = 1, and the counter value is 1 before execution of an mtspr that is loading dbcr3 with a different value, a counter event may be generated after the mtspr completes, even though dbcr3 is loaded with a value that prevents the particular event from being counted. when the mtspr finishes executing, a debug event is posted, but the dbcr3 value reflects the newly established control, whic h may indicate that the particular event is not to cause a counter update. modifying dbcr0 to affect counter event en abling/disabling may have similar issues, as may modifying dbsr[cnt1trg]. 4.12.4 debug status register (dbsr) dbsr, shown in table 57 , contains status on debug events and the most recent processor reset. hardware sets dbsr, and software reads and clears it by writing a 1 in any bit position that is to be cleared and 0 in all other bit positions. the write data to the debug status register is not direct data, but a mask. a 1 causes the bit to be cleared, and a 0 has no effect. debug status bits are set by debug events only while internal debug mode is enabled or external debug mode is enabled. when debug interrupts are enabled (msr[de] = 1, dbcr0[idm] = 1, and dbcr0[edm] = 0), a set bit in dbsr causes a debug interrupt to be generated. when debug interrupts are enabled (msr[de]=1, dbcr0[idm]=1, and dbcr0[edm]=0), a set bit in dbsr other than mrr or vles causes a debug interrupt. the debug interrupt handler clears dbsr bits before returning to normal execution. the powerpc vle apu 62 cnt2t1 debug counter 2 trigger counter 1 enable. 0 no effect. 1 counter 2 decrementing to 0 triggers counter 1 operation. 63 config debug counter configuration. 0 counter 1 and counter 2 are independent counters. 1 counter 1 and counter 2 are concatenated into a single 32-bit counter. the event count control bits for counter 1 are used and the even t count control bits for counter 2 are ignored. 1. if the dacx field in dbcr0 is set to restrict events to only reads or only writes, only thos e events are counted if enabled i n dbcr3. in general, dac events should be disabled in dbcr0. table 56. dbcr3 field descriptions (continued) bits name description
UM0434 register model 83/391 adds the dbsr[vles] status bit to indicate debug events occurring due to a powerpc vle instruction. table 58 provides field definitions for the debug status register. table 57. dbsr register 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 field ide ude mrr icmp brt irpt trap iac1 iac2 iac3 iac4 dac1r dac1w dac2r dac2w reset 0001_0000_0000_0000 r/w read/clear 48 49 52 53 54 55 56 57 58 59 62 63 field ret ? devt1 devt2 dcnt1 dcnt2 cirpt cret ? cnt1trg reset 0000_0000_0000_0000 r/w read/clear spr spr 304 table 58. dbsr field descriptions bits name description 32 ide imprecise debug event. set if msr[de] = 0 and dbcr0[edm] = 0 and a debug event causes its respective debug status register bit to be set. ide can also be set if dbcr0[edm] = 1 and an imprecise debug event occurs due to a dac even t on a load or store t hat is terminated with error, or if an icmp event occurs in conjunction with a spe fp round exception. 33 ude unconditional debug event. set when an unconditional debug event occurs. 34?35 mrr most recent reset. 00 no reset since software last cleared these bits. 01 a hard reset occurred since software last cleared these bits. 1 x reserved. 36 icmp instruction complete debug event. set if an instruction complete debug event occurs. 37 brt branch taken debug event. set if an branch taken debug event occurs. 38 irpt interrupt taken debug event. set if an interrupt taken debug event occurs. 39 trap trap taken debug event. set if a trap taken debug event occurs. 40 iac1 instruction address compare 1 debug event. set if an iac1 debug event occurs. 41 iac2 instruction address compare 2 debug event. set if an iac2 debug event occurs. 42 iac3 instruction address compare 3 debug event. set if an iac3 debug event occurs. 43 iac4 instruction address compare 4 debug event. set if an iac4 debug event occurs. 44 dac1r data address compare 1 read debug event. set if a read-type dac1 debug event occurs while dbcr0[dac1] = 0b10 or dbcr0[dac1] = 0b11. 45 dac1w data address compare 1 write debug event. set if a write-type dac1 debug event occurs while dbcr0[dac1] = 0b01 or dbcr0[dac1] = 0b11. 46 dac2r data address compare 2 read debug event. set if a read-type dac2 debug event occurs while dbcr0[dac2] = 0b10 or dbcr0[dac2] = 0b11.
register model UM0434 84/391 4.13 hardware implementati on dependent registers hardware implementation-dependent registers 0 and 1 (hid0 and hid1) are configuration registers to control various processor and system functions. 4.13.1 hardware implementatio n dependent regist er 0 (hid0) hid0, shown in table 59 , is used for various configuration and control functions. hid0 fields are described in table 60 . 47 dac2w data address compare 2 write debug event. set if a write-type dac2 debug event occurs while dbcr0[dac2] = 0b01 or dbcr0[dac2] = 0b11. 48 ret return debug event. set if a return debug event occurs. 49?52 ? reserved, should be cleared. 53 devt1 external debug event 1 debug event. set if a devt1 debug event occurs. 54 devt2 external debug event 2 debug event. set if a devt2 debug event occurs. 55 dcnt1 debug counter 1 debug event. set if a dcnt1 debug event occurs. 56 dcnt2 debug counter 2 debug event. set if a dcnt2 debug event occurs. 57 cirpt critical interrupt taken debug event. set if a critical interrupt taken debug event occurs. 58 cret critical return debug event. set if a critical return debug event occurs. 59?62 ? reserved, should be cleared. 63 cnt1trg counter 1 triggered. set if debug counter 1 is triggered by a trigger event. table 58. dbsr field descriptions (continued) bits name description table 59. hardware implementation dependent register 0 (hid0) 32 33 37 38 39 40 41 42 43 45 46 47 field emcp ? bpred doze nap sleep ? icr nhr reset all zeros r/w r/w 48 49 50 51 52 53 54 55 56 63 ? tbensel_tbclkdclree dclrceciclrdemcclrde dapuen ? reset all zeros r/w r/w spr spr 1008
UM0434 register model 85/391 table 60. hid0 field descriptions bits name description 32 emcp enable machine check signal ( p_mcp_b ). used to mask out further machine check exceptions caused by assertion of p_mcp_b . 0 p_mcp_b is disabled. 1 p_mcp_b is enabled. if msr[me] = 0, asserting p_mcp_b causes checkstop. if msr[me] = 1, asserting p_mcp_b causes a machine check interrupt. 33?37 ? reserved, should be cleared. 38?39 bpred branch prediction (acceleration) control. contro ls btb lookahead for branch acceleration. note that for branches with aa = 1, the msb of the displacement fi eld is still used to indicate forward/backward, even though the branch is absolute. used in conjunction with bucsr. 00 branch acceleration is enabled. 01 branch acceleration is disabled for backward branches. 10 branch acceleration is disabled for forward branches. 11 branch acceleration is disabled for both branch directions. 40 doze doze power management mode. doze mode is invoked by setting msr[we] while doze = 1. 0 doze mode is disabled. 1 doze mode is enabled. 41 nap nap power management mode. nap mode is invoked by setting msr[we] while nap=1. 0 nap mode is disabled. 1 nap mode is enabled. 42 sleep sleep power management mode. sleep mode is invoked by setting msr[we] while we=1. only one of doze, nap, or sleep should be set for proper operation. 0 sleep mode is disabled. 1 sleep mode is enabled. 43?45 ? reserved, should be cleared. 46 icr interrupt inputs clear reservation. 0 external and critical input interrupts do not affect reservation status. 1 external and critical input interrupts clear an outstanding reservation. 47 nhr not hardware reset. provided for software use. set anytime by software, cleared by reset. 0 indicates a reset to a reset exception handler if software has previously set this bit. 1 indicates to a reset exception handler that there was no reset if software has previously set this bit. 48 ? reserved, should be cleared. 49 tben time base enable. used to enable the time base and decrementer. 0 time base is disabled. 1 time base is enabled. 50 sel_tbcl k select time base clock. selects the time base clock source. th is bit must altered while the time base is disabled to prevent counter glitches. timer interrupts should be disabled beforehand, and tbl and tbu are reinitialized after a change of time base clock source. 0 time base is based on processor clock. 1 time base is based on the p_tbclk input.
register model UM0434 86/391 4.13.2 hardware implementatio n dependent regist er 1 (hid1) the hid1 register is used for bus configuration and system control. hid1 is shown in table 61 . 51 dclree debug interrupt clears msr[ee]. controls whether debug interrupts force external input interrupts to be disabled, or whether they remain unaffected. 0 msr[ee] unaffected by debug interrupt. 1 msr[ee] cleared by debug interrupt. 52 dclrce debug interrupt clears msr[ce]. controls whethe r debug interrupts force critical interrupts to be disabled, or whether they remain unaffected. 0 msr[ce] unaffected by debug interrupt. 1 msr[ce] cleared by debug interrupt. 53 ciclrde critical interrupt clears msr[de]. controls whet her certain critical interrupts (critical input, watchdog timer) force debug interrupts to be di sabled, or whether they remain unaffected. machine check interrupts have a separate control bit. 0 msr[de] unaffected by critical class interrupt. 1 msr[de] cleared by critical class interrupt. if critical interrupt debug events are enabled (dbcr0[cirpt] is set, which should only be done when the debug apu is enabled), and msr[de] is set at the time of a critical interrupt (critical input, watchdog timer), a debug event is generated after the critical interrupt handler has been fetched, and the debug handler is executed first. in this case, dsrr0[de] will have been cleared, such that after returning from the debug handler, the critical interrupt handler will not be run with msr[de] enabled. 54 mcclrde machine check interrupt clears msr[de]. controls whether machine check interrupts force debug interrupts to be disabled or are unaffec ted. if critical interrupt debug events are enabled (dbcr0[cirpt] is set, which should only be done when the debug apu is enabled), and msr[de] is set at the time of a machine check interrupt, a debug event is generated after the machine check interrupt handler is fetched, and the debug handler executes first. in this case, dsrr0[de] is cleared so that after returning from the debug handler, the machine check handler cannot be run if msr[de] = 1. 0 msr[de] unaffected by machine check interrupt. 1 msr[de] cleared by machine check interrupt. 55 dapuen debug apu enable. controls whether the debug apu is enabled. 0 debug apu disabled. debug interrupts use the critical interrupt re sources: csrr0/csrr1 and rfci ; rfdi is treated as an illegal instruction. dclree, dclrce, ciclrde, and mcclrde settings are ignored and are assumed to be ones. 1 debug apu enabled. debug interrupts use dsrr0/dsrr1 for saving state and rfdi is available for returning from a debug interrupt. read and write access to dsrr0/dsrr1 via mfspr and mtspr is not affected by this bit. 56?63 ? reserved, should be cleared. table 60. hid0 field descriptions (continued) bits name description
UM0434 register model 87/391 hid1 fields are described in table 62 . 4.14 branch target buffer (btb) registers this section describes the only register that controls the branch target buffer. 4.14.1 branch unit control and status register (bucsr) bucsr, shown in table 63 , is for general control & status of the branch target buffer (btb). bucsr fields are described in table 64 . table 61. hardware implementation dependent register 1 (hid1) 32 55 56 57 62 63 field ? ats ? ard reset all zeros r/w r/w spr spr 1009 table 62. hid1 field descriptions bits name description 32?55 ? reserved, should be cleared. 56 ats atomic status (read-only). indi cates state of the reservation bit in the load/store unit. see chapter 5.7: memory synchronization and reservation instructions on page 111 .? 57?62 ? reserved, should be cleared. 63 ard address retraction disable. 0 address retraction enabled. 1 address retraction disabled. controls address retraction operation. for details, see chapter 9.5.3: address retraction on page 282 .? table 63. branch unit control and status register (bucsr) 32 53 54 55 62 63 field ? bbfi ? bpen reset all zeros r/w r/w spr spr 1013
register model UM0434 88/391 4.15 l1 cache configuration registers this section describes the register t hat helps not to configure the cache. 4.15.1 l1 cache configurati on register 0 (l1cfg0) the l1 cache configuration register 0 (l1cfg0) provides information on how not to configure the e200z3 cache design. for e200z3, reads of this register return a value of all zeros. 4.16 mmu registers this section describes the e200z3 registers for setting up and maintaining the tlbs. 4.16.1 mmu control and stat us register 0 (mmucsr0) mmucsr0, shown in table 65 , controls the state of the mmu. the mmucsr0 fields are described in table 66 . table 64. branch unit control and status register bits name description 32?53 ? reserved, should be cleared. 54 bbfi branch target buffer flash invalidate. when set, bbfi flash clears the valid bit of all btb entries; clearing occurs regardless of the value of the enable bit (bpen). note : bbfi is always read as 0. 55?62 ? reserved, should be cleared. 63 bpen branch target buffer (btb) enable. 0 btb prediction disabled. no hits are generated from the btb and no new entries are allocated. en tries are not automatically invalidated when bpen is cleared; bbfi controls entry invalidation. 1 btb prediction enabled (enables btb to predict branches). table 65. mmu control and status register 0 (mmucsr0) 32 61 62 63 field ? tlb1_fi ? reset all zeros r/w r/w spr spr 1012
UM0434 register model 89/391 4.16.2 mmu configurati on register (mmucfg) the mmu configuration register (mmucfg) is a 32-bit read-only register. the spr number for mmucfg is 1015 in decimal. mmucfg, which provides information about the configuration of the e200z3 mmu design, is shown in table 67 . the mmucfg fields are described in table 68 . table 66. mmucsr0 field descriptions bits name description 32?61 ? reserved, should be cleared. 62 tlb1_fi tlb1 flash invalidate 0 no flash invalidate 1 tlb1 invalidation operation. hardwa re initiates a tl b1 invalidation, after which tlb1_fi is cleared. se tting tlb1_fi while an invalidation operation is in progress causes an undefined operation. clearing tlb1_fi while an invalidation operatio n is in progress is ignored. tlb1 invalidation operations require 3 cycles to complete. 63 ? reserved, should be cleared. table 67. mmu configuration register 1 (mmucfg) 32 48 49 52 53 57 58 59 60 61 62 63 field ? npids pidsize ? ntlbs mavn reset 0000_0000_0000_0000_0 000_1 001_11 00 01 00 r/w read only spr spr 1015
register model UM0434 90/391 4.16.3 tlb configuration registers (tlb n cfg) the tlb n cfg read-only registers provide information about each specific tlb that is visible to the programming model. tlb configuration register 0 (tlb0cfg) tlb0cfg, shown in table 69 , provides information about the configuration of tlb0. because the e200z3 mmu design does not implemen t tlb0, this register reads as all zeros. it is supplied to allow software to query it in a way compatible with other book e designs. the tlb0cfg fields are described in table 70 . table 68. mmucfg field descriptions bits name description 32?48 ? reserved, should be cleared. 49?52 npids number of pid registers. 0001 this version of the mmu implements one pid register (pid0). 53?57 pidsize pid register size. 00111 pid registers contain 8 bits in this version of the mmu. 58?59 ? reserved, should be cleared. 60?61 ntlbs number of tlbs. 01 this version of the mmu implements two tlb structures: a null tlb0 and a populated tlb1. 62?63 mavn mmu architecture version number. 00 this version of the mmu implements version 1.0 of the book e mmu architecture. table 69. tlb configuration register 0 (tlb0cfg) 32 39 40 43 44 47 48 49 50 51 52 63 field assoc minsize maxsize iprot avail ? nentry reset all zeros (tlb0 is not implemented) r/w read only spr spr 688 table 70. tlb0cfg field descriptions bits name description 32?39 assoc associativity. 40?43 minsize minimum page size. 44?47 maxsize maximum page size. 0 48 iprot invalidate protect capability. 0
UM0434 register model 91/391 tlb configuration register 1 (tlb1cfg) tlb1cfg, shown in table 71 , provides information on the tlb1 configuration. the tlb1cfg fields are described in table 72 . 4.16.4 mmu assist regist ers (mas0?mas4, mas6) the e200z3 uses six special purpose registers (mas0?mas4, and mas6) for reading, writing, and searching the tlbs. the mas registers can be read or written using the mfspr and mtspr instructions. the e200z3 does not implement the mas5 register, which is present in other book e designs, because the tlbsx instruction only searches based on a single spid value. 49 avail page size availability. 0 50?51 ? reserved, should be cleared. 52?63 nentry number of entries. 0 tlb0 contains 0 entries. table 70. tlb0cfg field descriptions (continued) bits name description table 71. tlb configuration register 1 (tlb1cfg) 32 39 40 43 44 47 48 49 50 51 52 63 field assoc minsize maxsize iprot avail ? nentry reset 0010_0000 0001 1001 1 1 00 0000_0010_0000 r/w read only spr spr 689 table 72. tlb1cfg field descriptions bits name description 32?39 assoc associativity. 0x10 indicates that tl b1 associativity is 16 40?43 minsize minimum page size. 0x1 smallest page size is 4 kbytes. 44?47 maxsize maximum page size. 0x9 largest page size is 256 mbytes. 48 iprot invalidate protect capability. 1 invalidate protect capability is supported in tlb1. 49 avail page size availability. 1 all page sizes between minsiz e and maxsize are supported. 50?51 ? reserved, should be cleared. 52?63 nentry number of entries. 0x010 tlb1 contains 16 entries.
register model UM0434 92/391 for details on the mas n registers, see chapter 7.6.5: mmu assist registers (mas) on page 204 .? the mas0 register is shown in table 73 . mas0 fields are defined in table 74 . the mas1 register is shown in table 75 . mas1 fields are defined in table 76 . table 73. mas register 0 (mas0) format 32 33 34 35 36 42 43 47 48 58 59 63 field ? tlbsel ? esel ? nv reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 624 table 74. mas0 - mmu read/write and replacement control bits name description 32?33 ? reserved, should be cleared. 34?35 tlbsel selects tlb for access. 01 tlb1 (ignored by the e200 z3, should be writ ten to 01 for futu re compatibility). 36?42 ? reserved, should be cleared. 43?47 esel entry select for tlb1. 48?58 ? reserved, should be cleared. 59?63 nv next replacement victim for tlb1 (software managed) . software updates this field; it is copied to the esel field on a tlb error (see table 156 ). table 75. mmu assist register 1 (mas1) 32 33 34 39 40 47 48 50 51 52 55 56 63 field valid iprot ? tid ? ts tsize ? reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 625
UM0434 register model 93/391 the mas2 register is shown in table 77 . mas2 fields are defined in table 78 . table 76. mas1 - descriptor context and configuration control bits name description 32 valid tlb entry valid. 0 this tlb entry is invalid. 1 this tlb entry is valid. 33 iprot invalidation protect. protects tlb entry from invalidation by tlbivax (tlb1 only), or flash invalidates through mmucsr0[tlb1_fi]. 0 entry is not protected from invalidation. 1 entry is protected from invalidation as described in chapter 7.3.1: iprot invalidation protection in tlb1 on page 198 .? 34?39 ? reserved, should be cleared. 40?47 tid translation id. compared with the current process ids of the effective address to be translated. a tid value of 0 defines an entry as global and matches with all process ids. 48?50 ? reserved, should be cleared. 51 ts translation address space. compared with msr[ is] or msr[ds] (depending on the type of access) to determine if this tlb entry may be used for translation. 52?55 tsize entry page size. supported page sizes are: 0001 4 kbytes 0110 4 mbytes. 0010 16 kbytes 0111 16 mbytes. 0011 64 kbytes 1000 64 mbytes. 0100 256 kbytes 1001 256 mbytes. 0101 1 mbyte. all other values are undefined. 56?63 ? reserved, should be cleared. table 77. mmu assist register 2 (mas2) spr 626 access: supervisor read/write 0 32 r epn w reset undefined 32 51 52 54 55 56 57 58 59 60 61 62 63 r epn ?vlewimge w
register model UM0434 94/391 the mas3 register is shown in table 79 . table 78. mas2 - epn and page attributes bits name description 32?51 epn effective page number. 52?57 ? reserved, should be cleared. 58 vle vle mode. identifies pages that contain in structions from the vle apu. vl e is implemented only if the processor supports the vle apu. setting both the vle and e fields is a programming error; an attempt to fetch instructions from a page so ma rked produces an isi byte ordering exception and sets esr[bo]. 0 instructions fetched from the page are decoded and executed as powerpc or eis instructions. 1 instructions fetched from the page are decoded and executed as vle or eis instructions. implementation-dependent page attribute. 59 w write-through required. 0 this page is a write-back with respect to the caches in the system. 1 all stores performed to this page are written through to main memory. 60 i cache inhibited. 0 this page is cacheable. 1 this page is cache-inhibited. 61 m memory coherence required.the e200z3 does not support the memory coherence required attribute, and thus it is ignored. 0 memory coherence is not required. 1 memory coherence is required. 62 g guarded. the e200z3ignores the guarded attr ibute (other than for generation of the p_hprot[4:2] attributes on an external access), since no spec ulative or out-of-order processing is performed. 0 access to this page are not guarded, and can be performed before it is known if they are required by the sequential execution model. 1 all loads and stores to this page are performed without speculation (that is, they are known to be required). 63 e endianness. determines endianness for the corresponding page. 0 the page is accessed in big-endian byte order. 1 the page is accessed in true little-endian byte order.
UM0434 register model 95/391 mas3 fields are defined in table 80 . the mas4 register, shown in table 81 , contains fields for specifying default information to be pre-loaded on certain mmu related exceptions. the mas4 fields are defined in table 82 . table 79. mmu assist register 3 (mas3) permission bits 32 51 52 53 54 55 56 57 58 59 60 61 62 63 field rpn ? u0u1u2u3uxsxuwswursr reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 627 table 80. mas3 - rpn and access control bits name description 32?51 rpn real page number. only bits that correspond to a page number are valid. bits that represent offsets within a page are ignored and should be zero. 52?53 ? reserved, should be cleared. 54?57 u0?u3 user bits. 58?63 permis permission bits (ux, sx, uw, sw, ur, sr). table 81. mmu assist register 4 (mas4) spr 628 access: supervisor read/write 32 33 34 35 36 39 40 47 48 51 52 55 56 57 58 59 60 61 62 63 r ? tlbseld ? tidseld ? tsized ? vled wd id md gd ed w reset all zeros table 82. mas4 - hardware replacement assist configuration register bits name description 32?33 ? reserved, should be cleared. 34?35 tlbseld default tlb selected. 01 tlb1 (ignored by the e2 00z3, should be written to 01 for future compatibility) 36?43 ? reserved, should be cleared.
register model UM0434 96/391 the mas6 register is shown in table 83 . mas6 fields are defined in table 84 . 4.16.5 process id register (pid0) the process id register, pid0, is shown in table 85 . the book e architecture requires that a process id (pid) value be associated with each effective address (instruction or data) generated by the processor. book e defines one pid register that maintains the value of the pid for the current process. the number of pids implemented is indicated by the value of 44?47 tidseld tid default selection value. 4-bit field that spec ifies which of the current pid registers should be used to load the mas1[tid] field on a tlb miss exception. the pid registers are addressed as follows: 0000 = pid0 (pid). 0001 = pid1. ... 1110 = pid14. a value that references a non-implemented pid r egister causes a value of 0 to be placed in mas1[tid]. 48?51 ? reserved, should be cleared. 52?55 tsized default tsize value. 56?57 ? reserved, should be cleared. 58 vled default vle value. specifies the default value loaded into mas2[vle] on a tlb miss exception. 59?63 dwimge default wimge values. table 82. mas4 - hardware replacement assist configuration register (continued) bits name description table 83. mmu assist register 6 (mas6)) 32 39 40 47 48 62 63 field ? spid ? sas reset undefined on m_por assertion, unchanged on p_reset_b assertion r/w r/w spr spr 630 table 84. mas6 - tlb search context register 0 bits name description 32?39 ? reserved, should be cleared. 40?47 spid pid value for searches 48?62 ? reserved, should be cleared. 63 sas as value for searches
UM0434 register model 97/391 mmucfg[npids]. (the e200z3 defines no addition al pid registers.) pid values are used to construct virtual addresses for accessing memory. 4.17 support for fast context switching to provide real-time ca pabilities for embedded systems, futu re versions of the e200z3 core will include optional hardware support for fast co ntext switching. the initial version of the e200z3 does not implement additional register contexts. 4.17.1 context control register (ctxcr) the future versions of the e200z3 core may include optional hardware support for fast context switching to pr ovide real-time capabilities for embed ded systems. the initial version of e200z3 does not implement additional register contexts. a new privileged 32-bit special- purpose register (spr) called the context control register (ctxcr) is defined in the core cpu. the ctxcr controls the context registers that are mapped to the current context and holds current, alternate, and saved context information. supervisor software reads the ctxcr to determine whether multiple contexts are supported in hardware, and if so, the number implemented. when multiple register contexts are present (ctxcr[numctx] is non-zero), ctxcr is also writable. otherwise, writes are ignored, and the register reads as all zeros. ctxcr is shown in table 86 . 4.18 spr register access sprs are accessed with the mfspr and mtspr instructions. the following sections outline additional access requirements. 4.18.1 invalid spr references system behavior when an invalid spr is referenced depends on the apparent privilege level of the register, which is determined by bit 5 in the spr address. if the invalid spr is table 85. process id register (pid0) 32 55 56 63 field ? process id reset all zeros r/w r/w spr spr 48 table 86. context control register (ctxcr) 32 55 56 63 field ? reset all zeros r/w r/w (writes are ignored because no additional contexts are implemented.) spr spr 560
register model UM0434 98/391 accessible in user mode, an illegal exception is generated. if the inva lid spr is accessible only in supervisor mode and the cpu core is in supervisor mode (msr [pr] = 0), an illegal exception is generated. if the invalid spr address is accessible only in supervisor mode and the cpu is not in supervisor mode (msr[pr] = 1), a privilege exception is generated. 4.18.2 synchronization requirements for sprs except for the following registers, no synchronization is required for accessing sprs beyond those stated in book e. eref completely describes synchronization requirements. software requirements for synchronization be fore/after accessing thes e registers are shown in table 88 . the notation csi in the table refers to context synchronizing instructions, including sc , isync , rfi , rfci , and rfdi . table 87. system response to invalid spr reference spr address bit 5 mode msr[pr] response 0 ? ? illegal exception 1 supervisor 0 illegal exception 1 user 1 privilege exception table 88. additional synchronization requirements for sprs context altering event or instructio n required before required after notes mtmsr[ucle] none csi mfspr dbcnt debug counter register msync none (1) dbsr debug status register msync none hid0 hardware implementation dependent register 0 none none hid1 hardware implementation dependent register 1 msync none mmucsr mmu control and status register 0 csi none mtspr bucsr branch unit control and status register none csi ctxcr context control register csi csi dbcnt debug counter register none csi (1) dbcr0 debug control register 0 none csi dbcr1 debug control register 1 none csi dbcr2 debug control register 2 none csi dbcr3 debug control register 3 none csi dbsr debug status register msync none hid0 hardware implementation dependent reg 0 csi csi mmucsr mmu control and status register 0 csi csi 1. not required if counter is not currently enabled.
UM0434 register model 99/391 4.18.3 special purpose register summary powerpc book e and implementation-specific sprs for the e200z3 core are listed in table 89 . all registers are 32 bits. register bits are numbered from bit 32?63 (most significant to least significant). shaded entries represent optional registers. an spr can be read or written with the mfspr and mtspr instructions. in the inst ruction syntax, compilers should recognize the mnemonic in the table below. for details, see chapter 4.4: processor control registers on page 43 .? table 89. special purpose registers mnemonic name spr number access privileged e200z3 specific bucsr branch unit control and status register 1013 r/w yes yes csrr0 critical save/restore register 0 58 r/w yes no csrr1 critical save/restore register 1 59 r/w yes no ctr count register 9 r/w no no ctxcr context cont rol register 560 r/w (1) ye s ye s dac1 data address compare 1 316 r/w yes no dac2 data address compare 2 317 r/w yes no dbcnt debug counter register 562 r/w yes yes dbcr0 debug control register 0 308 r/w yes no dbcr1 debug control register 1 309 r/w yes no dbcr2 debug control register 2 310 r/w yes no dbcr3 debug control register 3 561 r/w yes yes dbsr debug status register 304 read/clear (2) ye s n o dear data exception address register 61 r/w yes no dec decrementer 22 r/w yes no decar decrementer auto-reload 54 r/w yes no dsrr0 debug save/restore register 0 574 r/w yes yes dsrr1 debug save/restore register 1 575 r/w yes yes esr exception syndrome register 62 r/w yes no hid0 hardware implementation dependent reg 0 1008 r/w yes yes hid1 hardware implementation dependent reg 1 1009 r/w yes yes iac1 instruction address compare 1 312 r/w yes no iac2 instruction address compare 2 313 r/w yes no iac3 instruction address compare 3 314 r/w yes no iac4 instruction address compare 4 315 r/w yes no ivor0 interrupt vector offs et register 0 400 r/w yes no ivor1 interrupt vector offs et register 1 401 r/w yes no ivor2 interrupt vector offs et register 2 402 r/w yes no
register model UM0434 100/391 ivor3 interrupt vector offs et register 3 403 r/w yes no ivor4 interrupt vector offs et register 4 404 r/w yes no ivor5 interrupt vector offs et register 5 405 r/w yes no ivor6 interrupt vector offs et register 6 406 r/w yes no ivor7 interrupt vector offs et register 7 407 r/w yes no ivor8 interrupt vector offs et register 8 408 r/w yes no ivor9 (3) interrupt vector offset register 9 409 r/w yes no ivor10 interrupt vector offset register 10 410 r/w yes no ivor11 interrupt vector offset register 11 411 r/w yes no ivor12 interrupt vector offset register 12 412 r/w yes no ivor13 interrupt vector offset register 13 413 r/w yes no ivor14 interrupt vector offset register 14 414 r/w yes no ivor15 interrupt vector offset register 15 415 r/w yes no ivor32 interrupt vector offset register 32 528 r/w yes yes ivor33 interrupt vector offset register 33 529 r/w yes yes ivor34 interrupt vector offset register 34 530 r/w yes yes ivpr interrupt vector prefix register 63 r/w yes no lr link register 8 r/w no no l1cfg0 l1 cache configuration register 0 515 read only no yes mas0 mmu assist register 0 624 r/w yes yes mas1 mmu assist register 1 625 r/w yes yes mas2 mmu assist register 2 626 r/w yes yes mas3 mmu assist register 3 627 r/w yes yes mas4 mmu assist register 4 628 r/w yes yes mas6 mmu assist register 6 630 r/w yes yes mcsr machine check syndrome register 572 r/w yes yes mmucfg mmu configuration register 1015 read only yes yes mmucsr0 mmu control and status register 0 1012 r/w yes yes pid0 process id register 48 r/w yes no pir processor id register 286 read only yes no pvr processor version register 287 read only yes no spefscr spe apu status and control register 512 r/w no no sprg0 spr general 0 272 r/w yes no sprg1 spr general 1 273 r/w yes no table 89. special purpose registers (continued) mnemonic name spr number access privileged e200z3 specific
UM0434 register model 101/391 4.18.4 reset settings table 90 shows the state of the powerpc book e registers and other optional resources immediately following a system reset. sprg2 spr general 2 274 r/w yes no sprg3 spr general 3 275 r/w yes no sprg4 spr general 4 260 read only no no 276 r/w yes no sprg5 spr general 5 261 read only no no 277 r/w yes no sprg6 spr general 6 262 read only no no 278 r/w yes no sprg7 spr general 7 263 read only no no 279 r/w yes no srr0 save/restore register 0 26 r/w yes no srr1 save/restore register 1 27 r/w yes no svr system version register 1023 read only yes yes tbl time base lower 268 read only no no 284 write only yes no tbu time base upper 269 read only no no 285 write only yes no tcr timer control register 340 r/w yes no tlb0cfg tlb0 configuration register 688 read only yes yes tlb1cfg tlb1 configuration register 689 read only yes yes tsr timer status register 336 read/clear (4) ye s n o usprg0 user spr general 0 256 r/w no no xer integer exception register 1 r/w no no notes: 1. only writable when multiple contexts ar e implemented. otherwise, writes are ignored 2. the debug status register (dbsr) is read using mfspr . dbsr cannot be directly written. instead, dbsr bits corresponding to 1 bits in the gpr can be cleared using mtspr . 3. ivor9 handles the auxiliary processor unav ailable interrupt. this interrupt is def ined by the eis but not supported in the e200z3; therefore, use of ivor 9 is not supported in the e200z3. 4. tsr is read using mfspr , but it cannot be directly written. instead, ts r bits corresponding to 1 bits in the gpr can be cleared using mtspr . table 89. special purpose registers (continued) mnemonic name spr number access privileged e200z3 specific
register model UM0434 102/391 table 90. reset settings for e200z3 resources resource system reset setting program counter p_rstbase[0:19] || 0xffc gprs unaffected (1) cr unaffected 1 bucsr 0x0000_0000 csrr0 unaffected 1 csrr1 unaffected 1 ctr unaffected 1 ctxcr 000 || numctx || 00_0000_0000_0000_0000_0000_0000 (2) dac1?dac2 0x0000_0000 dbcnt unaffected 1 dbcr0?dbcr3 0x0000_0000 dbsr 0x1000_0000 dear unaffected 1 dec unaffected 1 decar unaffected 1 dsrr0 unaffected 1 dsrr1 unaffected 1 esr 0x0000_0000 hid0?hid1 0x0000_0000 iac1?iac4 0x0000_0000 ivor0?ivor15 unaffected 1 ivor32?ivor34 unaffected 1 ivpr unaffected 1 l1cfg0 (3) ? lr unaffected 1 mas0?mas4, mas6 unaffected 1 mcsr 0x0000_0000 mmucfg 3 ? mmucsr0 0x0000_0000 msr 0x0000_0000 pid0 0x0000_0000 pir 3 0x0000_00 || p_cpuid[0:7] pvr 3 ? spefscr 0x0000_0000 sprg0?sprg7 unaffected 1
UM0434 register model 103/391 4.19 parallel signature unit registers to support applications requiring system integrity checking during operation, the e200z3 provides a parallel signature unit to monitor the cpu data read and data write ahb buses and to accumulate a pair of 32-bit misr signatures of the data values transferred over these buses. the primitive polynomia l used is p(x)=1+x 10 +x 30 +x 31 +x 32 . values are accumulated based on an initially programmed seed value and are qualified based on active byte lanes of the data read and data write buses ( p_d_hrdata[63:0] , p_d_hwdata[63:0] ) as indicated via the p_d_hbstrb[7:0] signals. inactive byte lanes use a value of all zeros as input data to the misrs. refer to table 170 for active byte lane information. if a transfer error occurs on any accumulated read data, the returned read data is ignored, a value of all zeros is used instead, and the error is logged. errors occurring on data writes are not logged, since the data driven by the cpu is valid. the unit can be independently enabled for read cycles and write cycles, allowing for flexible usage. software can also control accumulation of software-provided values via a pair of update registers. in addition, there is a counter for software to monitor the number of beats of data compressed. updates are performed when the parallel signature registers are initializ ed, when a qualified bus cycle is terminated, when a software update is performed via a high or low update register, and when the parallel signature high or low registers are written with an mtdcr instruction. note: updates due to qualified bus transfers are suppressed for the duration of a debug session. srr0 unaffected 1 srr1 unaffected 1 svr 3 ? tbl unaffected 1 tbu unaffected 1 tcr 0x0000_0000 tlb0cfg? tlb1cfg ? tsr undefined on power-on reset; ot herwise, 0x(0b00||wrs)000_0000 usprg0 unaffected 1 xer 0x0000_0000 1. undefined on m_por assertion, unchanged on p_reset_b assertion. 2. for ctxcr 0 only, others unaffected. 3. read-only register. table 90. reset settings for e200z3 resources (continued) resource system reset setting
register model UM0434 104/391 figure 6. parallel signature unit the parallel signature unit consists of seven registers as described in this section. access to these registers is privileged. no user-mode access is allowed. note: proper access of the psu registers requires an mfdcr that reads a psu register to be proceeded by either mbar or msync . to ensure that the effects of an mtdcr to one of the psu registers takes effect, the mtdcr is followed by a context synchronizing instruction ( sc , isync , rfi , rfci , rfdi ). 4.19.1 parallel signatur e control register (pscr) pscr, shown in table 91 , controls operation of the parallel signature unit. pscr field descriptions are shown in table 92 . . + d q + d q + d q + d q + d q + d q + d q ... ... d31 (d63) d30 (d62) d29 (d61) d28 (d60) d1 (d33) d0 (d32) d21 (d53) + d q d20 (d52) + d q d22 (d54) data bus (p_d_hrdata, p_d_hwdata) pshr, (pslr) table 91. parallel signature control register (pscr) 32 57 58 59 60 61 62 63 field ? cnten ? rden wren init reset all zeros r/w r/w dcr dcr 272 table 92. pscr field descriptions bits name description 32?57 ? reserved, should be cleared. 58 cnten counter enable. 0 counter is disabled. 1 counter is enabled. counter is incremented on every accumulated transfer or on an mtdcr psulr,r s. 59?60 ? reserved, should be cleared. 61 rden read enable. 0 processor data read cycles are ignored. 1 processor data reads cycles are accumulated. for inactive byte lanes, zeros are used for the data values.
UM0434 register model 105/391 4.19.2 parallel signature status register (pssr) pssr, shown in table 93 , provides status relative to operation of the parallel signature unit. the pssr register fields are described in table 94 . . 4.19.3 parallel signatur e high register (pshr) the pshr, shown in table 4.19.4 , provides signature information for the high word (bits 63? 32) of the ahb data read and data write buses. writing pshr initializes a seed value before enabling signature accumulation. pscr[init] may also be used to clear the pshr. pshr is unaffected by system reset, thus should be initialized by software before performing parallel signature operations. 62 wren write enable. 0 processor write cycles are ignored. 1 processor write cycles are accumulated. for inactive byte lanes, zeros are used for the data values. 63 init this bit can be written with a 1 to set the values in the pshr, pslr, and psctr registers to all 0s. (0x00000000). this bit always reads as 0. table 92. pscr field descriptions (continued) bits name description table 93. parallel signature status register (pssr) 32 62 63 field ? terr reset unaffected r/w ? w1c dcr dcr 273 table 94. pssr fi eld descriptions bits name description 32?62 ? reserved, should be cleared. 63 terr transfer error status. indicates whether a transfer error occurs on accumulated read data and that the read data values retur ned are ignored and 0s are used instead. hardware does not clear terr; only a software write of 1 to terr clears it. 0 no transfer error on accumulated read data since software last cleared this bit. 1 a transfer error occurred on accumulated read data since software last cleared this bit.
register model UM0434 106/391 4.19.4 parallel signatur e low register (pslr) pslr, shown in table 4.19.5 , provides signature information for the low word (bits 31-0) of the ahb data read and data write buses. writ ing pslr initializes a seed value prior to enabling signature accumulation. pscr[init] can also be used to clear the pslr. pslr is unaffected by system reset, thus should be initialized by software prior to performing parallel signature operations. 4.19.5 parallel signature counter register (psctr) psctr, shown in table 4.19.6 , provides count information for signature accumulation. it is incremented on every accumulated transfer or on an mtdcr psulr,r s. writing to psctr initializes a value before enabling signature accumulation. pscr[init] can also be used to clear psctr. psctr is unaffected by system reset, thus should be initialized by software before performing parallel signature operations. . 4.19.6 parallel signature update high register (psuhr) psuhr, shown in table 98 , updates the high signature value via software. it can be written via an mtdcr psuhr, r s instruction to cause signature accumulation to occur in the pshr using the data value written. writing to this register does not cause the psctr to increment. table 95. parallel signature high register (pshr) 32 63 field high signature reset unaffected r/w r/w dcr dcr 274 table 96. parallel signature low register (pslr) 32 63 field low signature reset unaffected r/w r/w dcr dcr 275 table 97. parallel signature counter register (psctr) 32 63 field counter reset unaffected r/w r/w dcr dcr 276
UM0434 register model 107/391 4.19.7 parallel signature update low register (psulr) psulr, shown in table 99 , updates the low signature value via software. writing to psulr causes signature accumulation in the parallel signature low register (pslr) using the data value written. writing to this register causes psctr to increment. table 98. parallel signature update high register (psuhr) 32 63 field high signature update data reset unaffected r/w write only dcr dcr 277 table 99. parallel signature update low register (psulr) 32 63 field low signature update data reset unaffected r/w write only dcr dcr 278
instruction model UM0434 108/391 5 instruction model this chapter provides additional information about the book e architecture as it relates specifically to the e200z3. the e200z3 is a 32-bit implementation of the book e architecture. the book e architecture specification includes a recognition that different processor implementations may require clarifications, extensions, or deviations from the architectural descriptions. book e instructions are described in the eref: a programmer's reference manual for freescale book e processors . 5.1 operand conventions this section describes operand conventions as they are represented in the book e architecture. these conventions follow the basic descriptions in the classic powerpc architecture with some changes in terminology. for example, distinctions between user- and supervisor-level instructions are maintained, but the designations?uisa, vea, and oea? do not apply. detailed descriptions are provided on conventions used for storing values in registers and memory, for accessing processor registers, and for representing data. 5.1.1 data organization in memory and data transfers bytes in memory are numbered consecutively starting with 0. each number is the address of the corresponding byte. memory operands can be bytes, half-words, words, or double-words (consisting of two 32- bit elements) or, for the load/store multiple instruction type, a sequence of bytes or words. the address of a memory operand is the address of its first byte (that is, of its lowest- numbered byte). operand length is implicit for each instruction. 5.1.2 alignment and misaligned accesses the e200z3 core provides hardware support for misaligned memory accesses; however, there is performance degradation for accesses that cross a 64-bit (8-byte) boundary. for loads that hit in the cache, the throughput of the load/store unit is degraded to 1 misaligned load every 2 cycles. stores misaligned across a 64-bit (8 byte) boundary can be translated at a rate of 2 cycles per store. frequent use of misaligned memory accesses is discouraged because of the impact on performance. note: accesses that cross a translation boundar y may be restarted. a misaligned access that crosses a page boundary is restarted entirely if the second portion of the access causes a tlb miss. this may result in the first portion being accessed twice. accesses that cross a translation boundary where the endianness changes cause a byte- ordering data storage interrupt. note: lmw , stmw , lwarx , and stwcx. instructions that are not word aligned cause an alignment exception. 5.1.3 e200z3 floating-point implementation the e200z3 core does not implement the floating -point instructions as they are defined in book e. attempts to execute a book e?defined fl oating-point instructio n result in an illegal
UM0434 instruction model 109/391 instruction exception. however, the vector spfp apu supports single-precision vector (64- bit, two 32-bit operand) instructions, and the scalar spfp apu performs single-precision floating-point operations using the lower 32 bits of the gprs. these instructions are described in chapter 5.10.4: embedded vector and scal ar single precision floating point apu instructions on page 120 .? unlike the powerpc uisa, the spfp apus store floating- point values as single-precision values in true 32-bit, single-precision format rather than in a 64-bit double-precision format used with fprs. 5.2 unsupported instructio ns and instruction forms because the e200z3 is a 32-bit book e core, all of the instructions defined for 64-bit implementations of the book e architecture are ille gal on the e200z3 an d cause an illegal instruction exception type program interruption. the e200z3 core does not support the instructions listed in table 100 . an unimplemented instruction or floating-point-unavailable exception is generated if the processor attempts to execute one of these instructions. 5.3 optionally supported instru ctions and instruction forms the e200z3 core optionally supports the instructions listed in table 101 if a cache and/or tlb is present. an instruction exception may be generated if the processor attempts to execute one of these instructions and the related functional block is not present, or the specific instruction may be treated as a no-op. 5.4 implementation-specific instructions book e defines some instructions that are implementation specific. table 102 summarizes the e200z3 implementation-specific instructions. table 100. list of unsupported instructions type/name mnemonics string instructions lswi, lswx, stswi, stswx floating point instructions fxxxx, lfxxxx, sfxxxx, mcrfs, mffs, mtfxxx device control register and move from apid mfapidi, mfdcrx, mtdcrx table 101. list of optionally supported instructions type/name mnemonics unit cache management instructions dcba, dcbf, dcbi, dcbt, dcbtst, dcbst, dcbz icbi, icbt data cache/unified cache instruction cache/unified cache cache locking instructions dcbtls, dcbtstls, dcblc icbtls, icblc data cache/unified cache instruction cache/unified cache tlb management instructions tlbivax, tlbre, tlb sx, tlbsync, tlbwe tlb dcr management mfdcr, mtdcr dcr
instruction model UM0434 110/391 5.5 booke instruction extensions the variable length encoding (vle) provides an extension to 32-bit powerpc book e. there are additional operations defined using an alternate instruction encoding to enable reduced code footprint. this alternate encoding set is selected on an instruction page basis. a single page attribute bit selects between standard powerpc book e instruction encodings and vle instructions for that page of memory. this page attribute is an extension to the powerpc book e page attributes. pages can be freely intermixed, allowing for a mixture of code using both types of encodings. instruction encodings in pages marked as using the vle extension are either 16 or 32 bits long, and are aligned on 16-bit boundaries. therefore, all instruction pages marked as vle are required to use big-endian byte ordering. this section describes the various extensions to book e instructions to support the vle extension. rfci , rfdi , rfi ?no longer mask bit 62 of csrr0, dsrr0, or srr0 respectively. the destination address is [d,c]srr0[32:62] || 0b0. bclr , bclrl , bcctr , bcctrl ?no longer mask bit 62 of the lr or ctr respectively. the destination address is [lr,ctr][32:62] || 0b0. 5.6 memory access alignment support the e200z3 core provides hardware support for unaligned memory accesses. however, there is a performance degradation for accesses that cross a 64-bit (8 byte) boundary. for these cases, the throughput of the load/store unit is degraded to one misaligned load every 2 cycles. stores misaligned across a 64-bit (8 byte) boundary can be translated at a rate of 2 cycles per store. frequent use of unaligned memory accesses is discouraged because of the impact on performance. table 102. implementation-specific instruction summary mnemonic implementation details mfapidi unimplemented instructions mfdcrx , mtdcrx stwcx. address match with prior lwarx not required for store to be performed mfdcr , mtdcr (1) 1. the e200z3 cpu takes an illegal instruction interrupt for unsupported dcr values optionally supported instructions tlbivax tlbre tlbsx tlbsync tlbwe
UM0434 instruction model 111/391 note: accesses that cross a translation boundar y may be restarted. a misaligned access that crosses a page boundary is restarted in its enti rety in the event of a tlb miss of the second portion of the access. this may result in the first portion being accessed twice. accesses that cross a translation boundary where endianness changes cause a byte- ordering data storage interrupt. 5.7 memory synchronization and reservation instructions table 103 lists the e200z3 implementation details for the memory synchronization and load and store with reservation instructions. 5.8 branch prediction the e200z3 instruction fetching mechanism uses a branch target buffer (btb), which holds branch target addresses combined with a 2-bit saturating up-down counter scheme for branch prediction. these bits can take four valu es: strongly taken, weakly taken, weakly not taken, and strongly not taken. this mechanism is described in chapter 8.3.5: change-of- flow instruction pipeline operation on page 213 .? branch paths are predicted by a btb and subsequently checked to see if the prediction was correct. this enables operation beyond a conditional branch without waiting for the branch to table 103. memory synchronization and reservation instructions e200z3 specific details instruction e200z3 implementation msync provides synchronization and memory barrier functions. msync completes only after all preceding instructions and data memory accesses complete. subsequent instructions in the stream are not dispatched until after the msync ensures these functions have been performed. mbar behaves identically to msync ; the mbar mo field is ignored by the e200z3 core. lwarx / stwcx. implemented as described in the eref . if the ea for either instruction is not a multiple of four, an alignment interrupt is invoked. the e200z3 allows lwarx and stwcx. to access a page marked as write-through required without invo king a data storage interrupt. as book e allows, the e200z3 does not require the eas for a stwcx. and the preceding lwarx to be to the same reservation granule. reservation granularity is implementation dependent. the e200z3 does not define a reservation granule explicitly; it is defined by external logic. when no external logic is provided, the e200z3 does not compare addresses; thus, the effective implementation granularity is null. the e200z3 implements an internal status flag, hid1[ats], which is set when an lwarx completes without error. it remains set until it is cleared by one of the following: ?an stwcx. executes without error ? the e200z3 core p_rsrv_clr input is asserted. see chapter 9 .? ? the reservation is invalidated when an external interrupt is signaled and hid0[icr] is set. the e200z3 treats lwarx and stwcx. as cache-inhibited and guarded, regardless of page attributes. the e200z3 core input p_xfail_b is sampled at termination of an stwcx. store transfer to allow an external agent or mechanism to indicate that the stwcx. failed to update memory, even though a reservation existed for the store when it was issued . this is not considered an error and causes the condition codes for the stwcx. to be written as if it had no reservation. also, any outstanding reservation is cleared.
instruction model UM0434 112/391 be decoded and resolved. the instruction fetch unit predicts the direction of the branch as follows: predict not taken for any branch whose fetch address misses in the btb or hits in the btb and is predicted not taken by the counter. predict taken for any branch that hits in the btb and is predicted taken by the counter. note that the static branch prediction bit defined by the book e architecture in the bo operand is ignored. 5.9 interruption of instruct ions by interrupt requests in general, the e200z3 core samples pending external input and critical input interrupt requests at instruction boundaries. however, in order to reduce interrupt latency, long- running instructions may be interrupted prior to completion. instructions in this class include divides ( divw [ uo ][ . ], efsdiv , evfsdiv , evdivw [ su ]), load multiple word ( lmw ), and store multiple word ( stmw ). when an instruction is interrupted before completion, the value saved in srr0/csrr0 is the address of the interrupted instruction. 5.10 e200z3-specific instructions the e200z3 core implements the following instructions that are not defined by the book e architecture: the eis-defined integer select ( isel ) apu consists of the isel instruction, described in chapter 5.10.1: integer select apu .? the return from debug interrupt instruction ( rfdi ) is defined by the book e debug apu. this instruction is described in chapter 5.10.2: debug apu .? the signal processing extension (spe) apu pr ovides a set of 64-bit simd instructions. these are listed in chapter 5.10.3: spe apu instructions ,? and described in the eref . the embedded vector and scalar single-precision floating-point apus are listed along with supporting in structions in chapter 5.10.4: embedded vector and scalar single precision floating point apu instructions .? these instructions are described in detail in the eref . 5.10.1 integer select apu the integer select apu defines the integer select ( isel ) instruction, which provides a means to select one of two registers and place the result in a destination register under the control of a predicate value supplied by a bit in the condition register. isel can be used to eliminate branches in software and in many cases improve performance; it can also increase program execution time determinism by eliminating the need to predict the target and direction of the branches replaced by the integer select function. the isel instruction form and definition are described in the eref 5.10.2 debug apu the e200z3 implements the book e debug apu to support the ability to handle the debug interrupt as an additional interrupt level. to support this interrupt level, the return from debug interrupt instruction ( rfdi ) is defined as part of the debug apu, along with a pair of save/restore registers, dsrr0, and dsrr1.
UM0434 instruction model 113/391 when the debug apu is enabled (hid0[dapuen] = 1), rfdi provides a way to return from a debug interrupt. see chapter 4.13.1: hardware implementation dependent register 0 (hid0) on page 84 ,? for more information about enabling the debug apu. the instruction form and definition is provided in the eref. 5.10.3 spe apu instructions spe apu instructions treat 64-b it gprs as a vector of two 32-bit elements. (some instructions also read or wr ite 16-bit elements.) the spe apu supports a number of forms of multiply and multiply-accumulate operations, and of add and subtract to accumulator operations. the spe supports sign ed and unsigned forms, and opti onal fractional forms. for these instructions, the fractional form does not apply to unsigned forms because integer and fractional forms are identical for unsigned operands. table 104 shows how spe apu vector multiply in struction mnemonics are structured. table 105 defines mnemonic extensions for these instructions. table 104. spe apu vector multiply instruction mnemonic structure prefix multiply element data ty pe element accumulate element evm ho he hog heg wh wl whg wlg w half odd (16x16
instruction model UM0434 114/391 table 106 lists spe apu instructions. data type smf signed modulo fractional (wrap, no saturate) smi signed modulo integer (wrap, no saturate) ssf signed saturate fractional ssi signed saturate integer umi unsigned modulo integer (wrap, no saturate) usi unsigned saturate integer accumulate options a update accumulator update accumulator (no add) aa add to accumulator add result to accumulator (64-bit sum) aaw add to accumulator (words) add word results to accumulator words (p air of 32-bit sums) an add negated add negated result to accumulator (64-bit sum) anw add negated to accumulator (words) add negated word results to accumulator words (pair of 32-bit sums) table 105. mnemonic extensions for multiply-accumulate instructions extension meaning comments table 106. spe apu vector instructions instruction mnemonic syntax bit reversed increment (1) brinc r d ,r a ,r b initialize accumulator evmra r d ,r a multiply half words, even, guarded, signed, modulo, fractional and accumulate evmhegsmfaa r d ,r a ,r b multiply half words, even, guarded, signed, modulo, fractional and accumulate negative evmhegsmfan r d ,r a ,r b multiply half words, even, guarded, signe d, modulo, integer and accumulate evmhegsmiaa r d ,r a ,r b multiply half words, even, guarded, signed, modulo, integer and accumulate negative evmhegsmian r d ,r a ,r b multiply half words, even, guarded, unsigned, modulo, integer and accumulate evmhegumiaa r d ,r a ,r b multiply half words, even, guarded, un signed, modulo, integer and accumulate negative evmhegumian r d ,r a ,r b multiply half words, odd, guarded, signed, modulo, fractional and accumulate evmhogsmfaa r d ,r a ,r b multiply half words, odd, guarded, signed, modulo, fractional and accumulate negative evmhogsmfan r d ,r a ,r b multiply half words, odd, guarded, signed, modulo, integer and accumulate evmhogsmiaa r d ,r a ,r b multiply half words, odd, guarded, signed, modulo, integer and accumulate negative evmhogsmian r d ,r a ,r b multiply half words, odd, guarded, unsigned, modulo, integer and accumulate evmhogumiaa r d ,r a ,r b
UM0434 instruction model 115/391 multiply half words, odd, guarded, unsigned, modulo, integer and accumulate negative evmhogumian r d ,r a ,r b vector absolute value evabs r d ,r a vector add immediate word evaddiw r d ,r b , uimm vector add signed, modulo, integer to accumulator word evaddsmiaaw r d ,r a vector add signed, saturate, integer to accumulator word evaddssiaaw r d ,r a vector add unsigned, modulo, integer to accumulator word evaddumiaaw r d ,r a vector add unsigned, saturate, integer to accumulator word evaddusiaaw r d ,r a vector add word evaddw r d ,r a ,r b vector and evand r d ,r a ,r b vector and with complement evandc r d ,r a ,r b vector compare equal evcmpeq cr d ,r a ,r b vector compare greater than signed evcmpgts cr d ,r a ,r b vector compare greater than unsigned evcmpgtu cr d ,r a ,r b vector compare less than signed evcmplts cr d ,r a ,r b vector compare less than unsigned evcmpltu cr d ,r a ,r b vector convert floating-point from signed fraction evfscfsf r d ,r b vector convert floating-point from signed integer evfscfsi r d ,r b vector convert floating-point from unsigned fraction evfscfuf r d ,r b vector convert floating-point from unsigned integer evfscfui r d ,r b vector convert floating-point to signed fraction evfsctsf r d ,r b vector convert floating-point to signed integer evfsctsi r d ,r b vector convert floating-point to signed integer with round toward zero evfsctsiz r d ,r b vector convert floating-point to unsigned fraction evfsctuf r d ,r b vector convert floating-point to unsigned integer evfsctui r d ,r b vector convert floating-point to unsigned integer with round toward zero evfsctuiz r d ,r b vector count leading sign bits word evcntlsw r d ,r a vector count leading zeros word evcntlzw r d ,r a vector divide word signed evdivws r d ,r a ,r b vector divide word unsigned evdivwu r d ,r a ,r b vector equivalent eveqv r d ,r a ,r b vector extend sign byte evextsb r d ,r a vector extend sign half word evextsh r d ,r a vector floating-point absolute value evfsabs r d ,r a vector floating-point add evfsadd r d ,r a ,r b table 106. spe apu vector in structions (continued) instruction mnemonic syntax
instruction model UM0434 116/391 vector floating-point compare equal evfscmpeq cr d ,r a ,r b vector floating-point com pare greater than evfscmpgt cr d ,r a ,r b vector floating-point compare less than evfscmplt cr d ,r a ,r b vector floating-point divide evfsdiv r d ,r a ,r b vector floating-point multiply evfsmul r d ,r a ,r b vector floating-point negate evfsneg r d ,r a vector floating-point negative absolute value evfsnabs r d ,r a vector floating-point subtract evfssub r d ,r a ,r b vector floating-point test equal evfststeq cr d ,r a ,r b vector floating-point test greater than evfststgt cr d ,r a ,r b vector floating-point test less than evfststlt cr d ,r a ,r b vector load double into half words evldh r d ,d(r a ) vector load double into half words indexed evldhx r d ,r a ,r b vector load double into two words evldw r d ,d(r a ) vector load double into two words indexed evldwx r d ,r a ,r b vector load double word into double word evldd r d ,d(r a ) vector load double word into double word indexed evlddx r d ,r a ,r b vector load half word into half word odd signed and splat evlhhossplat r d ,d(r a ) vector load half word into half word odd signed and splat indexed evlhhossplatx r d ,r a ,r b vector load half word into half wo rd odd unsigned and splat evlhhousplat r d ,d(r a ) vector load half word into half word odd unsigned and splat indexed evlhhousplatx r d ,r a ,r b vector load half word into half words even and splat evlhhesplat r d ,d(r a ) vector load half word into half wo rds even and splat indexed evlhhesplatx r d ,r a ,r b vector load word into half words and splat evlwhsplat r d ,d(r a ) vector load word into half words and splat indexed evlwhsplatx r d ,r a ,r b vector load word into half words odd signed (with sign extension) evlwhos r d ,d(r a ) vector load word into half words odd signed indexed (with sign extension) evlwhosx r d ,r a ,r b vector load word into two half words even evlwhe r d ,d(r a ) vector load word into two half words even indexed evlwhex r d ,r a ,r b vector load word into two half wo rds odd unsigned (zero-extended) evlwhou r d ,d(r a ) vector load word into two half words odd unsigned indexed (zero-extended) evlwhoux r d ,r a ,r b vector load word into word and splat evlwwsplat r d ,d(r a ) vector load word into word and splat indexed evlwwsplatx r d ,r a ,r b vector merge high evmergehi r d ,r a ,r b vector merge high/low evmergehilo r d ,r a ,r b table 106. spe apu vector in structions (continued) instruction mnemonic syntax
UM0434 instruction model 117/391 vector merge low evmergelo r d ,r a ,r b vector merge low/high evmergelohi r d ,r a ,r b vector multiply half words, even, signed, modulo, fractional evmhesmf r d ,r a ,r b vector multiply half words, even, signed, modulo, fractional and accumulate into words evmhesmfaaw r d ,r a ,r b vector multiply half words, even, signed, modulo, fractional and accumulate negative into words evmhesmfanw r d ,r a ,r b vector multiply half words, even, signed, modulo, fractional, accumulate evmhesmfa r d ,r a ,r b vector multiply half words, even, signed, modulo, integer evmhesmi r d ,r a ,r b vector multiply half words, even, sign ed, modulo, integer and accumulate into words evmhesmiaaw r d ,r a ,r b vector multiply half words, even, si gned, modulo, integer and accumulate negative into words evmhesmianw r d ,r a ,r b vector multiply half words, even, sign ed, modulo, integer, accumulate evmhesmia r d ,r a ,r b vector multiply half words, even, signed, saturate, fractional evmhessf r d ,r a ,r b vector multiply half words, even, signed, saturate, fractional and accumulate into words evmhessfaaw r d ,r a ,r b vector multiply half words, even, signed, saturate, fractional and accumulate negative into words evmhessfanw r d ,r a ,r b vector multiply half words, even, signed, saturate, fractional, accumulate evmhessfa r d ,r a ,r b vector multiply half words, even, signed, saturate, integer and accumulate into words evmhessiaaw r d ,r a ,r b vector multiply half words, even, signed, saturate, integer and accumulate negative into words evmhessianw r d ,r a ,r b vector multiply half words, even, unsigned, modulo, integer evmheumi r d ,r a ,r b vector multiply half words, even, unsigned, modulo, integer and accumulate into words evmheumiaaw r d ,r a ,r b vector multiply half words, even, unsigned, modulo, integer and accumulate negative into words evmheumianw r d ,r a ,r b vector multiply half words, even, unsigned, modulo, integer, accumulate evmheumia r d ,r a ,r b vector multiply half words, even, unsign ed, saturate, integer and accumulate into words evmheusiaaw r d ,r a ,r b vector multiply half words, even, unsigned, saturate, integer and accumulate negative into words evmheusianw r d ,r a ,r b vector multiply half words, odd, signed, modulo, fractional evmhosmf r d ,r a ,r b vector multiply half words, odd, signed , modulo, fractional and accumulate into words evmhosmfaaw r d ,r a ,r b vector multiply half words, odd, signed, modulo, fractional and accumulate negative into words evmhosmfanw r d ,r a ,r b vector multiply half words, odd, signed, modulo, fractional, accumulate evmhosmfa r d ,r a ,r b table 106. spe apu vector in structions (continued) instruction mnemonic syntax
instruction model UM0434 118/391 vector multiply half words, odd, signed, modulo, integer evmhosmi r d ,r a ,r b vector multiply half words, odd, signed, modulo, integer and accumulate into words evmhosmiaaw r d ,r a ,r b vector multiply half words, odd, signed, modulo, integer and accumulate negative into words evmhosmianw r d ,r a ,r b vector multiply half words, odd, signed, modulo, integer, accumulate evmhosmia r d ,r a ,r b vector multiply half words, odd, signed, saturate, fractional evmhossf r d ,r a ,r b vector multiply half words, odd, signed, saturate, fractional and accumulate into words evmhossfaaw r d ,r a ,r b vector multiply half words, odd, signed , saturate, fractional and accumulate negative into words evmhossfanw r d ,r a ,r b vector multiply half words, odd, signed, saturate, fractional, accumulate evmhossfa r d ,r a ,r b vector multiply half words, odd, signed , saturate, integer and accumulate into words evmhossiaaw r d ,r a ,r b vector multiply half words, odd, si gned, saturate, integer and accumulate negative into words evmhossianw r d ,r a ,r b vector multiply half words, odd, unsigned, modulo, integer evmhoumi r d ,r a ,r b vector multiply half words, odd, unsign ed, modulo, integer and accumulate into words evmhoumiaaw r d ,r a ,r b vector multiply half words, odd, un signed, modulo, integer and accumulate negative into words evmhoumianw r d ,r a ,r b vector multiply half words, odd, unsi gned, modulo, integer, accumulate evmhoumia r d ,r a ,r b vector multiply half words, odd, unsign ed, saturate, integer and accumulate into words evmhousiaaw r d ,r a ,r b vector multiply half words, odd, unsi gned, saturate, integer and accumulate negative into words evmhousianw r d ,r a ,r b vector multiply word high signed, modulo, fractional evmwhsmf r d ,r a ,r b vector multiply word high signed, modulo, fractional and accumulate evmwhsmfa r d ,r a ,r b vector multiply word high signed, modulo, integer evmwhsmi r d ,r a ,r b vector multiply word high signed, modulo, integer and accumulate evmwhsmia r d ,r a ,r b vector multiply word high signed, saturate, fractional evmwhssf r d ,r a ,r b vector multiply word high signed, saturate, fractional and accumulate evmwhssfa r d ,r a ,r b vector multiply word high unsigned, modulo, integer evmwhumi r d ,r a ,r b vector multiply word high unsigned, modulo, integer and accumulate evmwhumia r d ,r a ,r b vector multiply word low signed, modulo, integer and accumulate in words evmwlsmiaaw r d ,r a ,r b vector multiply word low signed, modul o, integer and accumulate negative in words evmwlsmianw r d ,r a ,r b vector multiply word low signed, saturate, integer and accumulate in words evmwlssiaaw r d ,r a ,r b table 106. spe apu vector in structions (continued) instruction mnemonic syntax
UM0434 instruction model 119/391 vector multiply word low signed, saturate, integer and accumulate negative in words evmwlssianw r d ,r a ,r b vector multiply word low unsigned, modulo, integer evmwlsmi r d ,r a ,r b vector multiply word low unsigned, modulo, integer and accumulate evmwlumia r d ,r a ,r b vector multiply word low unsigned, modulo, integer and accumulate in words evmwlumiaaw r d ,r a ,r b vector multiply word low unsigned, modulo, integer and accumulate negative in words evmwlumianw r d ,r a ,r b vector multiply word low unsigned, saturate, integer and accumulate in words evmwlusiaaw r d ,r a ,r b vector multiply word low unsigned, saturate, integer and accumulate negative in words evmwlusianw r d ,r a ,r b vector multiply word signed, modulo, fractional evmwsmf r d ,r a ,r b vector multiply word signed, modulo, fractional and accumulate evmwsmfa r d ,r a ,r b vector multiply word signed, modulo, fractional and accumulate evmwsmfaa r d ,r a ,r b vector multiply word signed, modulo, fractional and accumulate negative evmwsmfan r d ,r a ,r b vector multiply word signed, modulo, integer evmwsmi r d ,r a ,r b vector multiply word signed, modulo, integer and accumulate evmwsmia r d ,r a ,r b vector multiply word signed, modulo, integer and accumulate evmwsmiaa r d ,r a ,r b vector multiply word signed, modulo, integer and accumulate negative evmwsmian r d ,r a ,r b vector multiply word signed, saturate, fractional evmwssf r d ,r a ,r b vector multiply word signed, saturate, fractional and accumulate evmwssfa r d ,r a ,r b vector multiply word signed, saturate, fractional and accumulate evmwssfaa r d ,r a ,r b vector multiply word signed, saturate, fractional and accumulate negative evmwssfan r d ,r a ,r b vector multiply word unsigned, modulo, integer evmwumi r d ,r a ,r b vector multiply word unsigned, modulo, integer and accumulate evmwumia r d ,r a ,r b vector multiply word unsigned, modulo, integer and accumulate evmwumiaa r d ,r a ,r b vector multiply word unsigned, modulo, integer and accumulate negative evmwumian r d ,r a ,r b vector nand evnand r d ,r a ,r b vector negate evneg r d ,r a vector nor evnor r d ,r a ,r b vector or evor r d ,r a ,r b vector or with complement evorc r d ,r a ,r b vector rotate left word evrlw r d ,r a ,r b vector rotate left word immediate evrlwi r d ,r a , uimm vector round word evrndw r d ,r a vector select evsel r d ,r a ,r b ,cr s vector shift left word evslw r d ,r a ,r b table 106. spe apu vector in structions (continued) instruction mnemonic syntax
instruction model UM0434 120/391 5.10.4 embedded vector and scalar single precisi on floating point apu instructions the vector and scalar spfp apus perform floating-point operations on single-precision operands. these operations ar e ieee-compliant with software interrupt handlers and offer a simpler interrupt model than the floating-point instructions defined by the powerpc isa. instead of fprs, these instructions use gprs and offer improved performance for vector shift left word immediate evslwi r d ,r a , uimm vector shift right word immediate signed evsrwis r d ,r a , uimm vector shift right word immediate unsigned evsrwiu r d ,r a , uimm vector shift right word signed evsrws r d ,r a ,r b vector shift right word unsigned evsrwu r d ,r a ,r b vector splat fractional immediate evsplatfi r d , simm vector splat immediate evsplati r d , simm vector store double of double evstdd r s ,d(r a ) vector store double of double indexed evstddx r s ,r a ,r b vector store double of four half words evstdh r s ,d(r a ) vector store double of four half words indexed evstdhx r s ,r a ,r b vector store double of two words evstdw r s ,d(r a ) vector store double of two words indexed evstdwx r s ,r a ,r b vector store word of two half words from even evstwhe r s ,d(r a ) vector store word of two half words from even indexed evstwhex r s ,r a ,r b vector store word of two half words from odd evstwho r s ,d(r a ) vector store word of two half words from odd indexed evstwhox r s ,r a ,r b vector store word of word from even evstwwe r s ,d(r a ) vector store word of word from even indexed evstwwex r s ,r a ,r b vector store word of word from odd evstwwo r s ,d(r a ) vector store word of word from odd indexed evstwwox r s ,r a ,r b vector subtract from word evsubfw r d ,r a ,r b vector subtract immediate from word evsubifw r d , uimm ,r b vector subtract signed, modulo, integer to accumulator word evsubfsmiaaw r d ,r a vector subtract signed, saturate, inte ger to accumulator word evsubfssiaaw r d ,r a vector subtract unsigned, modulo, inte ger to accumulator word evsubfumiaaw r d ,r a vector subtract unsigned, saturate, in teger to accumulator word evsubfusiaaw r d ,r a vector xor evxor r d ,r a ,r b 1. an implementation can restrict the number of bits specified in a mask. the e200z3 li mits it to 16 bits, which allows the user to perform bit-reversed address com putations for 65536-byte samples. table 106. spe apu vector in structions (continued) instruction mnemonic syntax
UM0434 instruction model 121/391 converting between floating-point, integer, and fractional values. sharing gprs allows vector floating-point instructions to use spe load and store instructions. the two spfp apus are described as follows: vector spfp instructions operate on a vector of two 32-bit, single-precision floating- point numbers that reside in the upper and lower halves of the 64-bit gprs. these instructions are listed in table 107 alongside their scalar equivalents. scalar spfp instructions operate on single 32-bit operands that reside in the lower 32 bits of the gprs. these instructions are listed in table 107 . note: both the vector and scalar versions of the instructions have the same syntax. table 107. vector and scalar spfp apu floating-point instructions instruction mnemonic syntax scalar vector convert floating-point from signed fraction efscfsf evfscfsf r d ,r b convert floating-point from signed integer efscfsi evfscfsi r d ,r b convert floating-point from unsigned fraction efscfuf evfscfuf r d ,r b convert floating-point from unsigned integer efscfui evfscfui r d ,r b convert floating-point to signed fraction efsctsf evfsctsf r d ,r b convert floating-point to signed integer efsctsi evfsctsi r d ,r b convert floating-point to signed integer with round toward zero efsctsiz evfsctsiz r d ,r b convert floating-point to unsigned fraction efsctuf evfsctuf r d ,r b convert floating-point to unsigned integer efsctui evfsctui r d ,r b convert floating-point to unsigned integer with round toward zero efsctuiz evfsctuiz r d ,r b floating-point absolute value efsabs evfsabs r d ,r a floating-point add efsadd evfsadd r d ,r a ,r b floating-point compare e qual efscmpeq evfscmpeq cr d ,r a ,r b floating-point compare greate r than efscmpgt evfscmpgt cr d ,r a ,r b floating-point compare less than efscmplt evfscmplt cr d ,r a ,r b floating-point divide efsdiv evfsdiv r d ,r a ,r b floating-point multiply efsmul evfsmul r d ,r a ,r b floating-point negate efsneg evfsneg r d ,r a floating-point negative absolute value efsnabs evfsnabs r d ,r a floating-point subtract efssub evfssub r d ,r a ,r b floating-point test equal efststeq evfststeq cr d ,r a ,r b floating-point test greater than efststgt evfststgt cr d ,r a ,r b floating-point test less than efststlt evfststlt cr d ,r a ,r b
instruction model UM0434 122/391 options for embedded floating-point apu implementations table 108 lists implementation options allowed by the embedded floating-point architecture and describes how the e200z3 handles those options. 5.11 unimplemented sprs and read only sprs the e200z3 fully decodes the spr field of mfspr and mtspr instructions. if the spr specified is undefined and not privileged, an illegal instruction exception is generated. if the spr specified is undefined and privileged and the cpu is in user mode (msr[pr] = 1), a privileged instruction exception is generated. if the spr specified is undefined and privileged and the cpu is in su pervisor mode (msr[pr] = 0), an illegal instruction exception is generated. for mtspr , if the spr specified is read-only an d not privileged, an illegal instruction exception is generated. if the spr specified is read-only and privileged and the cpu is in user mode (msr[pr] = 1, a privileged instruction exception is generated. if the spr specified is read-only and privileged and the cpu is in supervisor mode (msr[pr] = 0), an illegal instruction exce ption is generated. 5.12 invalid instruction forms table 109 describes invalid instruction forms. table 108. embedded floating-point apu options option e200z3 implementation overflow and underflow conditions may be signaled by doing exponent evaluation of the operation. if an examining of the exponents determines that an overflow or underflow could occur, the implementation may choose to signal an overflow or underflow. follows the recommendation; does not use the estimation. if an operand for a calculation or conversion is denormalized, the implementation may choose to use a same-signed zero value in place of the denormalized operand. uses a same-signed zero value in place of the denormalized operand. +infinity and -infinity rounding modes are not required to be handled by an implementation. if an implementation does not support infinity rounding modes and the rounding mode is set to be +infinity or -infinity, an embedded floating-point round interrupt occurs after every floating-point instruction for which rounding may occur, regardless of the value of finxe, unless an embedded floating-point data interrupt also occurs and is taken. supports rounding to infinity. for absolute value, negate, and negative abs olute value operations, an implementation may choose either to simply perform the sign bit operation recognizing interrupts or to compute the operation and handle except ions and saturation where appropriate. a sign bit operation is performed; interrupts are taken. spefscr fgh and fxh bits ar e undefined upon th e completion of a scalar floating- point operation. an implementation may choo se to clear them or leave them unchanged. always clears these bits for such operations. an implementation may choose to only implement sticky bit setting by hardware for fdbzs and finxs, allowing software to manage the other sticky bits. it is recommended that all future implementations implem ent all sticky bit settings in hardware. implements all sticky bit settings in hardware.
UM0434 instruction model 123/391 5.13 instruction summary in addition to the spe instructions listed in table 106 and the floating-point instructions listed in table 107 , the e200z3 implements the instructions defined in table 110 and table 111 . instructions not listed in these tables are not supported by the e200z3 core and signal an illegal, unimpl emented, or floating-point unava ilable exception. implementation- dependent instructions are identified with a footnote. note: specific apus are not included in the table below: spe apu vle extension 5.13.1 instruction index sorted by mnemonic table 110 lists instructions by mnemonic. table 109. invalid instruction forms instructions descriptions load and store with update book e defines as an invalid form the case when a load with update instruction specifies the same register in the r d and r a field of the instruction. for this invalid case, the e200z3 core performs the instruction and updates the register with the load data. in addition, if r a = 0 for any load or store with update instruction, the e200z3 core updates r a (gpr0). load multiple word ( lmw ) book e defines as invalid any form of lmw instruction in which r a is in the range of registers to be loaded, including the case in which r a = 0. on the e200z3, invalid forms of lmw execute as follows: ? case 1: r a is in the range of r d, r a in this case address generation for all loads to register targets r d=0 to r d = 31 is done substituting the value of 0 for r a. branch conditional to count register [and link] book e defines as invalid any bcctr or bcctrl instruction that specifies the decrement and test ctr (bo[2] = 0) option. the e200z3 executes instructions with these invalid forms by decrementing the ctr and branching to the location specified by the pre-decremented ct r value if all cr and ctr conditions are met as specified by the other bo field settings. instructions with non- zero reserved fields book e defines certain bit fields in various instructio ns as reserved and specifies that these fields be set to zero. following the book e recommendation, the e200z3 ignores the value of the reserved field (bit 31) in x-form integer load and store instructions. the e200z3 ignores the value of the reserved ?z? bits in the bo field of branch in structions. for all other instructions, the e200z3 generates an illegal instruction exception if a reserved field is non-zero. table 110. instructions sorted by mnemonic format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 ) x 011111 01000 01010 0 add add x 011111 01000 01010 1 add. add & record cr
instruction model UM0434 124/391 x 011111 00000 01010 0 addc add carrying x 011111 00000 01010 1 addc. add carrying & record cr x 011111 10000 01010 0 addco add carrying & record ov x 011111 10000 01010 1 addco. add carrying & record ov & cr x 011111 00100 01010 0 adde add extended with ca x 011111 00100 01010 1 adde. add extended with ca & record cr x 011111 10100 01010 0 addeo add extended with ca & record ov x 011111 10100 01010 1 addeo. add extended with ca & record ov & cr d 001110 ????? ????? ? addi add immediate d 001100 ????? ????? ? addic add immediate carrying d 001101 ????? ????? ? addic. add immediate carrying & record cr d 001111 ????? ????? ? addis add immediate shifted x 011111 00111 01010 0 addme add to minus one extended with ca x 011111 00111 01010 1 addme. add to minus one extended with ca & record cr x 011111 10111 01010 0 addmeo add to minus one extended with ca & record ov x 011111 10111 01010 1 addmeo. add to minus one extended with ca & record ov & cr x 011111 11000 01010 0 addo add & record ov x 011111 11000 01010 1 addo. add & record ov & cr x 011111 00110 01010 0 addze add to zero extended with ca x 011111 00110 01010 1 addze. add to zero extended with ca & record cr x 011111 10110 01010 0 addzeo add to zero extended with ca & record ov x 011111 10110 01010 1 addzeo. add to zero extended with ca & record ov & cr x 011111 00000 11100 0 and and x 011111 00000 11100 1 and. and & record cr x 011111 00001 11100 0 andc and with complement x 011111 00001 11100 1 andc. and with complement & record cr d 011100 ????? ????? ? andi. and immediate and record cr d 011101 ????? ????? ? andis. and immediate shifted and record cr i 010010 ????? ????0 0 b branch i 010010 ????? ????1 0 ba branch absolute b 010000 ????? ????0 0 bc branch conditional b 010000 ????? ????1 0 bca branch conditional absolute xl 010011 10000 10000 0 bcctr branch conditional to count register table 110. instructions sorted by mnemonic (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
UM0434 instruction model 125/391 xl 010011 10000 10000 1 bcctrl branch conditional to count register and link b 010000 ????? ????0 1 bcl branch conditional and link b 010000 ????? ????1 1 bcla branch conditional and link absolute xl 010011 00000 10000 0 bclr branch conditional to link register xl 010011 00000 10000 1 bclrl branch conditional to link register and link i 010010 ????? ????0 1 bl branch and link i 010010 ????? ????1 1 bla branch and link absolute x 011111 00000 00000 / cmp compare d 001011 ????? ????? ? cmpi compare immediate x 011111 00001 00000 / cmpl compare logical d 001010 ????? ????? ? cmpli compare logical immediate x 011111 00000 11010 0 cntlzw count leading zeros word x 011111 00000 11010 1 cntlzw. count leading zeros word and record cr xl 010011 01000 00001 / crand condition register and xl 010011 00100 00001 / crandc condition register and with complement xl 010011 01001 00001 / creqv condition register equivalent xl 010011 00111 00001 / crnand condition register nand xl 010011 00001 00001 / crnor condition register nor xl 010011 01110 00001 / cror condition register or xl 010011 01101 00001 / crorc condition register or with complement xl 010011 00110 00001 / crxor condition register xor x 011111 10111 10110 / dcba data cache block allocate x 011111 00010 10110 / dcbf data cache block flush x 011111 01110 10110 / dcbi data cache block invalidate x 011111 00001 10110 / dcbst data cache block store x 011111 01000 10110 / dcbt data cache block touch x 011111 00111 10110 / dcbtst data cache block touch for store x 011111 11111 10110 / dcbz data cache block set to zero x 011111 01111 01011 0 divw divide word x 011111 01111 01011 1 divw. divide word and record cr x 011111 11111 01011 0 divwo divide word and record ov x 011111 11111 01011 1 divwo. divide word and record ov and cr x 011111 01110 01011 0 divwu divide word unsigned table 110. instructions sorted by mnemonic (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
instruction model UM0434 126/391 x 011111 01110 01011 1 divwu. divide word unsigned and record cr x 011111 11110 01011 0 divwuo divide word unsigned and record ov x 011111 11110 01011 1 divwuo. divide word unsigned and record ov and cr x 011111 01000 11100 0 eqv equivalent x 011111 01000 11100 1 eqv. equivalent and record cr x 011111 11101 11010 0 extsb extend sign byte x 011111 11101 11010 1 extsb. extend sign byte and record cr x 011111 11100 11010 0 extsh extend sign half word x 011111 11100 11010 1 extsh. extend sign half word and record cr x 111111 01000 01000 0 fabs (1) floating absolute value x 111111 01000 01000 1 fabs. (1) floating absolute value and record cr a 111111 ????? 10101 0 fadd1 (1) floating add a 111111 ????? 10101 1 fadd. (1) floating add and record cr a 111011 ????? 10101 0 fadds (1) floating add single a 111011 ????? 10101 1 fadds. (1) floating add single and record cr x 111111 11010 01110 / fcfid (1) floating convert from int doubleword x 111111 00001 00000 / fcmpo (1) floating compare ordered x 111111 00000 00000 / fcmpu (1) floating compare unordered x 111111 11001 01110 / fctid (1) floating convert to int doubleword x 111111 11001 01111 / fctidz (1) floating convert to int doubleword with round to zero x 111111 00000 01110 0 fctiw (1) floating convert to int word x 111111 00000 01110 1 fctiw. (1) floating convert to int word and record cr x 111111 00000 01111 0 fctiwz (1) floating convert to int wo rd with round to zero x 111111 00000 01111 1 fctiwz. (1) floating convert to int word with round to zero & record cr a 111111 ????? 10010 0 fdiv (1) floating divide a 111111 ????? 10010 1 fdiv. (1) floating divide and record cr a 111011 ????? 10010 0 fdivs (1) floating divide single a 111011 ????? 10010 1 fdivs. (1) floating divide single and record cr a 111111 ????? 11101 0 fmadd (1) floating multiply-add a 111111 ????? 11101 1 fmadd. (1) floating multiply-add and record cr a 111011 ????? 11101 0 fmadds (1) floating multiply-add single a 111011 ????? 11101 1 fmadds. (1) floating multiply-add single and record cr x 111111 00010 01000 0 fmr (1) floating move register table 110. instructions sorted by mnemonic (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
UM0434 instruction model 127/391 x 111111 00010 01000 1 fmr. (1) floating move register and record cr a 111111 ????? 11100 0 fmsub (1) floating multiply-subtract a 111111 ????? 11100 1 fmsub. (1) floating multiply-subtract and record cr a 111011 ????? 11100 0 fmsubs (1) floating multiply-subtract single a 111011 ????? 11100 1 fmsubs. (1) floating multiply-subtract single and record cr a 111111 ????? 11001 0 fmul (1) floating multiply a 111111 ????? 11001 1 fmul. (1) floating multiply and record cr a 111011 ????? 11001 0 fmuls (1) floating multiply single a 111011 ????? 11001 1 fmuls. (1) floating multiply single and record cr x 111111 00100 01000 0 fnabs (1) floating negative absolute value x 111111 00100 01000 1 fnabs. (1) floating negative absolute value and record cr x 111111 00001 01000 0 fneg (1) floating negate x 111111 00001 01000 1 fneg. (1) floating negate and record cr a 111111 ????? 11111 0 fnmadd (1) floating negative multiply-add a 111111 ????? 11111 1 fnmadd. (1) floating negative multiply-add and record cr a 111011 ????? 11111 0 fnmadds (1) floating negative multiply-add single a 111011 ????? 11111 1 fnmadds (1) floating negative multiply-add single and record cr a 111111 ????? 11110 0 fnmsub (1) floating negative multiply-subtract a 111111 ????? 11110 1 fnmsub. (1) floating negative multiply-subtract and record cr a 111011 ????? 11110 0 fnmsubs (1) floating negative multiply-subtract single a 111011 ????? 11110 1 fnmsubs (1) floating negative multiply-subtract single and record cr a 111011 ????? 11000 0 fres (1) floating reciprocal estimate single a 111011 ????? 11000 1 fres. (1) floating reciprocal estimate single and record cr x 111111 00000 01100 0 frsp (1) floating round to single-precision x 111111 00000 01100 1 frsp. (1) floating round to single-precision and record cr a 111111 ????? 11010 0 frsqrte (1) floating reciprocal square root estimate a 111111 ????? 11010 1 frsqrte. (1) floating reciprocal square root estimate and record cr a 111111 ????? 10111 0 fsel (1) floating select a 111111 ????? 10111 1 fsel. (1) floating select and record cr a 111111 ????? 10110 0 fsqrt (1) floating square root a 111111 ????? 10110 1 fsqrt. (1) floating square root and record cr a 111011 ????? 10110 0 fsqrts (1) floating square root single a 111011 ????? 10110 1 fsqrts. (1) floating square root single and record cr table 110. instructions sorted by mnemonic (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
instruction model UM0434 128/391 a 111111 ????? 10100 0 fsub (1) floating subtract a 111111 ????? 10100 1 fsub. (1) floating subtract and record cr a 111011 ????? 10100 0 fsubs (1) floating subtract single a 111011 ????? 10100 1 fsubs. (1) floating subtract single and record cr x 011111 11110 10110 / icbi instruction cache block invalidate x 011111 00000 10110 / icbt instruction cache block touch x 011111 ????? 01111 / isel (2) integer select xl 010011 00100 10110 / isync instruction synchronize d 100010 ????? ????? ? lbz load byte and zero d 100011 ????? ????? ? lbzu load byte and zero with update x 011111 00011 10111 / lbzux load byte and zero with update indexed x 011111 00010 10111 / lbzx load byte and zero indexed d 110010 ????? ????? ? lfd (1) load floating-point double d 110011 ????? ????? ? lfdu (1) load floating-point double with update x 011111 10011 10111 / lfdux (1) load floating-point double with update indexed x 011111 10010 10111 / lfdx (1) load floating-point double indexed d 110000 ????? ????? ? lfs (1) load floating-point single d 110001 ????? ????? ? lfsu (1) load floating-point single with update x 011111 10001 10111 / lfsux (1) load floating-point single with update indexed x 011111 10000 10111 / lfsx (1) load floating-point single indexed d 101010 ????? ????? ? lha load half word algebraic d 101011 ????? ????? ? lhau load half word algebraic with update x 011111 01011 10111 / lhaux load half word algebraic with update indexed x 011111 01010 10111 / lhax load half word algebraic indexed x 011111 11000 10110 / lhbrx load half word byte-reverse indexed d 101000 ????? ????? ? lhz load half word and zero d 101001 ????? ????? ? lhzu load half word and zero with update x 011111 01001 10111 / lhzux load half word and zero with update indexed x 011111 01000 10111 / lhzx load half word and zero indexed d 101110 ????? ????? ? lmw load multiple word x 011111 10010 10101 / lswi (3) load string word immediate x 011111 10000 10101 / lswx (3) load string word indexed x 011111 00000 10100 / lwarx (4) load word and reserve indexed table 110. instructions sorted by mnemonic (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
UM0434 instruction model 129/391 x 011111 10000 10110 / lwbrx load word byte-reverse indexed d 100000 ????? ????? ? lwz load word and zero d 100001 ????? ????? ? lwzu load word and zero with update x 011111 00001 10111 / lwzux load word and zero with update indexed x 011111 00000 10111 / lwzx load word and zero indexed x 011111 11010 10110 / mbar (4) memory barrier xl 010011 00000 00000 / mcrf move condition register field x 111111 00010 00000 / mcrfs (1) move to condition register from fpscr x 011111 10000 00000 / mcrxr move to condition register from xer x 011111 01000 10011 / mfapidi 3 move from apid indirect x 011111 00000 10011 / mfcr move from condition register xfx 011111 01010 00011 / mfdcr (3) move from device control register x 011111 01000 00011 / mfdcrx (3) move from device control register indexed x 111111 10010 00111 0 mffs (1) move from fpscr x 111111 10010 00111 1 mffs. (1) move from fpscr and record cr x 011111 00010 10011 / mfmsr move from machine state register xfx 011111 01010 10011 / mfspr move from special purpose register x 011111 10010 10110 / msync (4) memory synchronize xfx 011111 00100 10000 / mtcrf move to condition register fields xfx 011111 01110 00011 / mtdcr (3) move to device control register x 011111 01100 00011 / mtdcrx (3) move to device control register indexed x 111111 00010 00110 0 mtfsb0 (1) move to fpscr bit 0 x 111111 00010 00110 1 mtfsb0. (1) move to fpscr bit 0 and record cr x 111111 00001 00110 0 mtfsb1 (1) move to fpscr bit 1 x 111111 00001 00110 1 mtfsb1. (1) move to fpscr bit 1 and record cr xfl 111111 10110 00111 0 mtfsf (1) move to fpscr fields xfl 111111 10110 00111 1 mtfsf. (1) move to fpscr fields and record cr x 111111 00100 00110 0 mtfsfi (1) move to fpscr field immediate x 111111 00100 00110 1 mtfsfi. (1) move to fpscr field immediate and record cr x 011111 00100 10010 / mtmsr move to machine state register xfx 011111 01110 10011 / mtspr move to special purpose register x 011111 /0010 01011 0 mulhw multiply high word x 011111 /0010 01011 1 mulhw. multiply high word and record cr table 110. instructions sorted by mnemonic (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
instruction model UM0434 130/391 x 011111 /0000 01011 0 mulhwu multiply high word unsigned x 011111 /0000 01011 1 mulhwu. multiply high word unsigned and record cr d 000111 ????? ????? ? mulli multiply low immediate x 011111 00111 01011 0 mullw multiply low word x 011111 00111 01011 1 mullw. multiply low word and record cr x 011111 10111 01011 0 mullwo multiply low word and record ov x 011111 10111 01011 1 mullwo. multiply low word and record ov and cr x 011111 01110 11100 0 nand nand x 011111 01110 11100 1 nand. nand and record cr x 011111 00011 01000 0 neg negate x 011111 00011 01000 1 neg. negate and record cr x 011111 10011 01000 0 nego negate and record ov x 011111 10011 01000 1 nego. negate and record ov and record cr x 011111 00011 11100 0 nor nor x 011111 00011 11100 1 nor. nor and record cr x 011111 01101 11100 0 or or x 011111 01101 11100 1 or. or and record cr x 011111 01100 11100 0 orc or with complement x 011111 01100 11100 1 orc. or with compleme nt and record cr d 011000 ????? ????? ? ori or immediate d 011001 ????? ????? ? oris or immediate shifted xl 010011 00001 10011 / rfci return from critical interrupt xl 010011 00001 00111 / rfdi (5) return from debug interrupt xl 010011 00001 10010 / rfi return from interrupt m 010100 ????? ????? 0 rlwimi rotate left word immed then mask insert m 010100 ????? ????? 1 rlwimi. rotate left word immed then mask insert and record cr m 010101 ????? ????? 0 rlwinm rotate left word immed then and with mask m 010101 ????? ????? 1 rlwinm. rotate left word immed then and with mask & record cr m 010111 ????? ????? 0 rlwnm rotate left word then and with mask m 010111 ????? ????? 1 rlwnm. rotate left word then a nd with mask and record cr sc 010001 / / / / / / / / /1 / sc system call x 011111 00000 11000 0 slw shift left word x 011111 00000 11000 1 slw. shift left word and record cr table 110. instructions sorted by mnemonic (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
UM0434 instruction model 131/391 x 011111 11000 11000 0 sraw shift right algebraic word x 011111 11000 11000 1 sraw. shift right algebraic word and record cr x 011111 11001 11000 0 srawi shift right algebraic word immediate x 011111 11001 11000 1 srawi. shift right algebraic word immediate and record cr x 011111 10000 11000 0 srw shift right word x 011111 10000 11000 1 srw. shift right word and record cr d 100110 ????? ????? ? stb store byte d 100111 ????? ????? ? stbu store byte with update x 011111 00111 10111 / stbux store byte with update indexed x 011111 00110 10111 / stbx store byte indexed d 110110 ????? ????? ? stfd (1) store floating-point double d 110111 ????? ????? ? stfdu (1) store floating-point double with update x 011111 10111 10111 / stfdux (1) store floating-point double with update indexed x 011111 10110 10111 / stfdx (1) store floating-point double indexed x 011111 11110 10111 / stfiwx (1) store floating-point as int word indexed d 110100 ????? ????? ? stfs (1) store floating-point single d 110101 ????? ????? ? stfsu (1) store floating-point single with update x 011111 10101 10111 / stfsux (1) store floating-point single with update indexed x 011111 10100 10111 / stfsx (1) store floating-point single indexed d 101100 ????? ????? ? sth store half word x 011111 11100 10110 / sthbrx store half word byte-reverse indexed d 101101 ????? ????? ? sthu store half word with update x 011111 01101 10111 / sthux store half word with update indexed x 011111 01100 10111 / sthx store half word indexed d 101111 ????? ????? ? stmw store multiple word x 011111 10110 10101 / stswi (3) store string word immediate x 011111 10100 10101 / stswx (3) store string word indexed d 100100 ????? ????? ? stw store word x 011111 10100 10110 / stwbrx store word byte-reverse indexed x 011111 00100 10110 1 stwcx. (4) store word conditional indexed and record cr d 100101 ????? ????? ? stwu store word with update x 011111 00101 10111 / stwux store word with update indexed x 011111 00100 10111 / stwx store word indexed table 110. instructions sorted by mnemonic (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
instruction model UM0434 132/391 x 011111 00001 01000 0 subf subtract from x 011111 00001 01000 1 subf. subtract from and record cr x 011111 00000 01000 0 subfc subtract from carrying x 011111 00000 01000 1 subfc. subtract from carrying and record cr x 011111 10000 01000 0 subfco subtract from carrying and record ov x 011111 10000 01000 1 subfco. subtract from carrying and record ov and cr x 011111 00100 01000 0 subfe subtract from extended with ca x 011111 00100 01000 1 subfe. subtract from extended with ca and record cr x 011111 10100 01000 0 subfeo subtract from extended with ca and record ov x 011111 10100 01000 1 subfeo. subtract from extended with ca and record ov and cr d 001000 ????? ????? ? subfic subtract from immediate carrying x 011111 00111 01000 0 subfme subtract from minus one extended with ca x 011111 00111 01000 1 subfme. subtract from minus one extended with ca & record cr x 011111 10111 01000 0 subfmeo subtract from minus one extended with ca and record ov x 011111 10111 01000 1 subfmeo. subtract from minus one extended with ca & record ov & cr x 011111 10001 01000 0 subfo subtract from and record ov x 011111 10001 01000 1 subfo. subtract from and record ov and cr x 011111 00110 01000 0 subfze subtract from zero extended with ca x 011111 00110 01000 1 subfze. subtract from zero extended with ca and record cr x 011111 10110 01000 0 subfzeo subtract from zero extended with ca and record ov x 011111 10110 01000 1 subfzeo. subtract from zero extended with ca & record ov and cr x 011111 11000 10010 / tlbivax tlb invalidate virtual address indexed x 011111 11101 10010 / tlbre tlb read entry x 011111 11100 10010 / tlbsx tlb search indexed x 011111 10001 10110 / tlbsync tlb synchronize x 011111 11110 10010 / tlbwe tlb write entry x 011111 00000 00100 / tw trap word d 000011 ????? ????? ? twi trap word immediate x 011111 00100 00011 / wrtee write external enable x 011111 00101 00011 / wrteei write external enable immediate x 011111 01001 11100 0 xor xor x 011111 01001 11100 1 xor. xor and record cr table 110. instructions sorted by mnemonic (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
UM0434 instruction model 133/391 5.13.2 instruction index sorted by opcode table 111 lists instructions by opcode. d 011010 ????? ????? ? xori xor immediate d 011011 ????? ????? ? xoris xor immediate shifted 1. attempted execution causes an unimplem ented exception if msr[fp]=1, or an fp unavailable exception if msr[fp]=0. 2. eis-defined isel instruction, refer to chapter 5.10.1: integer select apu on page 112 .? 3. the core cpu will take an illegal instru ction exception for unsupported dcr values. 4. see chapter 5.7: memory synchronization and reservation instructions on page 111 . ? 5. see chapter 5.10.2: debug apu on page 112 . ? table 110. instructions sorted by mnemonic (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 ) legend: - don?t care, usually part of an operand field / reserved bit, invalid instruction form if encoded as 1 ? allocated for implementation-dependent use. table 111. instructions sorted by opcode format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 ) d 000011 ????? ????? ? twi trap word immediate d 000111 ????? ????? ? mulli multiply low immediate d 001000 ????? ????? ? subfic subtract from immediate carrying d 001010 ????? ????? ? cmpli compare logical immediate d 001011 ????? ????? ? cmpi compare immediate d 001100 ????? ????? ? addic add immediate carrying d 001101 ????? ????? ? addic. add immediate carrying and record cr d 001110 ????? ????? ? addi add immediate d 001111 ????? ????? ? addis add immediate shifted b 010000 ????? ????0 0 bc branch conditional b 010000 ????? ????0 1 bcl branch conditional and link b 010000 ????? ????1 0 bca branch conditional absolute b 010000 ????? ????1 1 bcla branch conditional and link absolute sc 010001 / / / / / / / / / 1 / sc system call
instruction model UM0434 134/391 i 010010 ????? ????0 0 b branch i 010010 ????? ????0 1 bl branch and link i 010010 ????? ????1 0 ba branch absolute i 010010 ????? ????1 1 bla branch and link absolute xl 010011 00000 00000 / mcrf move condition register field xl 010011 00000 10000 0 bclr branch conditional to link register xl 010011 00000 10000 1 bclrl branch conditional to link register and link xl 010011 00001 00001 / crnor condition register nor xl 010011 00001 00111 / rfdi return from debug interrupt xl 010011 00001 10010 / rfi return from interrupt xl 010011 00001 10011 / rfci return from critical interrupt xl 010011 00100 00001 / crandc condition register and with complement xl 010011 00100 10110 / isync instruction synchronize xl 010011 00110 00001 / crxor condition register xor xl 010011 00111 00001 / crnand condition register nand xl 010011 01000 00001 / crand condition register and xl 010011 01001 00001 / creqv condition register equivalent xl 010011 01101 00001 / crorc condition register or with complement xl 010011 01110 00001 / cror condition register or xl 010011 10000 10000 0 bcctr branch conditional to count register xl 010011 10000 10000 1 bcctrl branch conditional to count register and link m 010100 ????? ????? 0 rlwimi rotate left word immed then mask insert m 010100 ????? ????? 1 rlwimi. rotate left word immed then mask insert and record cr m 010101 ????? ????? 0 rlwinm rotate left word immed then and with mask m 010101 ????? ????? 1 rlwinm. rotate left word immed then and with mask and record cr m 010111 ????? ????? 0 rlwnm rotate left word then and with mask m 010111 ????? ????? 1 rlwnm. rotate left word then and with mask and record cr d 011000 ????? ????? ? ori or immediate d 011001 ????? ????? ? oris or immediate shifted d 011010 ????? ????? ? xori xor immediate d 011011 ????? ????? ? xoris xor immediate shifted d 011100 ????? ????? ? andi. and immediate and record cr d 011101 ????? ????? ? andis. and immediate shifted and record cr table 111. instructions sorted by opcode (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
UM0434 instruction model 135/391 ?? 011111 ????? 01111 / isel integer select x 011111 00000 00000 / cmp compare x 011111 00000 00100 / tw trap word x 011111 00000 01000 0 subfc subtract from carrying x 011111 00000 01000 1 subfc. subtract from carrying and record cr x 011111 00000 01010 0 addc add carrying x 011111 00000 01010 1 addc. add carrying and record cr x 011111 /0000 01011 0 mulhwu multiply high word unsigned x 011111 /0000 01011 1 mulhwu. multiply high word unsigned and record cr x 011111 00000 10011 / mfcr move from condition register x 011111 00000 10100 / lwarx load word and reserve indexed x 011111 00000 10110 / icbt instruction cache block touch x 011111 00000 10111 / lwzx load word and zero indexed x 011111 00000 11000 0 slw shift left word x 011111 00000 11000 1 slw. shift left word and record cr x 011111 00000 11010 0 cntlzw count leading zeros word x 011111 00000 11010 1 cntlzw. count leading zeros word and record cr x 011111 00000 11100 0 and and x 011111 00000 11100 1 and. and and record cr x 011111 00001 00000 / cmpl compare logical x 011111 00001 01000 0 subf subtract from x 011111 00001 01000 1 subf. subtract from and record cr x 011111 00001 10110 / dcbst data cache block store x 011111 00001 10111 / lwzux load word and zero with update indexed x 011111 00001 11100 0 andc and with complement x 011111 00001 11100 1 andc. and with complement and record cr x 011111 /0010 01011 0 mulhw multiply high word x 011111 /0010 01011 1 mulhw. multiply high word and record cr x 011111 00010 10011 / mfmsr move from machine state register x 011111 00010 10110 / dcbf data cache block flush x 011111 00010 10111 / lbzx load byte and zero indexed x 011111 00011 01000 0 neg negate x 011111 00011 01000 1 neg. negate and record cr table 111. instructions sorted by opcode (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
instruction model UM0434 136/391 x 011111 00011 10111 / lbzux load byte and zero with update indexed x 011111 00011 11100 0 nor nor x 011111 00011 11100 1 nor. nor and record cr x 011111 00100 00011 / wrtee write external enable x 011111 00100 01000 0 subfe subtract from extended with ca x 011111 00100 01000 1 subfe. subtract fr om extended with ca and record cr x 011111 00100 01010 0 adde add extended with ca x 011111 00100 01010 1 adde. add extended with ca and record cr xfx 011111 00100 10000 / mtcrf move to condition register fields x 011111 00100 10010 / mtmsr move to machine state register x 011111 00100 10110 1 stwcx. store word conditional indexed and record cr x 011111 00100 10111 / stwx store word indexed x 011111 00101 00011 / wrteei write external enable immediate x 011111 00101 10111 / stwux store word with update indexed x 011111 00110 01000 0 subfze subtract from zero extended with ca x 011111 00110 01000 1 subfze. subtract from zero extended with ca and record cr x 011111 00110 01010 0 addze add to zero extended with ca x 011111 00110 01010 1 addze. add to zero extended with ca and record cr x 011111 00110 10111 / stbx store byte indexed x 011111 00111 01000 0 subfme subtract from minus one extended with ca x 011111 00111 01000 1 subfme. subtract from minus one extended with ca and record cr x 011111 00111 01010 0 addme add to minus one extended with ca x 011111 00111 01010 1 addme. add to minus one extended with ca and record cr x 011111 00111 01011 0 mullw multiply low word x 011111 00111 01011 1 mullw. multiply low word and record cr x 011111 00111 10110 / dcbtst data cache block touch for store x 011111 00111 10111 / stbux store byte with update indexed x 011111 01000 00011 / mfdcrx move from device control register indexed x 011111 01000 01010 0 add add x 011111 01000 01010 1 add. add and record cr x 011111 01000 10011 / mfapidi move from apid indirect x 011111 01000 10110 / dcbt data cache block touch x 011111 01000 10111 / lhzx load halfword and zero indexed table 111. instructions sorted by opcode (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
UM0434 instruction model 137/391 x 011111 01000 11100 0 eqv equivalent x 011111 01000 11100 1 eqv. equivalent and record cr x 011111 01001 10111 / lhzux load halfword and zero with update indexed x 011111 01001 11100 0 xor xor x 011111 01001 11100 1 xor. xor and record cr xfx 011111 01010 00011 / mfdcr move from device control register xfx 011111 01010 10011 / mfspr move from special purpose register x 011111 01010 10111 / lhax load halfword algebraic indexed x 011111 01011 10111 / lhaux load halfword algebraic with update indexed x 011111 01100 00011 / mtdcrx move to device control register indexed x 011111 01100 10111 / sthx store halfword indexed x 011111 01100 11100 0 orc or with complement x 011111 01100 11100 1 orc. or with complement and record cr x 011111 01101 10111 / sthux store halfword with update indexed x 011111 01101 11100 0 or or x 011111 01101 11100 1 or. or and record cr xfx 011111 01110 00011 / mtdcr move to device control register x 011111 01110 01011 0 divwu divide word unsigned x 011111 01110 01011 1 divwu. divide word unsigned and record cr xfx 011111 01110 10011 / mtspr move to special purpose register x 011111 01110 10110 / dcbi data cache block invalidate x 011111 01110 11100 0 nand nand x 011111 01110 11100 1 nand. nand and record cr x 011111 01111 01011 0 divw divide word x 011111 01111 01011 1 divw. divide word and record cr x 011111 10000 00000 / mcrxr move to condition register from xer x 011111 10000 01000 0 subfco subtract from carrying and record ov x 011111 10000 01000 1 subfco. subtract from carrying and record ov and cr x 011111 10000 01010 0 addco add carrying and record ov x 011111 10000 01010 1 addco. add carrying and record ov and cr x 011111 10000 10101 / lswx load string word indexed x 011111 10000 10110 / lwbrx load word byte-reverse indexed x 011111 10000 10111 / lfsx load floating-point single indexed table 111. instructions sorted by opcode (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
instruction model UM0434 138/391 x 011111 10000 11000 0 srw shift right word x 011111 10000 11000 1 srw. shift right word and record cr x 011111 10001 01000 0 subfo subtract from and record ov x 011111 10001 01000 1 subfo. subtract from and record ov and cr x 011111 10001 10110 / tlbsync tlb synchronize x 011111 10001 10111 / lfsux load floating-point single with update indexed x 011111 10010 10101 / lswi load string word immediate x 011111 10010 10110 / msync memory synchronize x 011111 10010 10111 / lfdx load floating-point double indexed x 011111 10011 01000 0 nego negate and record ov x 011111 10011 01000 1 nego. negate and record ov and record cr x 011111 10011 10111 / lfdux load floating-point double with update indexed x 011111 10100 01000 0 subfeo subtract from extended with ca and record ov x 011111 10100 01000 1 subfeo. subtract from extended with ca and record ov and cr x 011111 10100 01010 0 addeo add extended with ca and record ov x 011111 10100 01010 1 addeo. add extended with ca and record ov and cr x 011111 10100 10101 / stswx store string word indexed x 011111 10100 10110 / stwbrx store word byte-reverse indexed x 011111 10100 10111 / stfsx store floating-point single indexed x 011111 10101 10111 / stfsux store floating-point single with update indexed x 011111 10110 01000 0 subfzeo subtract from zero extended with ca and record ov x 011111 10110 01000 1 subfzeo. subtract from zero extended with ca and record ov and cr x 011111 10110 01010 0 addzeo add to zero extended with ca and record ov x 011111 10110 01010 1 addzeo. add to zero extended with ca and record ov and cr x 011111 10110 10101 / stswi store string word immediate x 011111 10110 10111 / stfdx store floating-point double indexed x 011111 10111 01000 0 subfmeo subtract from minus one extended with ca and record ov x 011111 10111 01000 1 subfmeo. subtract from minus one extended with ca & record ov & cr x 011111 10111 01010 0 addmeo add to minus one extended with ca and record ov x 011111 10111 01010 1 addmeo. add to minus one extended with ca and record ov and cr x 011111 10111 01011 0 mullwo multiply low word and record ov x 011111 10111 01011 1 mullwo. multiply low word and record ov and cr table 111. instructions sorted by opcode (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
UM0434 instruction model 139/391 x 011111 10111 10110 / dcba data cache block allocate x 011111 10111 10111 / stfdux store floating- point double with update indexed x 011111 11000 01010 0 addo add and record ov x 011111 11000 01010 1 addo. add and record ov and cr x 011111 11000 10010 / tlbivax tlb invalidate virtual address indexed x 011111 11000 10110 / lhbrx load halfword byte-reverse indexed x 011111 11000 11000 0 sraw shift right algebraic word x 011111 11000 11000 1 sraw. shift right algebraic word and record cr x 011111 11001 11000 0 srawi shift right algebraic word immediate x 011111 11001 11000 1 srawi. shift right algebraic word immediate and record cr x 011111 11010 10110 / mbar memory barrier x 011111 11100 10010 ? tlbsx tlb search indexed x 011111 11100 10110 / sthbrx store halfword byte-reverse indexed x 011111 11100 11010 0 extsh extend sign halfword x 011111 11100 11010 1 extsh. extend sign halfword and record cr x 011111 11101 10010 / tlbre tlb read entry x 011111 11101 11010 0 extsb extend sign byte x 011111 11101 11010 1 extsb. extend sign byte and record cr x 011111 11110 01011 0 divwuo divide word unsigned and record ov x 011111 11110 01011 1 divwuo. divide word unsigned and record ov and cr x 011111 11110 10010 / tlbwe tlb write entry x 011111 11110 10110 / icbi instruction cache block invalidate x 011111 11110 10111 / stfiwx store floating-point as int word indexed x 011111 11111 01011 0 divwo divide word and record ov x 011111 11111 01011 1 divwo. divide word and record ov and cr x 011111 11111 10110 / dcbz data cache block set to zero d 100000 ????? ????? ? lwz load word and zero d 100001 ????? ????? ? lwzu load word and zero with update d 100010 ????? ????? ? lbz load byte and zero d 100011 ????? ????? ? lbzu load byte and zero with update d 100100 ????? ????? ? stw store word d 100101 ????? ????? ? stwu store word with update d 100110 ????? ????? ? stb store byte table 111. instructions sorted by opcode (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
instruction model UM0434 140/391 d 100111 ????? ????? ? stbu store byte with update d 101000 ????? ????? ? lhz load halfword and zero d 101001 ????? ????? ? lhzu load halfword and zero with update d 101010 ????? ????? ? lha load halfword algebraic d 101011 ????? ????? ? lhau load halfword algebraic with update d 101100 ????? ????? ? sth store halfword d 101101 ????? ????? ? sthu store halfword with update d 101110 ????? ????? ? lmw load multiple word d 101111 ????? ????? ? stmw store multiple word d 110000 ????? ????? ? lfs load floating-point single d 110001 ????? ????? ? lfsu load floating-point single with update d 110010 ????? ????? ? lfd load floating-point double d 110011 ????? ????? ? lfdu load floating-point double with update d 110100 ????? ????? ? stfs store floating-point single d 110101 ????? ????? ? stfsu store floating-point single with update d 110110 ????? ????? ? stfd store floating-point double d 110111 ????? ????? ? stfdu store floating-point double with update a 111011 ????? 10010 0 fdivs floating divide single a 111011 ????? 10010 1 fdivs. floating divide single and record cr a 111011 ????? 10100 0 fsubs floating subtract single a 111011 ????? 10100 1 fsubs. floating subtract single and record cr a 111011 ????? 10101 0 fadds floating add single a 111011 ????? 10101 1 fadds. floating add single and record cr a 111011 ????? 10110 0 fsqrts floating square root single a 111011 ????? 10110 1 fsqrts. floating square root single and record cr a 111011 ????? 11000 0 fres floating reciprocal estimate single a 111011 ????? 11000 1 fres. floating reciprocal estimate single and record cr a 111011 ????? 11001 0 fmuls floating multiply single a 111011 ????? 11001 1 fmuls. floating multiply single and record cr a 111011 ????? 11100 0 fmsubs floating multiply-subtract single a 111011 ????? 11100 1 fmsubs. floating multiply-subtract single and record cr a 111011 ????? 11101 0 fmadds floating multiply-add single a 111011 ????? 11101 1 fmadds. floating multiply-add single and record cr table 111. instructions sorted by opcode (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
UM0434 instruction model 141/391 a 111011 ????? 11110 0 fnmsubs floating negative multiply-subtract single a 111011 ????? 11110 1 fnmsubs. floating negative multiply-subtract single and record cr a 111011 ????? 11111 0 fnmadds floating negative multiply-add single a 111011 ????? 11111 1 fnmadds. floating negative multiply-add single and record cr a 111111 ????? 10010 0 fdiv floating divide a 111111 ????? 10010 1 fdiv. floating divide and record cr a 111111 ????? 10100 0 fsub floating subtract a 111111 ????? 10100 1 fsub. floating subtract and record cr a 111111 ????? 10101 0 fadd floating add a 111111 ????? 10101 1 fadd. floating add and record cr a 111111 ????? 10110 0 fsqrt floating square root a 111111 ????? 10110 1 fsqrt. floating square root and record cr a 111111 ????? 10111 0 fsel floating select a 111111 ????? 10111 1 fsel. floating select and record cr a 111111 ????? 11001 0 fmul floating multiply a 111111 ????? 11001 1 fmul. floating multiply and record cr a 111111 ????? 11010 0 frsqrte floating reciprocal square root estimate a 111111 ????? 11010 1 frsqrte. floating reciprocal square root estimate and record cr a 111111 ????? 11100 0 fmsub floating multiply-subtract a 111111 ????? 11100 1 fmsub. floating multiply-subtract and record cr a 111111 ????? 11101 0 fmadd floating multiply-add a 111111 ????? 11101 1 fmadd. floating multiply-add and record cr a 111111 ????? 11110 0 fnmsub floating negative multiply-subtract a 111111 ????? 11110 1 fnmsub. floating negat ive multiply-subtract and record cr a 111111 ????? 11111 0 fnmadd floating negative multiply-add a 111111 ????? 11111 1 fnmadd. floating negative multiply-add and record cr x 111111 00000 00000 / fcmpu floating compare unordered x 111111 00000 01100 0 frsp floating round to single-precision x 111111 00000 01100 1 frsp. floating round to single-precision and record cr x 111111 00000 01110 0 fctiw floating convert to int word x 111111 00000 01110 1 fctiw. floating convert to int word and record cr x 111111 00000 01111 0 fctiwz floating convert to int word with round to zero table 111. instructions sorted by opcode (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 )
instruction model UM0434 142/391 table 112 lists all supported instructi ons, including vle instructions. x 111111 00000 01111 1 fctiwz. floating convert to int word with round to zero and record cr x 111111 00001 00000 / fcmpo floating compare ordered x 111111 00001 00110 0 mtfsb1 move to fpscr bit 1 x 111111 00001 00110 1 mtfsb1. move to fpscr bit 1 and record cr x 111111 00001 01000 0 fneg floating negate x 111111 00001 01000 1 fneg. floating negate and record cr x 111111 00010 00000 / mcrfs move to condition register from fpscr x 111111 00010 00110 0 mtfsb0 move to fpscr bit 0 x 111111 00010 00110 1 mtfsb0. move to fpscr bit 0 and record cr x 111111 00010 01000 0 fmr floating move register x 111111 00010 01000 1 fmr. floating move register and record cr x 111111 00100 00110 0 mtfsfi move to fpscr field immediate x 111111 00100 00110 1 mtfsfi. move to fpscr field immediate and record cr x 111111 00100 01000 0 fnabs floating negative absolute value x 111111 00100 01000 1 fnabs. floating negative absolute value and record cr x 111111 01000 01000 0 fabs floating absolute value x 111111 01000 01000 1 fabs. floating absolute value and record cr x 111111 10010 00111 0 mffs move from fpscr x 111111 10010 00111 1 mffs. move from fpscr and record cr xfl 111111 10110 00111 0 mtfsf move to fpscr fields xfl 111111 10110 00111 1 mtfsf. move to fpscr fields and record cr x 111111 11001 01110 / fctid floating convert to int doubleword x 111111 11001 01111 / fctidz floating convert to int doubleword with round to zero x 111111 11010 01110 / fcfid floating convert from int doubleword table 111. instructions sorted by opcode (continued) format opcode mnemonic instruction primary (inst 0:5 ) extended (inst 21:31 ) table 112. full instruction listing mnemonic instruction name source add add book e add. add & record cr book e addc add carrying book e addc. add carrying & record cr book e
UM0434 instruction model 143/391 addco add carrying & record ov book e addco. add carrying & record ov & cr book e adde add extended with ca book e adde. add extended with ca & record cr book e addeo add extended with ca & record ov book e addeo. add extended with ca & record ov & cr book e addi add immediate book e addic add immediate carrying book e addic. add immediate carrying & record cr book e addis add immediate shifted book e addme add to minus one extended with ca book e addme. add to minus one extended with ca & record cr book e addmeo add to minus one extended with ca & record ov book e addmeo. add to minus one extended with ca & record ov & cr book e addo add & record ov book e addo. add & record ov & cr book e addze add to zero extended with ca book e addze. add to zero extended with ca & record cr book e addzeo add to zero extended with ca & record ov book e addzeo. add to zero extended with ca & record ov & cr book e and and book e and. and & record cr book e andc and with complement book e andc. and with complement & record cr book e andi. and immediate and record cr book e andis. and immediate shifted and record cr book e b branch book e ba branch absolute book e bc branch conditional book e bca branch conditional absolute book e bcctr branch conditional to count register book e bcctrl branch conditional to count register and link book e bcl branch conditional and link book e bcla branch conditional and link absolute book e bclr branch conditional to link register book e bclrl branch conditional to link register and link book e bl branch and link book e table 112. full instruction listing (continued) mnemonic instruction name source
instruction model UM0434 144/391 bla branch and link absolute book e brinc bit reversed increment (1) spe cmp compare book e cmpi compare immediate book e cmpl compare logical book e cmpli compare logical immediate book e cntlzw count leading zeros word book e cntlzw. count leading zeros word and record cr book e crand condition register and book e crandc condition register and with complement book e creqv condition register equivalent book e crnand condition register nand book e crnor condition register nor book e cror condition register or book e crorc condition register or with complement book e crxor condition register xor book e dcba (2) data cache block allocate book e dcbf 2 data cache block flush book e dcbi 2 data cache block invalidate book e dcblc 2 data cache block lock clear cache locking dcbst 2 data cache block store book e dcbt 2 data cache block touch book e dcbtls 2 data cache block touch and lock set cache locking dcbtst 2 data cache block touch for store book e dcbtstls 2 data cache block touch for store and lock set cache locking dcbz 2 data cache block set to zero book e divw divide word book e divw. divide word and record cr book e divwo divide word and record ov book e divwo. divide word and record ov and cr book e divwu divide word unsigned book e divwu. divide word unsigned and record cr book e divwuo divide word unsigned and record ov book e divwuo. divide word unsigned and record ov and cr book e efsabs floating-point absolute value scalar spfp efsadd floating-point add scalar spfp efscfsf convert floating-point from signed fraction scalar spfp table 112. full instruction listing (continued) mnemonic instruction name source
UM0434 instruction model 145/391 efscfsi convert floating-point from signed integer scalar spfp efscfuf convert floating-point from unsigned fraction scalar spfp efscfui convert floating-point from unsigned integer scalar spfp efscmpeq floating-point compare equal scalar spfp efscmpgt floating-point compar e greater than scalar spfp efscmplt floating-point compare less than scalar spfp efsctsf convert floating-point to signed fraction scalar spfp efsctsi convert floating-point to signed integer scalar spfp efsctsiz convert floating-point to signed integer with round toward zero scalar spfp efsctuf convert floating-point to unsigned fraction scalar spfp efsctui convert floating-point to unsigned integer scalar spfp efsctuiz convert floating-point to unsigned integer with round toward zero scalar spfp efsdiv floating-point divide scalar spfp efsmul floating-point multiply scalar spfp efsnabs floating-point negative absolute value scalar spfp efsneg floating-point negate scalar spfp efssub floating-point subtract scalar spfp efststeq floating-point te st equal scalar spfp efststgt floating-point test greater than scalar spfp efststlt floating-point test less than scalar spfp eqv equivalent book e eqv. equivalent and record cr book e evabs vector absolute value spe evaddiw vector add immediate word spe evaddsmiaaw vector add signed, modulo, integer to accumulator word spe evaddssiaaw vector add signed, saturate, integer to accumulator word spe evaddumiaaw vector add unsigned, modulo, integer to accumulator word spe evaddusiaaw vector add unsigned, saturate, integer to accumulator word spe evaddw vector add word spe evand vector and spe evandc vector and with complement spe evcmpeq vector compare equal spe evcmpgts vector compare greater than signed spe evcmpgtu vector compare greater than unsigned spe evcmplts vector compare less than signed spe evcmpltu vector compare less than unsigned spe evcntlsw vector count leading sign bits word spe table 112. full instruction listing (continued) mnemonic instruction name source
instruction model UM0434 146/391 evcntlzw vector count leading zeros word spe evdivws vector divide word signed spe evdivwu vector divide word unsigned spe eveqv vector equivalent spe evextsb vector extend sign byte spe evextsh vector extend sign half word spe evfsabs vector floating-point absolute value spe evfsabs floating-point absolute value vector spfp evfsadd vector floating-point add spe evfsadd floating-point add vector spfp evfscfsf vector convert floatin g-point from signed fraction spe evfscfsf convert floating-point from signed fraction vector spfp evfscfsi vector convert floatin g-point from signed integer spe evfscfsi convert floating-point from signed integer vector spfp evfscfuf vector convert floating-point from unsigned fraction spe evfscfuf convert floating-point from unsigned fraction vector spfp evfscfui vector convert floatin g-point from unsigned integer spe evfscfui convert floating-point from unsigned integer vector spfp evfscmpeq vector floating-point compare equal spe evfscmpeq floating-point compare equal vector spfp evfscmpgt vector floating-point compare greater than spe evfscmpgt floating-point compar e greater than vector spfp evfscmplt vector floating-point compare less than spe evfscmplt floating-point compare less than vector spfp evfsctsf vector convert floating-point to signed fraction spe evfsctsf convert floating-point to signed fraction vector spfp evfsctsi vector convert floating-point to signed integer spe evfsctsi convert floating-point to signed integer vector spfp evfsctsiz vector convert floating-point to signed integer with round toward zero spe evfsctsiz convert floating-point to signed integer with round toward zero vector spfp evfsctuf vector convert floating-point to unsigned fraction spe evfsctuf convert floating-point to unsigned fraction vector spfp evfsctui vector convert floating-point to unsigned integer spe evfsctui convert floating-point to unsigned integer vector spfp evfsctuiz vector convert floating-point to unsigned integer with round toward zero spe evfsctuiz convert floating-point to unsigned integer with round toward zero vector spfp table 112. full instruction listing (continued) mnemonic instruction name source
UM0434 instruction model 147/391 evfsdiv vector floating-point divide spe evfsdiv floating-point divide vector spfp evfsmul vector floating-point multiply spe evfsmul floating-point multiply vector spfp evfsnabs vector floating-point negative absolute value spe evfsnabs floating-point negative absolute value vector spfp evfsneg vector floating-point negate spe evfsneg floating-point negate vector spfp evfssub vector floating-point subtract spe evfssub floating-point subtract vector spfp evfststeq vector floating-point test equal spe evfststeq floating-point test equal vector spfp evfststgt vector floating-point test greater than spe evfststgt floating-point test greater than vector spfp evfststlt vector floating-point test less than spe evfststlt floating-point test less than vector spfp evldd vector load double word into double word spe evlddx vector load double word into double word indexed spe evldh vector load double into half words spe evldhx vector load double into half words indexed spe evldw vector load double into two words spe evldwx vector load double into two words indexed spe evlhhesplat vector load half word into half words even and splat spe evlhhesplatx vector load half word into half words even and splat indexed spe evlhhossplat vector load half word into half word odd signed and splat spe evlhhossplatx vector load half word into half word odd signed and splat indexed spe evlhhousplat vector load half word into half word odd unsigned and splat spe evlhhousplatx vector load half word into half word odd unsigned and splat indexed spe evlwhe vector load word into two half words even spe evlwhex vector load word into two half words even indexed spe evlwhos vector load word into half wo rds odd signed (with sign extension) spe evlwhosx vector load word into half wo rds odd signed indexed (with sign extension) spe evlwhou vector load word into two half words odd unsigned (zero-extended) spe evlwhoux vector load word into two half words odd unsigned indexed (zero- extended) spe evlwhsplat vector load word into half words and splat spe table 112. full instruction listing (continued) mnemonic instruction name source
instruction model UM0434 148/391 evlwhsplatx vector load word into half words and splat indexed spe evlwwsplat vector load word into word and splat spe evlwwsplatx vector load word into word and splat indexed spe evmergehi vector merge high spe evmergehilo vector merge high/low spe evmergelo vector merge low spe evmergelohi vector merge low/high spe evmhegsmfaa multiply half words, even, guard ed, signed, modulo, fractional and accumulate spe evmhegsmfan multiply half words, even, guard ed, signed, modulo, fractional and accumulate negative spe evmhegsmiaa multiply half words, even, guarded, signed, modulo, integer and accumulate spe evmhegsmian multiply half words, even, guar ded, signed, modulo, integer and accumulate negative spe evmhegumiaa multiply half words, even, guard ed, unsigned, modulo, integer and accumulate spe evmhegumian multiply half words, even, guard ed, unsigned, modulo, integer and accumulate negative spe evmhesmf vector multiply half words, even, signed, modulo, fractional spe evmhesmfa vector multiply half words, even, signed, modulo, fractional, accumulate spe evmhesmfaaw vector multiply half words, even, signed, modulo, fractional and accumulate into words spe evmhesmfanw vector multiply half words, even, signed, modulo, fractional and accumulate negative into words spe evmhesmi vector multiply half words, even, signed, modulo, integer spe evmhesmia vector multiply half words, even, signed, modulo, integer, accumulate spe evmhesmiaaw vector multiply half words, even, signed, modulo, integer and accumulate into words spe evmhesmianw vector multiply half words, even, signed, modulo, integer and accumulate negative into words spe evmhessf vector multiply half words, even, signed, saturate, fractional spe evmhessfa vector multiply half words, even, signed, saturate, fractional, accumulate spe evmhessfaaw vector multiply half words, even, signed, saturate, fractional and accumulate into words spe evmhessfanw vector multiply half words, even, signed, saturate, fractional and accumulate negative into words spe evmhessiaaw vector multiply half words, ev en, signed, saturate, integer and accumulate into words spe table 112. full instruction listing (continued) mnemonic instruction name source
UM0434 instruction model 149/391 evmhessianw vector multiply half words, ev en, signed, saturate, integer and accumulate negative into words spe evmheumi vector multiply half words, even, unsigned, modulo, integer spe evmheumia vector multiply half words, even, unsigned, modulo, integer, accumulate spe evmheumiaaw vector multiply half words, even, unsigned, modulo, integer and accumulate into words spe evmheumianw vector multiply half words, even, unsigned, modulo, integer and accumulate negative into words spe evmheusiaaw vector multiply half words, even, unsigned, saturate, integer and accumulate into words spe evmheusianw vector multiply half words, even, unsigned, saturate, integer and accumulate negative into words spe evmhogsmfaa multiply half words, odd, guarded, signed, modulo, fractional and accumulate spe evmhogsmfan multiply half words, odd, guarded, signed, modulo, fractional and accumulate negative spe evmhogsmiaa multiply half words, odd, guarded, signed, modulo, integer and accumulate spe evmhogsmian multiply half words, odd, guarded, signed, modulo, integer and accumulate negative spe evmhogumiaa multiply half words, odd, guarded, unsigned, modulo, integer and accumulate spe evmhogumian multiply half words, odd, guarded, unsigned, modulo, integer and accumulate negative spe evmhosmf vector multiply half words, odd, signed, modulo, fractional spe evmhosmfa vector multiply half words, odd, signed, modulo, fractional, accumulate spe evmhosmfaaw vector multiply half words, odd, signed, modulo, fractional and accumulate into words spe evmhosmfanw vector multiply half words, odd, signed, modulo, fractional and accumulate negative into words spe evmhosmi vector multiply half words, odd, signed, modulo, integer spe evmhosmia vector multiply half words, odd, signed, modulo, integer, accumulate spe evmhosmiaaw vector multiply half words, odd, signed, modulo, integer and accumulate into words spe evmhosmianw vector multiply half words, odd, signed, modulo, integer and accumulate negative into words spe evmhossf vector multiply half words, odd, signed, saturate, fractional spe evmhossfa vector multiply half words, odd, signed, saturate, fractional, accumulate spe evmhossfaaw vector multiply half words, odd, signed, saturate, fractional and accumulate into words spe table 112. full instruction listing (continued) mnemonic instruction name source
instruction model UM0434 150/391 evmhossfanw vector multiply half words, odd, signed, saturate, fractional and accumulate negative into words spe evmhossiaaw vector multiply half words, o dd, signed, saturate, integer and accumulate into words spe evmhossianw vector multiply half words, o dd, signed, saturate, integer and accumulate negative into words spe evmhoumi vector multiply half words, odd, unsigned, modulo, integer spe evmhoumia vector multiply half words, odd, unsigned, modulo, integer, accumulate spe evmhoumiaaw vector multiply half words, o dd, unsigned, modulo, integer and accumulate into words spe evmhoumianw vector multiply half words, o dd, unsigned, modulo, integer and accumulate negative into words spe evmhousiaaw vector multiply half words, odd, unsigned, saturate, integer and accumulate into words spe evmhousianw vector multiply half words, odd, unsigned, saturate, integer and accumulate negative into words spe evmra initialize accumulator spe evmwhsmf vector multiply word high signed, modulo, fractional spe evmwhsmfa vector multiply word high signed, modulo, fractional and accumulate spe evmwhsmi vector multiply word high signed, modulo, integer spe evmwhsmia vector multiply word high signed, modulo, integer and accumulate spe evmwhssf vector multiply word high signed, saturate, fractional spe evmwhssfa vector multiply word high signed, saturate, fractional and accumulate spe evmwhumi vector multiply word high unsigned, modulo, integer spe evmwhumia vector multiply word high unsigned, modulo, integer and accumulate spe evmwlsmi vector multiply word low unsigned, modulo, integer spe evmwlsmiaaw vector multiply word low signed, modulo, integer and accumulate in words spe evmwlsmianw vector multiply word low signed, modulo, integer and accumulate negative in words spe evmwlssiaaw vector multiply word low signed, saturate, integer and accumulate in words spe evmwlssianw vector multiply word low signed, saturate, integer and accumulate negative in words spe evmwlumia vector multiply word low unsigned, modulo, integer and accumulate spe evmwlumiaaw vector multiply word low unsigned, modulo, integer and accumulate in words spe evmwlumianw vector multiply word low unsigned, modulo, integer and accumulate negative in words spe table 112. full instruction listing (continued) mnemonic instruction name source
UM0434 instruction model 151/391 evmwlusiaaw vector multiply word low unsigned, saturate, integer and accumulate in words spe evmwlusianw vector multiply word low unsigned, saturate, integer and accumulate negative in words spe evmwsmf vector multiply word signed, modulo, fractional spe evmwsmfa vector multiply word signed, modulo, fractional and accumulate spe evmwsmfaa vector multiply word signed, modulo, fractional and accumulate spe evmwsmfan vector multiply word signed, modulo, fractional and accumulate negative spe evmwsmi vector multiply word signed, modulo, integer spe evmwsmia vector multiply word signed, modulo, integer and accumulate spe evmwsmiaa vector multiply word signed, modulo, integer and accumulate spe evmwsmian vector multiply word signed, modulo, integer and accumulate negative spe evmwssf vector multiply word signed, saturate, fractional spe evmwssfa vector multiply word signed, saturate, fractional and accumulate spe evmwssfaa vector multiply word signed, saturate, fractional and accumulate spe evmwssfan vector multiply word signed, saturate, fractional and accumulate negative spe evmwumi vector multiply word unsigned, modulo, integer spe evmwumia vector multiply word unsigned, modulo, integer and accumulate spe evmwumiaa vector multiply word unsigned, modulo, integer and accumulate spe evmwumian vector multiply word unsigned, modulo, integer and accumulate negative spe evnand vector nand spe evneg vector negate spe evnor vector nor spe evor vector or spe evorc vector or with complement spe evrlw vector rotate left word spe evrlwi vector rotate left word immediate spe evrndw vector round word spe evsel vector select spe evslw vector shift left word spe evslwi vector shift left word immediate spe evsplatfi vector splat fractional immediate spe evsplati vector splat immediate spe evsrwis vector shift right word immediate signed spe evsrwiu vector shift right word immediate unsigned spe table 112. full instruction listing (continued) mnemonic instruction name source
instruction model UM0434 152/391 evsrws vector shift right word signed spe evsrwu vector shift right word unsigned spe evstdd vector store double of double spe evstddx vector store double of double indexed spe evstdh vector store double of four half words spe evstdhx vector store double of four half words indexed spe evstdw vector store double of two words spe evstdwx vector store double of two words indexed spe evstwhe vector store word of two half words from even spe evstwhex vector store word of two half words from even indexed spe evstwho vector store word of two half words from odd spe evstwhox vector store word of two half words from odd indexed spe evstwwe vector store word of word from even spe evstwwex vector store word of word from even indexed spe evstwwo vector store word of word from odd spe evstwwox vector store word of word from odd indexed spe evsubfsmiaaw vector subtract signed, modulo, integer to accumulator word spe evsubfssiaaw vector subtract signed, saturate, integer to accumulator word spe evsubfumiaaw vector subtract unsigned, modulo, integer to accumulator word spe evsubfusiaaw vector subtract unsigned, saturate, intege r to accumulator word spe evsubfw vector subtract from word spe evsubifw vector subtract immediate from word spe evxor vector xor spe extsb extend sign byte book e extsb. extend sign byte and record cr book e extsh extend sign half word book e extsh. extend sign half word and record cr book e e_add16i add immediate vle (16-bit opcodes) e_add2i. add (2 operand) immediate and record cr vle (16-bit opcodes) e_add2is add (2 operand) immediate shifted vle (16-bit opcodes) e_addi add immediate vle (16-bit opcodes) e_addi. add immediate and record vle (16-bit opcodes) e_addic add immediate carrying vle (16-bit opcodes) e_addic. add immediate carrying and record vle (16-bit opcodes) e_and2i. and (2 operand) immediate & record cr vle (16-bit opcodes) e_and2is. and (2 operand) immediate shifted & record cr vle (16-bit opcodes) e_andi and immediate vle (16-bit opcodes) table 112. full instruction listing (continued) mnemonic instruction name source
UM0434 instruction model 153/391 e_andi. and immediate and record vle (16-bit opcodes) e_b branch vle (16-bit opcodes) e_bc branch conditional vle (16-bit opcodes) e_bcl branch conditional & link vle (16-bit opcodes) e_bl branch & link vle (16-bit opcodes) e_cmp16i compare immediate vle (16-bit opcodes) e_cmph compare halfword vle (16-bit opcodes) e_cmph16i compare halfword immediate vle (16-bit opcodes) e_cmphl compare halfword logical vle (16-bit opcodes) e_cmphl16i compare halfword logical immediate vle (16-bit opcodes) e_cmpi compare immediate vle (16-bit opcodes) e_cmpl16i compare logical immediate vle (16-bit opcodes) e_cmpli compare logical immediate vle (16-bit opcodes) e_crand condition register and vle (16-bit opcodes) e_crandc condition register and with complement vle (16-bit opcodes) e_creqv condition register equivalent vle (16-bit opcodes) e_crnand condition register nand vle (16-bit opcodes) e_crnor condition register nor vle (16-bit opcodes) e_cror condition register or vle (16-bit opcodes) e_crorc condition register or with complement vle (16-bit opcodes) e_crxor condition register xor vle (16-bit opcodes) e_lbz load byte & zero vle (16-bit opcodes) e_lbzu load byte & zero with update vle (16-bit opcodes) e_lha load halfword algebraic vle (16-bit opcodes) e_lhau load halfword algebraic with update vle (16-bit opcodes) e_lhz load halfword & zero vle (16-bit opcodes) e_lhzu load halfword & zero with update vle (16-bit opcodes) e_li load immediate vle (16-bit opcodes) e_lis load immediate shifted vle (16-bit opcodes) e_lmw load multiple word vle (16-bit opcodes) e_lwz load word & zero vle (16-bit opcodes) e_lwzu load word & zero with update vle (16-bit opcodes) e_mcrf move condition register field vle (16-bit opcodes) e_mull2i multiply low word (2 operand) immediate vle (16-bit opcodes) e_mulli multiply low immediate vle (16-bit opcodes) e_or2i or (2 operand) immediate vle (16-bit opcodes) e_or2is or (2 operand) immediat e shifted vle (16-bit opcodes) table 112. full instruction listing (continued) mnemonic instruction name source
instruction model UM0434 154/391 e_ori or immediate vle (16-bit opcodes) e_ori. or immediate and record vle (16-bit opcodes) e_rlw rotate left word vle (16-bit opcodes) e_rlw. rotate left word & record cr vle (16-bit opcodes) e_rlwi rotate left word immediate vle (16-bit opcodes) e_rlwi. rotate left word immediate & record cr vle (16-bit opcodes) e_rlwimi rotate left word immed then mask insert vle (16-bit opcodes) e_rlwinm rotate left word immed then and with mask vle (16-bit opcodes) e_slwi shift left word immediate vle (16-bit opcodes) e_slwi. shift left word immediate & record cr vle (16-bit opcodes) e_srwi shift right word immediate vle (16-bit opcodes) e_srwi. shift right word immediate & record cr vle (16-bit opcodes) e_stb store byte vle (16-bit opcodes) e_stbu store byte with update vle (16-bit opcodes) e_sth store halfword vle (16-bit opcodes) e_sthu store halfword with update vle (16-bit opcodes) e_stmw store multiple word vle (16-bit opcodes) e_stw store word vle (16-bit opcodes) e_stwu store word with update vle (16-bit opcodes) e_subfic subtract from immediate carrying vle (16-bit opcodes) e_subfic. subtract from immediate and record vle (16-bit opcodes) e_xori xor immediate vle (16-bit opcodes) e_xori. xor immediate and record vle (16-bit opcodes) icbi 2 instruction cache bl ock invalidate book e icblc 2 instruction cache block lock clear cache locking icbt 2 instruction cache block touch book e icbtls 2 instruction cache block touch and lock set cache locking isel integer select eis isync instruction synchronize book e lbz load byte and zero book e lbzu load byte and zero with update book e lbzux load byte and zero with update indexed book e lbzx load byte and zero indexed book e lha load half word algebraic book e lhau load half word algebraic with update book e lhaux load half word algebraic with update indexed book e lhax load half word algebraic indexed book e table 112. full instruction listing (continued) mnemonic instruction name source
UM0434 instruction model 155/391 lhbrx load half word byte-reverse indexed book e lhz load half word and zero book e lhzu load half word and zero with update book e lhzux load half word and zero with update indexed book e lhzx load half word and zero indexed book e lmw load multiple word book e lwarx load word and reserve indexed book e lwbrx load word byte-reverse indexed book e lwz load word and zero book e lwzu load word and zero with update book e lwzux load word and zero with update indexed book e lwzx load word and zero indexed book e mbar (3) memory barrier book e mcrf move condition register field book e mcrxr move to condition register from xer book e mfcr move from condition register book e mfdcr (4) move from device control register book e mfdcrx 4 move from device control register indexed book e mfmsr move from machine state register book e mfspr move from special purpose register book e msync 3 memory synchronize book e mtcrf move to condition register fields book e mtdcr 4 move to device control register book e mtdcrx 4 move to device control register indexed book e mtmsr move to machine state register book e mtspr move to special purpose register book e mulhw multiply high word book e mulhw. multiply high word and record cr book e mulhwu multiply high word unsigned book e mulhwu. multiply high word unsigned and record cr book e mulli multiply low immediate book e mullw multiply low word book e mullw. multiply low word and record cr book e mullwo multiply low word and record ov book e mullwo. multiply low word and record ov and cr book e nand nand book e nand. nand and record cr book e table 112. full instruction listing (continued) mnemonic instruction name source
instruction model UM0434 156/391 neg negate book e neg. negate and record cr book e nego negate and record ov book e nego. negate and record ov and record cr book e nor nor book e nor. nor and record cr book e or or book e or. or and record cr book e orc or with complement book e orc. or with complement and record cr book e ori or immediate book e oris or immediate shifted book e rfci return from critical interrupt book e rfdi return from debug interrupt debug rfi return from interrupt book e rlwimi rotate left word immed then mask insert book e rlwimi. rotate left word immed then mask insert and record cr book e rlwinm rotate left word imm ed then and with mask book e rlwinm. rotate left word immed then and with mask and record cr book e rlwnm rotate left word then and with mask book e rlwnm. rotate left word then and with mask and record cr book e sc system call book e se_add add vle (32-bit opcodes) se_addi add immediate vle (32-bit opcodes) se_and and vle (32-bit opcodes) se_and. and and record vle (32-bit opcodes) se_andc and with complement vle (32-bit opcodes) se_andi and immediate vle (32-bit opcodes) se_b branch vle (32-bit opcodes) se_bc branch conditional vle (32-bit opcodes) se_bclri bit clear immediate vle (32-bit opcodes) se_bctr branch to count register vle (32-bit opcodes) se_bctrl branch to count register & link vle (32-bit opcodes) se_bgeni bit generate immediate vle (32-bit opcodes) se_bl branch and link vle (32-bit opcodes) se_blr branch to link register vle (32-bit opcodes) se_blrl branch to link register & link vle (32-bit opcodes) table 112. full instruction listing (continued) mnemonic instruction name source
UM0434 instruction model 157/391 se_bmaski bit mask generate immediate vle (32-bit opcodes) se_bseti bit set immediate vle (32-bit opcodes) se_btsti bit test immediate vle (32-bit opcodes) se_cmp compare vle (32-bit opcodes) se_cmph compare halfword vle (32-bit opcodes) se_cmphl compare halfword logical vle (32-bit opcodes) se_cmpi compare immediate vle (32-bit opcodes) se_cmpl compare logical vle (32-bit opcodes) se_cmpli compare logical immediate vle (32-bit opcodes) se_extsb extend sign byte vle (32-bit opcodes) se_extsh extend sign halfword vle (32-bit opcodes) se_extzb extend with zeros byte vle (32-bit opcodes) se_extzh extend with zeros halfword vle (32-bit opcodes) se_illegal illegal vle (32-bit opcodes) se_isync instruction synchronize vle (32-bit opcodes) se_lbz load byte and zero vle (32-bit opcodes) se_lhz load halfword and zero vle (32-bit opcodes) se_li load immediate vle (32-bit opcodes) se_lwz load word and zero vle (32-bit opcodes) se_mfar move from alternate register vle (32-bit opcodes) se_mfctr move from count register vle (32-bit opcodes) se_mflr move from link register vle (32-bit opcodes) se_mr move register vle (32-bit opcodes) se_mtar move to alternate register vle (32-bit opcodes) se_mtctr move to count register vle (32-bit opcodes) se_mtlr move to link register vle (32-bit opcodes) se_mullw multiply low word vle (32-bit opcodes) se_neg negate vle (32-bit opcodes) se_not not vle (32-bit opcodes) se_or or vle (32-bit opcodes) se_rfci return from critical interrupt vle (32-bit opcodes) se_rfdi return from debug interrupt vle (32-bit opcodes) se_rfi return from interrupt vle (32-bit opcodes) se_sc system call vle (32-bit opcodes) se_slw shift left word vle (32-bit opcodes) se_slwi shift left word immediate vle (32-bit opcodes) se_sraw shift right algebraic word vle (32-bit opcodes) table 112. full instruction listing (continued) mnemonic instruction name source
instruction model UM0434 158/391 se_srawi shift right algebraic word immediate vle (32-bit opcodes) se_srw shift right word vle (32-bit opcodes) se_srwi shift right word immediate vle (32-bit opcodes) se_stb store byte vle (32-bit opcodes) se_sth store halfword vle (32-bit opcodes) se_stw store word vle (32-bit opcodes) se_sub subtract vle (32-bit opcodes) se_subf subtract from vle (32-bit opcodes) se_subi subtract immediate vle (32-bit opcodes) se_subi. subtract immediate and record vle (32-bit opcodes) slw shift left word book e slw. shift left word and record cr book e sraw shift right algebraic word book e sraw. shift right algebraic word and record cr book e srawi shift right algebraic word immediate book e srawi. shift right algebraic word immediate and record cr book e srw shift right word book e srw. shift right word and record cr book e stb store byte book e stbu store byte with update book e stbux store byte with update indexed book e stbx store byte indexed book e sth store half word book e sthbrx store half word byte-reverse indexed book e sthu store half word with update book e sthux store half word with update indexed book e sthx store half word indexed book e stmw store multiple word book e stw store word book e stwbrx store word byte-reverse indexed book e stwcx. store word conditional indexed and record cr book e stwu store word with update book e stwux store word with update indexed book e stwx store word indexed book e subf subtract from book e subf. subtract from and record cr book e subfc subtract from carrying book e table 112. full instruction listing (continued) mnemonic instruction name source
UM0434 instruction model 159/391 subfc. subtract from carrying and record cr book e subfco subtract from carrying and record ov book e subfco. subtract from carrying and record ov and cr book e subfe subtract from extended with ca book e subfe. subtract from extended with ca and record cr book e subfeo subtract from extended with ca and record ov book e subfeo. subtract from extended with ca and record ov and cr book e subfic subtract from immediate carrying book e subfme subtract from minus one extended with ca book e subfme. subtract from minus one extended with ca and record cr book e subfmeo subtract from minus one exte nded with ca and record ov book e subfmeo. subtract from minus one extended with ca and record ov & cr book e subfo subtract from and record ov book e subfo. subtract from and record ov and cr book e subfze subtract from zero extended with ca book e subfze. subtract from zero extended with ca and record cr book e subfzeo subtract from zero extended with ca and record ov book e subfzeo. subtract from zero extended with ca and record ov and cr book e tlbivax tlb invalidate virtual address indexed book e tlbre tlb read entry book e tlbsx tlb search indexed book e tlbsync tlb synchronize book e tlbwe tlb write entry book e tw trap word book e twi trap word immediate book e wrtee write external enable book e wrteei write external enable immediate book e xor xor book e xor. xor and record cr book e xori xor immediate book e xoris xor immediate shifted book e 1. an implementation can restrict the no. of bits shown in a mask. devices using 16-bit instru ctions are limited to 16 bits, which allows the user to perform bit-revers ed address computations for 65536 byte samples. 2. not supported by e200z3 unless th e integrated device includes a cache; treated as no-ops, with the exception of dcbz, which results in an alignment interrupt, and dc bi, which is treated as a privileged no-op. 3. see chapter 5.7: memory synchronization and reservation instructions 4. the core cpu will take an illegal instru ction exception for unsupported dcr values. table 112. full instruction listing (continued) mnemonic instruction name source
interrupts and exceptions UM0434 160/391 6 interrupts and exceptions this chapter provides a general description of the powerpc book e interrupt and exception model and gives details of the additions and changes to that model that are implemented in the e200z3 core. this chapter identifies features defined by book e, the freescale book e implementation standards (eis), and the e200z3 implementation. 6.1 overview book e defines the mechanisms by which th e e200z3 core implements interrupts and exceptions. note the following definitions: interrupt action in which the processor saves its old context and begins execution at a predetermined interrupt handler address exceptions events that, if enabled, cause the processor to take an interrupt the powerpc exception mechanism allows the processor to change to supervisor state for the following reasons: as a result of unusual conditions (exceptions) arising in the execution of instructions as a response to the assertion of external signals, bus errors, or various internal conditions when an interrupt occurs, information about the processor state held in the msr and the address at which execution should resume after the interrupt is handled are saved to a pair of save/restore registers (srr0/srr1 for non-cr itical interrupts, csrr0/csrr1 for critical interrupts, or dsrr0/dsrr1 for debug interrupts when the debug apu is enabled), and the processor begins executing at an address (interrupt vector) determined by the interrupt vector prefix register (ivpr) and an interrupt-specific interrupt vector offset register (ivor n ). processing of instructions within the interrupt handler begins in supervisor mode. multiple exception conditions can map to a single interrupt vector and may be distinguished by examining registers associated with the interrupt. the exception syndrome register (esr) is updated with information specific to the exception type when an interrupt occurs. to prevent loss of state information, interrupt handlers must save the information stored in the save/restore registers soon after the interrupt is taken. hardware supports nesting of critical interrupts within non-critical interrupts, and debug interrupts within both critical and non-critical interrupts. the interrupt handler must save necessary state information if interrupts of a given class are re-enabled within the handler. the following terms are used to describe the stages of exception processing: recognition exception recognition occurs when the condition that can cause an exception is identified by the processor. recognition is also referred to as an ?exception event.? taken an interrupt is said to be taken when control of instruction execution is passed to the interrupt handler; that is, the context is saved, the instruction at the appropriate vector offset is fetched, and the interrupt handler routine begins. handling interrupt handling is performed by the software linked to the appropriate vector offset. interrupt handling is begun in supervisor mode.
UM0434 interrupts and exceptions 161/391 returning from an interrupt is performed by executing the appropriate return from interrupt instruction ( rfi , rfci , or rfdi ), which restores state information from their respective save/restore registers and returns instruction fetching to the interrupted flow. 6.2 e200z3 interrupts the book e architecture specifies that interr upts can be precise or imprecise, synchronous or asynchronous, and critical or non-critical. these characteristics are described as follows: asynchronous exceptions are caused by events external to the processor?s instruction execution. synchronous exceptions are directly caused by instructions or by an event somehow synchronous to the program flow, such as a context switch. a precise interrupt architecturally guarantees that no instruction beyond the instruction causing the exception has (visibly) executed. an imprecise interrupt does not have this guarantee. book e defines critical and non-critical interrupt types, and the e200z3 defines an implementation-specific debug apu that includes the debug interrupt type. each interrupt type provides separate resources (save/restore registers and return from interrupt instructions) that allow interrupts of one type to not interfere with the state handling of an interrupt of another type. table 113 describes how these apply to the interrupts implemented by the e200z3 core. the classifications in table 113 are discussed in greater detail in chapter 6.6: interrupt definitions on page 168 .? interrupts implemented in the e200z3 and the exception conditions that cause them, are listed in table 114 . note that although this table lists system reset, book e does not define system reset as an interr upt and assigns no inte rrupt vector to it. table 113. interrupt classifications interrupt types synchronous / asynchronous precise / imprecise critical / non-critical / debug system reset asynchronous, non-maskable imprecise ? machine check ? ? critical critical input watchdog timer asynchronous, maskable imprecise critical external input fixed-interval timer decrementer asynchronous, maskable imprecise non-critical instruction based debug synchronous precise critical/debug debug (ude) debug imprecise asynchronous imprecise critical/debug data storage / alignment / tlb instruction storage / tlb synchronous precise non-critical
interrupts and exceptions UM0434 162/391 table 114. exceptions and conditions interrupt type ivor n cause section/page system reset (not an interrupt) none (1) reset by assertion of p_reset_b watchdog timer reset control debug reset control ? critical input 0 (2) p_critint_b is asserted and msr[ce]=1 chapter 6.6.1 machine check 1 p_mcp_b is asserted and msr[me] =1 isi, itlb error on first instruction fetch for an exception handler and current msr[me] = 1 write bus error on buffered store or cache line push and current msr[me]=1 bus error (xte) with msr[ee] =0 and current msr[me]=1 chapter 6.6.2 data storage 2 access control byte ordering due to misaligned access across page boundary to pages with mismatched e bits precise external termination error ( p_d_tea_b assertion and precise recognition) and msr[ee]=1 chapter 6.6.3 instruction storage 3 access control precise external termination error ( p_i_tea_b assertion and precise recognition) and msr[ee]=1 byte ordering due to misaligned instruction across page boundary to pages with mismatched vle bits, or access to page with vle set, and e indicating little-endian. misaligned instruction fetch due to a change of flow to an odd halfword instruction boundary on a book e (non-vle) instruction page, due to value in lr, ctr, or xsrr0 chapter 6.6.4 external input 4 2. p_extint_b is asserted and msr[ee]=1 chapter 6.6.5 alignment 5 lmw , stmw not word aligned lwarx or stwcx. not word aligned dcbz with disabled cache, or no cache present, or to w or i storage chapter 6.6.6 program 6 illegal, privileged, trap, floating-point enabled, apu enabled, unimplemented operation chapter 6.6.7 floating-point unavailable 7 msr[fp] = 0 and attempt to execute a book e floating-point operation chapter 6.6.8 system call 8 execution of the system call ( sc ) instruction chapter 6.6.9 apu unavailable 9 unused by the e200z3 chapter 6.6.10 decrementer 10 as specified in book e chapter 6.6.11 fixed-interval timer 11 as specified in book e chapter 6.6.12 watchdog timer 12 as specified in book e chapter 6.6.13 data tlb error 13 data translation lookup did not match a valid tlb entry. chapter 6.6.14 instruction tlb error 14 instruction translation lookup did not match a valid tlb entry. chapter 6.6.15
UM0434 interrupts and exceptions 163/391 6.3 exception syndro me register (esr) esr, shown in table 115 , provides a syndrome to distinguish exceptions that can generate the same interrupt type. the e200z3 adds some im plementation-specific bits to this register. the esr fields are described in table 116 . debug 15 trap, instruction address compare, data address compare, instruction complete, branch taken, return from interrupt, interrupt taken, debug counter, external debug event, unconditional debug event chapter 6.6.16 reserved 6?31 ? ? spe unavailable 32 see chapter 6.6.18: spe apu unavailable interrupt (ivor32) .? chapter 6.6.18 spe data 33 see chapter 6.6.19: spe floating- point data interrupt (ivor33) .? chapter 6.6.19 spe round 34 see chapter 6.6.20: spe floating-po int round interrupt (ivor34) .? chapter 6.6.20 1. vector to [p_rstbase[0:19]] || 0xffc. 2. autovectored external & critical input in terrupts, use this ivor. vectored interrupt s supply an interrupt vector offset direc tly. table 114. exceptions and conditions (continued) interrupt type ivor n cause section/page table 115. exception syndrome register (esr) 32 35 36 37 38 39 40 41 42 43 44 45 46 47 48 55 56 57 58 59 61 62 63 field ? pil ppr ptr fp st ? dlk ilk ap puo bo pie ? spe ? vlemi ? mif xte reset all zeros r/w r/w spr spr 62 table 116. esr field descriptions bit(s) name description asso ciated interrupt type 32?35 ? reserved, should be cleared. ? 36 pil illegal instruction exception program 37 ppr privileged instruction exception program 38 ptr trap exception program 39 fp floating-point operation alignment, data storage, data tlb, program 40 st store operation alignment, data storage, data tlb 41 ? reserved, should be cleared. ? 42 dlk data cache locking (1) data storage 43 ilk instruction cache locking data storage` 44 ap auxiliary processor operation. (unused in the e200z3) alignment, data storage, data tlb, program 45 puo unimplemented operation exception program
interrupts and exceptions UM0434 164/391 6.4 machine state register (msr) the msr, shown in figure 117 , defines the state of the processor. the msr bits are described in table 118 . 46 bo byte ordering exception data storage 47 pie program imprecise exception?unused in the e200z3 (reserved, should be cleared.) ? 48?55 ? reserved, should be cleared. ? 56 spe spe apu operation spe unavailable, spe fl oating-point data exception, spe floating-poi nt round exception, alignment, data storage, data tlb 57 ? reserved, should be cleared. ? 58 vlemi vle mode instruction spe unavailable, spe fl oating-point data exception, spe floating-poi nt round exception, data storage, data tlb, instruction storage, alignment, program, and system call 59?61 ? reserved, should be cleared. ? 62 mif misaligned instruction fetch instruction storage, instruction tlb 63 xte external termination error (precise) data storage, instruction storage 1. when optional cache is present. unused on e200z3. table 116. esr field descriptions (continued) bit(s) name description asso ciated interrupt type table 117. processor state definition of msr 32 3637 38 39 4445 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 field ? ucle spe ? we ce ? ee pr fp me fe0 uble de fe1 ? is ds ? reset all zeros r/w r/w table 118. msr field descriptions bits name description 32?36 ? reserved, should be cleared. 37 ucle user cache lock enable. (implemented, but ignored by e200z3) 0 execution of the cache locking instructions in user mode (msr[pr] = 1) disabled; data storage interrupt taken instead, and ilk or dlk is set in the esr. 1 execution of the cache lock in structions in user mode enabled 38 spe spe available 0 execution of spe apu vector instructions is disabled; spe unavailable exception taken instead, and esr[spe] is set. 1 execution of spe apu vector instructions is enabled. 39?44 ? reserved, should be cleared.
UM0434 interrupts and exceptions 165/391 45 we wait state (power management) enable. defined as optional by book e and implemented in the e200z3. 0 power management is disabled. 1 power management is enabled. the processor can enter a power-saving mode when additional conditions are present. the mode chosen is determ ined by hid0[doze,na p,sleep], described in section 4.13.1, ?hardware impl ementation dependent register 0 (hid0).? 46 ce critical interrupt enable 0 critical input and watchdog timer interrupts are disabled. 1 critical input and watchdog timer interrupts are enabled. 47 ? preserved 48 ee external interrupt enable 0 external input, decrementer, and fix ed-interval timer interrupts are disabled. 1 external input, decrementer, and fixed-interval timer interrupts are enabled. 49 pr problem state 0 the processor is in supervisor mode, can execute any instruction, and can access any resource (for example, gprs, sprs, msr, etc.). 1 the processor is in user mode, cannot execute any privileged instruction, and cannot access any privileged resource. 50 fp floating-point available 0 floating-point unit is unavailable. the proc essor cannot execute float ing-point instructions, including floating-point loads, stores, and moves. (an fp unavailable interrupt is generated on attempted execution of floating-point instructions). 1 floating-point unit is available. the processor can execute floating-point instructions. (note that for the e200z3, the floating-point unit is not su pported; an unimplemented operation exception is generated for attempted execution of floating -point instructions when fp is set). 51 me machine check enable 0 machine check interrupts are disabled. checkstop mode is entered when p_mcp_b is recognized asserted or an isi or itlb exception occurs on a fetch of the first instruction of an exception handler. 1 machine check interrupts are enabled. 52 fe0 floating-point exception mode 0 (not used by the e200z3) 53 ? reserved, should be cleared. 54 de debug interrupt enable 0 debug interrupts are disabled. 1 debug interrupts are enabled if dbcr0[idm] is set. 55 fe1 floating-point exception mode 1 (not used by the e200z3) 56 ? reserved, should be cleared. 57 ? preserved, should be cleared. 58 is instruction address space 0 the processor directs all instruction fetches to address space 0 (ts=0 in the relevant tlb entry). 1 the processor directs all instruction fetches to address space 1 (ts=1 in the relevant tlb entry). table 118. msr field descriptions bits name description
interrupts and exceptions UM0434 166/391 6.4.1 machine check syndrome register (mcsr) when the core complex takes a machine check interrupt, it updates mcsr, shown in table 119 , to identify machine chec k conditions. the mcsr also indicates whether the source of a machine check condition is recoverable. when an mcsr bit is set, the core complex asserts p_mcp_out for system information. table 120 describes mcsr fields. interrupt vector prefix register (ivpr) the ivpr, shown in table 121 , is used during interrupt processing for determining the starting address for the software interrupt handler. the value contained in the vector offset field of the ivor selected for a particular interrupt type is concatenated with the value in the ivpr to form an instruction address from which execution is to begin. 59 ds data address space 0 the core directs all data storage accesses to address space 0 (ts=0 in the relevant tlb entry). 1 the core directs all data storage accesses to address space 1 (ts=1 in the relevant tlb entry). 60?61 ? reserved, should be cleared. 62?63 ? reserved, should be cleared. table 118. msr field descriptions bits name description table 119. machine check syndrome register (mcsr) 32 33 34 35 36 37 58 59 60 61 62 63 field mcp ? cp_perrcperr excp_err ? bus_irerrbus_drerr bus_wrerr ? reset all zeros r/w r/w table 120. mcsr field descriptions bits name description recoverable 32 mcp machine check input pin maybe 33 ? reserved, should be cleared. ? 34 cp_perr cache push parity error (1) unlikely 35 cperr cache parity error 1 precise 36 excp_err isi, itlb, or bus error on first instruction fetch for an interrupt handler precise 37?58 ? reserved, should be cleared. ? 59 bus_irerr read bus error on instruction fetch unlikely 60 bus_drerr read bus error on data load unlikely 61 bus_wrerr write bus error on buffered store or cache line push unlikely 62?63 ? reserved, should be cleared. ? 1. this bit is implemented but must never be set by hardware.
UM0434 interrupts and exceptions 167/391 ivpr fields are defined in table 122 . 6.5 interrupt vector offset registers (ivorn) ivors are used during interrupt processing for determining the starting address of a software interrupt handler. the value in the vector offset field of the ivor assigned to the interrupt type is concatenated with the value in ivpr to form an instruction address at which execution is to begin. the e200z3 also defines the low-order bits of the ivors (defined as zeros in book e) as a context selector field to be used as the current context number once interrupt handling begins when multiple hardware contexts are supported (ctxcr[numctx]
interrupts and exceptions UM0434 168/391 ivor spr assignments are shown in table 124 . 6.6 interrupt definitions the following sections describe interrupts as they are implemented on the e200z3. 60 ? reserved, should be cleared. 61?63 cs context selector. when multiple har dware contexts are supported, th is selects an operating context for the interrupt handler. this value is loaded into the curctx field of the context control register as part of the interrupt vectoring process. th is field is not defined by powerpc book e. when multiple hardware contexts are not supported, this field is not implemented and is read as zero. table 123. ivor register fields (continued) bits name description table 124. ivor assignments ivor number spr interrupt type ivor0 400 critical input ivor1 401 machine check ivor2 402 data storage ivor3 403 instruction storage ivor4 404 external input ivor5 405 alignment ivor6 406 program ivor7 407 floating-point unavailable ivor8 408 system call ivor9 409 auxiliary processor unavailable. not used by the e200z3. ivor10 410 decrementer ivor11 411 fixed-interval timer interrupt ivor12 412 watchdog timer interrupt ivor13 413 data tlb error ivor14 414 instruction tlb error ivor15 415 debug ivor16?ivor31 ? reserved for future architectural use -specific ivors (defined by the eis) ivor32 528 spe apu unavailable ivor33 529 spe floating-point data exception ivor34 530 spe floating-point round exception
UM0434 interrupts and exceptions 169/391 6.6.1 critical input interrupt (ivor0) a critical input exception is signaled to the processor by the assertion of the critical interrupt pin ( p_critint_b ). when the e200z3 detects the exception, if critical interrupts are enabled (msr[ce] = 1), the e200z3 takes the critical input interrupt. the p_critint_b input is a level- sensitive signal expected to remain asserted until the e200z3 acknowledges the interrupt. if p_critint_b is negated early, recognition of the interrupt request is not guaranteed. after the e200z3 begins execution of the critical interrupt handler, the system can safely negate p_critint_b . a critical input interrupt may be delayed by other higher priority exceptions or if msr[ce] is cleared when the exception occurs. table 125 lists register settings when a critical input interrupt is taken. when the debug apu is enabled, msr[de] is not automatically cleared by a critical input interrupt but can be configured to be cleared through hid0 (hid0[ciclrde]). refer to chapter 4.13.1: hardware implementation dependent register 0 (hid0) on page 84 .? ivor0 is the vector offset register used by autovectored critical input interrupts to determine the interrupt handler location. the e200z3 also provides the c apability to directly vector critical input interrupts to multiple handlers by allowing a critical input interrupt request to be accompanied by a vector offset. the p_voffset[0:11] inputs are used in place of the value in ivor0 to form the interrupt vector when a critical input interrupt request is not autovectored ( p_avec_b negated when p_critint_b asserted). 6.6.2 machine check interrupt (ivor1) the e200z3 implements the machine check exception as defined in book e except for automatic clearing of msr[de]. the e200z3 initiates a machine check interrupt if msr[me]=1 and any of the machine check sources listed in table 114 is detected. as defined in book e, the interrupt is not taken if msr[me] is cleared, in which case the table 125. critical input interrupt register settings registe r setting description csrr0 set to the effective address of the instruction that the proc essor would have attempted to execute next if no exception conditions were present. csrr1 set to the contents of the ms r at the time of the interrupt. msr ucle 0 spe 0 we 0 ce 0 ee 0 pr 0 fp 0 me ? fe0 0 de ?/0 (1) fe1 0 is 0 ds 0 1. de is cleared when the debug apu is disabled. clearing of de is optionally supported by control in hid0 when the debug apu is enabled. esr unchanged mcsr unchanged dear unchanged vector ivpr[32?47] || ivor0[48?59] || 0b0000 (autovectored) ivpr[32?47] || p_voffset[0:11] || 0b0000 (non-autovectored)
interrupts and exceptions UM0434 170/391 processor generates an internal checkstop condition and enters checkstop state. when a processor is in checkstop state, instruction processing is suspended and generally cannot continue without restarting the processor. note that other conditions may lead to the checkstop condition; the disabled machine check exception is only one of these. the e200z3 implements mcsr to record the sources of machine checks. see chapter 6.4.1: machine check syndrome register (mcsr) on page 166 ,? for more information. msr[de] is not automatically cleared by a machine check exception but can be configured to be cleared or left unchanged through hid0[mcclrde]. see chapter 4.13.1: hardware implementation dependent register 0 (hid0) on page 84 .? machine check interrupt enabled (msr[me]=1) machine check interrupts are enabled when msr[me]=1. when a machine check interrupt is taken, registers are updated as shown in table 126 . the machine check input, p_mcp_b , can be masked by hid0[emcp]. most machine check exceptions are unrecoverable in the sense that execution cannot resume in the context that existed before th e interrupt. however, system software can use the machine check interrupt handler to try to identify and recover from the machine check condition. in particular, the mcsr is provided to identify the sources of a machine check and may be used to identify recoverable events. the interrupt handler should set msr[me] as early as possible to avoid entering checkstop state if another machine check condition occurs. table 126. machine check interrupt register settings register setting description csrr0 on a best-effort basis, the e200z3 sets this to the address of some instruction that was executing or about to be executing when the machine check condition occurred. csrr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce 0 ee 0 pr 0 fp 0 me 0 de 0 (1) fe1 0 is 0 ds 0 1. cleared when the debug apu is disabled. clearing of de is optionally supported by control in hid0 when the debug apu is enabled. esr unchanged mcsr updated to reflect the sources of a machine check dear unchanged unless machine check is due to a data access causing a cache parity error to be signaled; updated with data access effective address in that case vector ivpr[32?47] || ivor1[48?59] || 0b0000
UM0434 interrupts and exceptions 171/391 checkstop state the following exception conditions can cause a checkstop if msr[me]=0: a machine check occurs. first instruction in an interrupt handler cannot be executed due to a translation miss (itlb), a page marked no execute (isi), or a bus error termination. bus error termination for a buffered store . precise external termination error occurs and msr[ee]=0. non-exception?related checkstop conditions are as follows: tcr[wrc] - watchdog reset control bits set to checkstop on second watchdog timer overflow event when a processor is in checkstop state, instruction processing is suspended and generally cannot resume without the processor being reset. to indicate that a checkstop condition exists, the p_chkstop output is asserted whenever the cpu is in checkstop state. when a debug request is presented to the e200z3 core while it is in checkstop state, p_wakeup is asserted, and when m_clk is provided to the core, it temporarily exits checkstop state and enters debug mode. the p_chkstop output is negated while the core remains in a debug session ( p_debug_b asserted). when the debug session is exited, the core re-enters checkstop state. note that the external system logic may be in an undefined state following a checkstop condition, such as having an outstanding bus transaction or other inconsistency; thus, no guarantee can be made in general about activities performed in debug mode while a checkstop is outstanding. debug logic can generate assertion of p_resetout_b through dbcr0. 6.6.3 data storage interrupt (ivor2) a data storage interrupt may occur if no higher priority exception exists and one of the following exists: read or write access control exception condition byte-ordering exception condition external termination error (precise) and msr[ee]=1 access control is defined as in book e. a by te-ordering exception condition occurs for any misaligned access across a page boundary to pages with mismatched e bits. precise external termination errors occur when a load or guarded store is terminated by assertion of a p_d_tea_b =error termination response. table 127 lists register settings when a dsi is taken. table 127. data storage interrupt register settings register setting description srr0 set to the effective address of the excepting load/ store instruction srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0
interrupts and exceptions UM0434 172/391 6.6.4 instruction stor age interrupt (ivor3) an instruction storage interrupt (isi) occurs when no higher priority exception exists and an execute access control exception occurs. this interrupt is implemented as defined by book e, except for the following: the byte-ordering condition does not occur in the e200z3 the addition of precise external termination errors that occur when an instruction fetch is terminated by assertion of a p_i_tea_b =error termination response and msr[ee]=1 misaligned instruction fetch exceptions the extension of the byte ordering exception cases. exception extensions implemented in e200z3 for vle involve extending the definition of the instruction storage interrup t to include the following: byte-ordering exceptions for instruction accesses misaligned instruction fetch exceptions corresponding updates to the esr as shown in table 128 and table 129 . table 129 lists register settings when an isi is taken. esr access: byte ordering: external termination error (precise): [st], [vlemi ]. all other bits cleared. [st], [vlemi ], bo. all other bits cleared. [st], [vlemi ], xte. all other bits cleared. mcsr unchanged dear for access and byte-ordering exceptions, set to the effective address of a byte within the page whose access caused the violation. vector ivpr[32?47] || ivor2[48?59] || 0b0000 table 127. data storage interrupt register settings (continued) register setting description table 128. isi exceptions and conditions interrupt type ivor causing conditions instruction storage ivor 3 ? access control. ? precise external termination error ( p_tea_b assertion and precise recognition) and msr[ee]=1. ? byte ordering due to misaligned instruction across page boundary to pages with mismatched vle bits, or access to page with vle set, and e indicating little-endian. ? misaligned instruction fetch due to a change of flow to an odd halfword instruction boundary on a book e (non-vle) instruction page, due to value in lr, ctr, or xsrr0 table 129. instruction storage interrupt register settings register setting description srr0 set to the effective address of the excepting instruction. srr1 set to the contents of the msr at the time of the interrupt
UM0434 interrupts and exceptions 173/391 6.6.5 external input interrupt (ivor4) an external input exception is signaled to the processor by the assertion of the external interrupt input ( p_extint_b ), a level-sensitive signal expected to remain asserted until the e200z3 acknowledges the external interrupt. if p_extint_b is negated early, recognition of the interrupt request is not guaranteed. when the e200z3 detects the exception, if the exception is enabled by msr[ee], the e200z3 takes an external input interrupt. an external input interrupt may be delayed by other higher priority exceptions or if msr[ee] is cleared when the exception occurs. table 130 lists register settings when an external input interrupt is taken. ivor4 is the vector offset register used by autovectored external input interrupts to determine the interrupt handler location. the e200z3 also pr ovides the capability to directly vector external input interrupts to multiple handlers by allowing an external input interrupt request to be accompanied by a vector offset. the p_voffset[0:11] input signals are used in msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 esr [xte, bo, mif, vlemi]. all other bits cleared. mcsr unchanged dear unchanged vector ivpr[32?47] || ivor3[48?59] || 0b0000 table 129. instruction storage interrupt register settings (continued) register setting description table 130. external input interrupt register settings register setting description srr0 set to the effective address of the instruction the processor would attempt to execute next if no exception were present. srr1 set to the contents of the ms r at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 esr unchanged mcsr unchanged dear unchanged vector ivpr[32?47] || ivor4[48?59] || 0b0000 ivpr[32?47] || p_voffset[0:11] || 0b0000 (non-autovectored)
interrupts and exceptions UM0434 174/391 place of the value in ivor4 when an external input interrupt request is not autovectored ( p_avec_b negated when p_extint_b asserted). 6.6.6 alignment interrupt (ivor5) the e200z3 implements the alignment interrupt as defined by book e. an alignment exception is generated when any of the following occurs: the operand of lmw or stmw is not word-aligned. the operand of lwarx or stwcx. is not word-aligned. execution of dcbz is attempted execution is attempted of an spe apu load or store instruction that is not properly aligned. table 131 lists register settings when an alignment interrupt is taken. 6.6.7 program interrupt (ivor6) the e200z3 implements the program interrupt as defined by book e. a program interrupt occurs when no higher priority exception exists and one or more of the following exception conditions defined in book e occur: illegal instruction exception privileged instruction exception trap exception unimplemented operation exception the e200z3 invokes an illegal instruction program exception on attempted execution of the following instructions: instruction from the illegal instruction class mtspr and mfspr instructions that specify an undefined spr mtdcr and mfdcr instructions that specify an undefined dcr table 131. alignment interrupt register settings register setting description srr0 set to the effective address of the excepting load/store instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 esr [st], [vlemi ] . all other bits cleared. mcsr unchanged dear set to the effective address of a byte of the load or store whose access caused the violation. vector ivpr[32?47] || ivor5[48?59] || 0b0000
UM0434 interrupts and exceptions 175/391 the e200z3 invokes a privileged instruction program exception on attempted execution of the following instructions wh en msr[pr]=1 (user mode): a privileged instruction mtspr and mfspr instructions that specify an sprn value with sprn[5] = 1 (even if the spr is undefined). the e200z3 invokes a trap exception on execution of tw and twi if the trap conditions are met and the exception is not also enabled as a debug interrupt. the e200z3 invokes an unimplemented operation program exception on attempted execution of the instructions lswi , lswx , stswi , stswx , mfapidi , mfdcrx , mtdcrx , or any book e floating-point instruction when msr[fp]=1. all other defined or allocated instructions that are not impl emented by the e200z3 cause an illegal instruction program exception. table 132 lists register settings when a program interrupt is taken. 6.6.8 floating-point unavailable interrupt (ivor7) the floating-point unavailable interrupt is implemented as defined in book e. a floating-point unavailable interrupt occurs when no higher priority exception exists, an attempt is made to execute a book e-defined floating-point instruction (including floating-point load, store, or move instructions), and the floating-point available bit in the msr is cleared (msr[fp]=0). table 133 lists register settings when a floatin g-point unavailable interrupt is taken. table 132. program interrupt register settings register setting description srr0 set to the effective address of the excepting instruction. srr1 set to the contents of the msr at the time of the interrupt. msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 esr illegal: privileged: trap: unimplemented: pil, [vlemi]. all other bits cleared. ppr, [vlemi]. all other bits cleared. ptr, [vlemi]. all other bits cleared. puo, [fp], [vlemi]. all other bits cleared. mcsr unchanged dear unchanged vector ivpr[32?47] || ivor6[48?59] || 0b0000 table 133. floating-point unavailable interrupt register settings register setting description srr0 set to the effective address of the excepting instruction. srr1 set to the contents of the msr at the time of the interrupt
interrupts and exceptions UM0434 176/391 6.6.9 system call interrupt (ivor8) a system call interrupt occu rs when a system call ( sc, se_sc ) is executed and no higher priority exception exists. exception extensions implemented in e200z3 for vle include modification of the system call interrupt definition to include updating the esr. table 134 lists register settings when a system call interrupt is taken. 6.6.10 auxiliary processor una vailable interrupt (ivor9) an apu exception is defined by book e to occur when an attempt is made to execute an apu instruction which is implemented but configured as unavailable, and no higher priority exception condition exists. the e200z3 does not use this interrupt. msr ucle 0 spe 0 we 0 ce ? pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 esr unchanged mcsr unchanged dear unchanged vector ivpr[32?47] || ivor7[48?59] || 0b0000 table 133. floating-point unavailable interrupt register settings register setting description table 134. system call interrupt register settings register setting description srr0 set to the effective address of the instruction following the sc instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 esr [vlemi]. all other bits cleared. mcsr unchanged dear unchanged vector ivpr[32?47] || ivor8[48?59] || 0b0000
UM0434 interrupts and exceptions 177/391 6.6.11 decrementer interrupt (ivor10) the e200z3 implements the decrementer exception as described in book e. a decrementer interrupt occurs when no higher priority exception exists, a decrementer exception condition exists (tsr[dis]=1), and the interrupt is enabled (both tcr[die] and msr[ee]=1). the timer status register (tsr) holds the decr ementer interrupt bit se t by the timer facility when an exception is detected. the interrupt handler must clear this bit to avoid repeated decrementer interrupts. table 135 lists register settings when a decrementer interrupt is taken. 6.6.12 fixed-interval timer interrupt (ivor11) the e200z3 implements the fixed-interval timer exception as defined in book e. the triggering of the exception is caused by selected bits in the time base register changing from 0 to 1. a fixed-interval timer interrupt occurs when no higher priority exception exists, a fixed- interval timer exception exists (tsr[fis]=1), and the interrupt is enabled (both tcr[fie] and msr[ee]=1). the timer status register (tsr) holds the fixed-interval timer interrupt bit set by the timer facility when an exception is detec ted. software must clear this bit in the interrupt handler to avoid repeated fixed-interval timer interrupts. table 136 lists register settings when a fixe d-interval timer interrupt is taken. table 135. decrementer interrupt register settings register setting description srr0 set to the effective address of the instruction that the processor would have attempted to execute next if no exceptio n conditions were present. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 esr unchanged mcsr unchanged dear unchanged vector ivpr[32?47] || ivor10[48?59] || 0b0000 table 136. fixed-interval timer interrupt register settings register setting description srr0 set to the effective address of the instructio n that the processor would have attempted to execute next if no exception conditions were present. srr1 set to the contents of the ms r at the time of the interrupt.
interrupts and exceptions UM0434 178/391 6.6.13 watchdog timer interrupt (ivor12) the e200z3 implements the watchdog timer interrupt as defined in book e. the exception is triggered by the first enabled watchdog timeout. a watchdog timer interrupt occurs when no higher priority exception exists, a watchdog timer exception exists (tsr[wis]=1), and the interrupt is enabled (both tcr[wie] and msr[ce] = 1). the tsr holds the watchdog in terrupt bit set by the timer facility when an exception is detected. software must clear this bit in the interrupt handler to avoid repeated watchdog interrupts. table 137 lists register settings when a watchdog timer interrupt is taken. msr[de] is not automatically cleared by a watchdog timer interrupt, but can be configured to be cleared through hid0[ciclrde]. see chapter 4.13.1: hardware implementation dependent register 0 (hid0) on page 84 .? msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 esr unchanged mcsr unchanged dear unchanged vector ivpr[32?47] || ivor11[48?59] || 0b0000 table 136. fixed-interval timer interrupt register settings (continued) register setting description table 137. watchdog timer interrupt register settings register setting description csrr0 set to the effective address of the instructi on that the processor would have attempted to execute next if no exception conditions were present. csrr1 set to the contents of the ms r at the time of the interrupt msr ucle 0 spe 0 we 0 ce 0 ee 0 pr 0 fp 0 me ? fe0 0 de 0/? (1) fe1 0 is 0 ds 0 1. de is cleared when the debug apu is disabled. clearing of de is optionally supported by control in hid0 when the debug apu is enabled. esr unchanged mcsr unchanged dear unchanged vector ivpr[32?47] || ivor12[48?59] || 0b0000
UM0434 interrupts and exceptions 179/391 6.6.14 data tlb erro r interrupt (ivor13) a data tlb error interrupt occurs when no higher priority exception exists and a data tlb error exception occurs due to a data tlb miss. table 138 lists register settings for dtlb interrupts. 6.6.15 instruction tlb error interrupt (ivor14) an instruction tlb error interrupt occurs when no higher priority exception exists and an instruction tlb error exception ex ists due to an instruction translation lookup miss in the tlb. table 139 lists register settings when an itlb interrupt is taken. table 138. data tlb error interrupt register settings register setting description srr0 set to the effective address of the excepting load/store instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 esr [st], [spe], [vlemi]. al l other bits cleared. mcsr unchanged dear set to the effective address of a byte of the load or store whose access caused the violation. vector ivpr[32?47] || ivor13[48?59] || 0b0000 table 139. instruction tlb error interrupt register settings register setting description srr0 set to the effective address of the excepting instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 esr [mif] all other bits cleared. mcsr unchanged dear unchanged vector ivpr[32?47] || ivor14[48?59] || 0b0000
interrupts and exceptions UM0434 180/391 6.6.16 debug interrupt (ivor15) the e200z3 implements the debug interrupt as defined in book e with changes as follows: when the debug apu is enabled (hid0[dapuen] = 1), debug is no longer a critical interrupt but uses dsrr0 and dsrr1 for saving machine state on context switch. the return from debug interrupt instruction ( rfdi ) supports the debug apu save/restore registers (dsrr0 and dsrr1). the critical interrupt taken debug event allows critical interrupts to generate a debug event. the critical return debug event allows debug events to be generated for rfci instructions. multiple sources can signal a debug exception. a debug interrupt occurs when no higher priority exception exists, a debug exception is indicated in the debug status register (dbsr), and debug interrupts are enabled (dbcr0[idm] = 1 (internal debug mode) and msr[de] = 1). enabling debug events and other debug modes is discussed in chapter 11: debug support .? with the debug apu enabled (see chapter 4.13.1: hardware implementation dependent register 0 (hid0) on page 84 ? ), the debug interrupt uses its own set of save/restore registers (dsrr0, dsrr1) to allow debugging of both critic al and non-critical interrupt handlers. this capability also allows interrupts to be handled while in a debug software handler. external and critical interrupts are not automatically disabled when a debug interrupt occurs but can be configured to be cleared through hid0[dclree,dclrce]. see chapter 4.13.1: hardware implementation dependent register 0 (hid0) on page 84 .? when the debug apu is disabled, debug interrupts use csrr0 and csrr1 to save machine state. note: for details regarding the following de scriptions of debug exception types, see chapter 11.4: software debug events and exceptions on page 299 .? table 140. debug exceptions exception cause instruction address compare (iac) instruction address compare events are enabled and an instruction address match occurs as defined by the debug control registers. this could either be a direct instruction address match or a selected set of instruction addresses. iac has the hig hest priority of all instruction-based interrupts, even if the instruction itself encountered an itlb error or instruction storage exception. branch taken (brt) a branch instruction is considered taken by the br anch unit ,and branch taken events are enabled. the debug interrupt is taken when no higher priority exception is pending. data address compare (dac) data address compare events are enabled, and a dat a access address match occurs as defined by the debug control registers. this could either be a direct data address match or a selected set of data addresses. the debug interrupt is taken when no higher priority exception is pending. the e200z3 does not implement the data value compar e debug mode, specified in book e. the e200z3 implementation provides iac linked with dac exceptio ns. this results in a dac exception only if one or more iac conditions are also met. trap (trap) debug program trap exception is generated while trap events are enabled. if msr[de] is set, the debug exception has higher priority than the program exce ption and is taken instead of a trap type program interrupt. the debug interrupt is taken when no higher priority exception is pending. if msr[de] is cleared when a trap debug exception occurs, a trap exception type program interrupt is taken instead.
UM0434 interrupts and exceptions 181/391 the dbsr provides a syndrome to differentiate among debug exceptions that can generate the same interrupt. table 141 lists register settings when a debug interrupt is taken. return (ret) return exceptions are enabled and rfi is executed. return debug exceptions are not generated for rfci or rfdi . if msr[de] = 1 when rfi executes, a debug interrupt occurs if no higher priority, enabled exception exists. csrr0 (debug apu disabled) or dsrr0 (debug apu enabled) is to set the address of the rfi . if msr[de] = 0 when rfi executes, a debug interrupt does not occur immediately; the event is recorded by setting dbsr[ret] and dbsr[ide]. critical return (cret) critical return debug events are enabled and rfci is executed. critical return debug exceptions are only generated for rfci . if msr[de]=1 when rfci executes, a debug interrupt occurs if no higher priority exception exists that is enabled to c ause an interrupt. csrr0 (debug apu disabled) or dsrr0 (debug apu enabled) is set to the address of the rfci . if msr[de] = 0 when rfci executes, a debug interrupt does not occur immediately, but t he event is recorded by setting dbsr[cret] and dbsr[ide]. note that critical return debug event s should not normally be enabled unless the debug apu is enabled to avoid corrupting csrr0 and csrr1. instruction complete (icmp) an instruction completed while this event is enabled. a mtmsr or mtdbcr0 that causes both msr[de] and dbcr0[idm] to end up set, enabling precise debug mode, may cause an imprecise (delayed) debug exception to be generated due to an earlier recorded event in the dbsr. interrupt taken (irpt) a non-critical interrupt context switch is detected. this exception is imprecise and unordered with respect to the program flow. note that an irpt debug interrupt occurs only when detecting a non- critical interrupt on the e200z3. the value saved in csrr0/dsrr0 is the address of the non-critical interrupt handler. critical interrupt taken (cirpt) a critical interrupt context swit ch is detected. this exception is imprecise and unordered with respect to program flow. note that a cirpt debug interrupt occurs only when detecting a critical interrupt on the e200z3. the addre ss of the critical interrupt handler is saved in csrr0/dsrr0. to avoid corrupting csrr0 and csrr1, critical interrupt taken debug events should not normally be enabled unless the debug apu is enabled. unconditional debug event (ude) the unconditional debug event signal ( p_ude ) transitions to asserted state. debug counter a debug counter exception is enabled and a debug counter decrements to zero. external debug an external debug exception is enabled and an external debug event ( p_devt1 , p_devt2 ) transitions to the asserted state. table 140. debug exceptions (continued) exception cause table 141. debug interrupt register settings register setting description csrr0 (msr[de]=0) dsrr0 (1) (msr[de]=1) set to the effective address of the excepting instruction for iac, brt, ret, cret, and trap. set to the effective address of the next inst ruction to be executed following the excepting instruction for dac and icmp. for ude, irpt, cirpt, dcnt, or devt type exceptions, set to the effective address of the instruction that would have atte mpted to execute next if no e xception conditions were present. csrr1/ dsrr1 set to the contents of the msr at the time of the interrupt
interrupts and exceptions UM0434 182/391 6.6.17 system reset the core implements the system reset, which is not an interrupt defined in book e. the system reset exception is a non-maskable, asynchronous exception signaled to the processor through the assertion of system-defined signals. a system reset may be initiated as follows: by asserting the p_reset_b input. p_reset_b must remain asserted for a period (specified in the hardware specifications) that allows internal logic to be reset. assertion for less than the required interval causes unpredictable results. by asserting m_por during power-on reset. m_por must be asserted during power up and must remain asserted for a period (specified in the hardware specifications) that allows internal logic to be reset. assertion for less than the required interval causes unpredictable results. by watchdog timer reset control by debug reset control msr ucle 0 spe 0 we 0 ce ?/0 (2) ee ?/0 2 pr 0 fp 0 me ? fe0 0 de 0 fe1 0 is 0 ds 0 dbsr (3) unconditional debug event: instruction complete debug event: branch taken debug event: interrupt taken debug event: critical interrupt taken debug event: trap instruction debug event: instruction address compare: data address compare: return debug event: critical return debug event: debug counter event: external debug event: (optional) imprecise debug event flag ude icmp brt irpt cirpt trap {iac1, iac2, iac3, iac4} {dac1r, dac1w, dac2r, dac2w} ret cret {dcnt1, dcnt2} {devt1, devt2} {ide} esr unchanged mcsr unchanged dear unchanged vector ivpr[32?47] || ivor15[48?59] || 0b0000 1. assumes that the debug interrupt is precise 2. conditional based on hid0 control bits. 3. note that multiple dbsr bits may be set. table 141. debug interrupt register settings (continued) register setting description
UM0434 interrupts and exceptions 183/391 when a reset request occurs, the processor branches to the system reset exception vector (value on p_rstbase[0:19] concatenated with 0xffc) without attempting to reach a recoverable state. if reset occurs during normal operation, all operations stop and machine state is lost. the internal state of the e200z6e200z3 after a reset is defined in chapter 4.18.4: reset settings .? for reset initiated by watchdog timer or debug reset control, the e200z6 implements tsr[wrs] or dbsr[mrr] to help software determine the cause. watchdog timer and debug reset control provid e the capability to assert p_resetout_b . external logic may factor this signal into p_reset_b to cause an e200z6e200z3 reset. table 142 shows the tsr bits associated with reset status. table 143 shows the dbsr bits associated with reset status. table 144 lists register settings wh en a system reset is taken. 6.6.18 spe apu unavailab le interrupt (ivor32) the spe apu unavailable exception is taken if msr[spe] is cleared and execution of an spe apu instruction other than an embedded scalar fl oating-point or brinc instruction is attempted. when the spe apu unavailable exception occurs, the processor suppresses table 142. tsr watchdog timer reset status bits name description 34?35 wrs 00 no action performed by watchdog timer 01 watchdog timer second timeout caused checkstop. 10 watchdog timer second timeout caused p_resetout_b to be asserted. 11 reserved table 143. dbsr most recent reset bits name function 34?35 mrr 00 no reset occurred since these bits were last cleared by software. 01 a reset occurred since these bits were last cleared by software. 1 x reserved table 144. system reset register settings register setting description csrr0 undefined csrr1 undefined msr ucle 0 we 0 ce 0 ee 0 pr 0 fp 0 me 0 de 0 fe1 0 is 0 ds 0 esr cleared dear undefined vector [ p_rstbase[0:19] ] || 0xffc
interrupts and exceptions UM0434 184/391 execution of the instruction causing the exception. table 145 lists register settings when an spe unavailable interrupt is taken. 6.6.19 spe float ing-point data interrupt (ivor33) the spe floating-point data interr upt is taken if no higher prio rity exception exists and an spe floating-point data exceptio n is generated. when a fl oating-point data exception occurs, the processor suppresses execution of the instruction causing the exception. table 146 lists register settings when an spe floating-point data interrupt is taken. table 145. spe unavailable in terrupt register settings register setting description srr0 set to the effective address of the excepting spe instruction srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 esr spe, [vlemi]. all other bits cleared. mcsr unchanged dear unchanged vector ivpr[32?47] || ivor32[48?59] || 0b0000 table 146. spe floating-point data interrupt regi ster settings register setting description srr0 set to the effective address of the excepting spe instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 esr spe, [vlemi]. all other bits cleared. mcsr unchanged dear unchanged vector ivpr[32?47] || ivor33[48?59] || 0b0000
UM0434 interrupts and exceptions 185/391 6.6.20 spe float ing-point round interrupt (ivor34) the spe floating-point round interrupt is taken when an spe floating-point instruction generates an inexact result and inexact exceptions are enabled. table 147 lists register settings when an spe floating-point round interrupt is taken. 6.7 exception recognition and priorities the following list of exception categories de scribes how the e200z3 handles exceptions up to the point of signaling the appropriate interrupt to occur. also, instruction completion is defined as updating all architectural registers associated with that instruction as necessary, and then removing the instruction from the pipeline. interrupts caused by asynchronous events (exceptions). these exceptions are further distinguished by whether they are maskable and recoverable. ? asynchronous, non-maskable, non-recoverable: system reset by assertion of p_reset_b. has highest priority and is taken immediately regardless of other pending exceptions or recoverability. (include s watchdog timer reset control and debug reset control) ? asynchronous, maskable, non-recoverable: machine check interrupt. has priority over any other pending exception except system reset conditions; is dependent on the source of the exception. typically non-recoverable. ? asynchronous, maskable, recoverable: external input, fixed-interval timer, decrementer, critical input, unconditional debug, external debug event, debug counter event, and watchdog timer interrupts. before handling this type of exception, the processor needs to reach a recoverable state. a maskable recoverable exception remains pending until taken or cancelled by software. table 147. spe floating-point round interrupt regi ster settings register setting description srr0 set to the effective addre ss of the instruction following the excepting spe instruction. srr1 set to the contents of the msr at the time of the interrupt msr ucle 0 spe 0 we 0 ce ? ee 0 pr 0 fp 0 me ? fe0 0 de ? fe1 0 is 0 ds 0 esr spe, [vlemi]. all other bits cleared. mcsr unchanged dear unchanged vector ivpr[32?47] || ivor34[48?59] || 0b0000
interrupts and exceptions UM0434 186/391 synchronous, non-instruction-based interrupts. the only exception in this category is the interrupt taken debug exception, recognized by an interrupt taken event. it is not considered instruction-based but is synchronous with respect to program flow. ? synchronous, maskable, recoverable: interrupt taken debug event. the machine is in a recoverable state due to the state of the machine at the context switch triggering this event. instruction-based interrupts. these interrupts are further organized by the point in instruction processing in which they generate an exception. ? instruction fetch: instruction storage, instruction tlb, and instruction address compare debug exceptions. once these types of exceptions are detected, the excepting instruction is tagged. when the excepting instruction is next to begin execution and a recoverable state has been reached, the interrupt is taken. if an event prior to the excepting instruction causes a redirection of execution, the instruction fetch exception is discarded (but may be encountered again). ? instruction dispatch/execution: program, system call, data storage, alignment, floating-point unavailable, spe unavailabl e, data tlb, spe floating-point data, spe floating-point round, debug (trap, branch taken, return) interrupts. determined during decode or execution of an instruction. the exception remains pending until all instructions before the exception-causing instruction complete. the interrupt is then taken without completing the exception-causing instruction. if completing previous instructions causes an exception, that exception takes priority over the pending instruction dispatch/execution exception, which is discarded (but may be encountered again when instruction processing resumes). ? post-instruction execution: debug (data address compare, instruction complete) interrupt generated following execution and completion of an instruction while the event is enabled. if executing the instruction produces conditions for another type of exception with higher priority, that exception is taken and the post-instruction exception is discarded for the instruction (but may be encountered again when instruction processing resumes). 6.7.1 interrupt priorities interrupts are prioritized as described in table 148 . some exceptions may be masked or imprecise, which affects their priority. non-maskable exceptions such as reset and machine check may occur at any time and are not delayed even if an interrupt is being serviced; thus, state information for any interrupt may be lost. reset and most machine checks are non- recoverable. table 148. e200z3 exception priorities priority exception cause ivor asynchronous exceptions system reset assertion of p_reset_b , watchdog timer reset control, or debug reset control none machine check assertion of p_mcp_b , exception on fetch of first instruction of an interrupt handler, bus error on buffered store , bus error (xte) with msr[ee]=0 and current msr[me]=1 1
UM0434 interrupts and exceptions 187/391 ?? ? (1) debug: ude debug: devt1 debug: devt2 debug: dcnt1 debug: dcnt2 debug: ide assertion of p_ude (unconditional debug event) assertion of p_devt1 and event enabled (external debug event 1) assertion of p_devt2 and event enabled (external debug event 2) debug counter 1 exception debug counter 2 exception imprecise debug event (event imprecise due to earlier, higher priority interrupt 15 1 critical input assertion of p_critint_b 0 1 watchdog timer watchdog timer first enabled time-out 12 1 external input assertion of p_extint_b 4 1 fixed-interval timer posting of a fixed-interval timer exception in tsr due to programmer-specified bit transition in the time base register 11 1 decrementer posting of a decrementer exception in tsr due to programmer-specified decrementer condition 10 instruction fetch exceptions debug: iac (unlinked) instruction address compare match for enabled iac debug event and dbcr0[idm] asserted 15 itlb error instruction translation lookup miss in the tlb 14 instruction storage access control precise external termination error ( p_tea_b assertion and precise recognition) and msr[ee] = 1 byte ordering due to misaligned instruction across page boundary to pages with mismatched vle bits, or access to page with vle set and e indicating little-endian. misaligned instruction fetch due to a change of flow to an odd halfword instruction boundary on a booke (non-vle) instruction page, due to value in lr, ctr, or x srr0 3 instruction dispatch/ execution interrupts program: illegal attempted execution of an illegal instruction 6 program: privileged attempted execution of a privileged instruction in user mode 6 floating-point unavailable any floating-point unavailable exception condition 7 spe unavailable any spe unavaila ble exception condition 32 program: unimplemented attempted execution of an unimplemented instruction 6 table 148. e200z3 exception priorities (continued) priority exception cause ivor
interrupts and exceptions UM0434 188/391 debug: brt debug: trap debug: ret debug: cret attempted execution of a taken branch instruction condition specified in tw or twi instruction met. attempted execution of a rfi instruction attempted execution of an rfci instruction exceptions require corresponding debug event enabled, msr[de]=1, and dbcr0[idm]=1. 15 program: trap condition specified in tw or twi instruction met and not a debug trap exception 15 system call execution of the system call ( sc, se_sc ) instruction. 8 spe floating-point data nan, infinity, or denormalized data detected as input or output, or underflow, overflow, divide by zero, or invalid operation in the spe apu. 33 spe round inexact result 34 alignment lmw , stmw, lwarx, or stwcx. not word aligned. dcbz with cache disabled or not present 5 debug with concurrent dtlb or data storage interrupt: dac/iac linked (2) dac unlinked 2 debug with concurrent dtlb or data storage interrupt. dbsr[ide] also set. data address compare linked with instruction address compare data address compare unlinked note : exceptions require corresponding debug event enabled, msr[de]=1, and dbcr0[idm]=1. in this case, the debug exception is considered imprecise and dbsr[ide] is set. saved pc points to the lo ad or store instruction causing the dac event. 15 data tlb error data translation lookup miss in the tlb. 13 data storage access control. byte ordering due to misaligned access across page boundary to pages with mismatched e bits. precise external termination error ( p_tea_b assertion and precise recognition) and msr[ee]=1 2 debug: irpt debug: cirpt interrupt taken (non-critical) critical interrupt taken (critical only) note : exceptions require corresponding debug event enabled, msr[de]=1 and dbcr0[idm]=1. 15 table 148. e200z3 exception priorities (continued) priority exception cause ivor
UM0434 interrupts and exceptions 189/391 6.8 interrupt processing when an interrupt is taken, srr0/srr1 fo r non-critical interrupts, csrr0/csrr1 for critical interrupts, and either csrr0/csrr1 or dsrr0/dsrr1 for debug interrupts are used to save the contents of the msr and to help identify where instruction execution should resume after the interrupt is handled. when an interrupt occurs, one of srr0/csrr0/dsrr0 is set to the address of the instruction that caused the exception or to the following instruction if appropriate. srr1 is used to save machine state (selected msr bits) on non-critical interrupts and to restore those values when an rfi executes. csrr1 is used to save machine status (selected msr bits) on critical interrupts and to restore those values when an rfci instruction is executed. dsrr1 is used to save machine status (selected msr bits) on debug interrupts when the debug apu is enabled and to restore those values when an rfdi executes. the esr is loaded with informat ion specific to the exception type. some interrupt types can only be caused by a single exception type an d thus do not use an esr setting to indicate the interrupt cause. the msr is updated to preclude unrecoverable interrupts from occurring during the initial portion of the interrupt handler. specific settings are described in table 149 . for alignment, data storage, or data tlb miss interrupts, or for a machine check due to cache parity error on data access interrupts, the data exception address register (dear) is loaded with the address that caused the interrupt to occur. for machine check interrupts, the mcsr is load ed with information specific to the exception type. post-instruction ex ecution exceptions debug: dac/iac linked 2 debug: dac unlinked 2 data address compare linked with instruction address compare data address compare unlinked notes : exceptions require corresponding debug event enabled, msr[de] = 1 and dbcr0[idm] = 1. saved pc points to the instruct ion following the load or store instruction causing the dac event. 15 debug: icmp completion of an instruction. note : exceptions require corresponding debug event enabled, msr[de]=1, and dbcr0[idm]=1. 15 1. these exceptions are sampled at instruction boundarie s, and may actually occur after exceptions that are due to a currently executing instruction. if one of thes e exceptions occurs during execution of an instruction in the pipeline, it is not proces sed until the pipeline has been flushed, and the exception associated with the excepting instruction may occur first. 2. when no data storage interrupt or data tlb error oc curs, the core implements the data address compare debug exceptions as post-instruction exceptions, which differs from the book e definition. when a tea (either a dtlb error or data storage interrupt) oc curs in conjunction with an enabled dac or linked dac/iac on a load or store class instruction, the debug interrupt takes priority, and the saved pc value points to the load or store class instruct ion, rather than to the next instruction. table 148. e200z3 exception priorities (continued) priority exception cause ivor
interrupts and exceptions UM0434 190/391 instruction fetch and execution resume, using the new msr value, at a location specific to the exception type. the location is determined by the ivpr and an ivor specific for each type of interrupt (see table 114 ). a new operating context is selected using the low-order three bits of the specific ivor selected by the type of interrupt. table 149 shows the msr settings for different interrupt categories. note that reserved and preserved msr bits are unimplemented and are read as 0. 6.8.1 enabling and disabling exceptions when a condition exists that may cause an exception to be generated, it must be determined whether the exception is enabled for that condition. system reset exceptions cannot be masked. a machine check exception can occur only if the machine check enable, msr[me], = 1. if me = 0, the processor goes directly into checkstop state when a machine check exception condition occurs. individual ma chine check exceptions can be enabled and disabled through hid0 bits. asynchronous, maskable non-critical exceptions (such as the external input and decrementer) are enabled by setting msr[ee]. when ee = 0, recognition of these exception conditions is delayed. ee is cleared automatically when a non-critical or critical interrupt is taken to mask furthe r recognition of conditions causing those exceptions. asynchronous, maskable critical exceptions (such as critical input and watchdog timer) are enabled by setting msr[ce]. when ce = 0, recognition of these exception conditions is delayed. ce is cleared automatic ally when a critical interrupt is taken to mask further recognition of conditions causing those exceptions. synchronous and asynchronous debug exceptions are enabled by setting msr[de]. if de = 0, recognition of these exception conditions is masked. de is cleared table 149. msr setting due to interrupt bits msr definition reset settin g non-critical interrupt criti cal interrupt debug interrupt 37 ucle 0 0 0 0 38 spe 0 0 0 0 45 we 0 0 0 0 46 ce 0 ? 0 ?/0 (1) 1. conditionally cl eared based on control bits in hid0 48 ee 0 0 0 ?/0 1 49 pr 0 0 0 0 50 fp 0 0 0 0 51 me 0 ? ? ? 52 fe0 0 0 0 0 54 de 0 ? ?/0 1 0 55 fe1 0 0 0 0 58 is 0 0 0 0 59 ds 0 0 0 0
UM0434 interrupts and exceptions 191/391 automatically when a debug interrupt is taken to mask further recognition of conditions causing those exceptions. chapter 11: debug support ,? gives details on individual control of debug exceptions. the floating-point unavailable exception can be prevented by setting msr[fp] (although the e200z3 generates an unimplemented instruction exception instead). 6.8.2 returning from an interrupt handler the return from interrupt ( rfi ), return from critical interrupt ( rfci ) and return from debug interrupt ( rfdi ) instructions perform context synchronization by allowing instructions issued earlier to complete before returning to the interrupted process. in general, execution of rfi , rfci , or rfdi ensures the following: all previous instructions have completed to a point where they can no longer cause an exception. this includes post-execute type exceptions. previous instructions complete execution in the context (privilege and protection) under which they were issued. the rfi copies srr1 bits back into the msr. the rfci copies csrr1 bits back into the msr. the rfdi copies dsrr1 bits back into the msr. instructions fetched after this execution in the context established by this instruction. program execution resumes at the instruction indicated by srr0 for rfi , csrr0 for rfci or dsrr0 for rfdi . note that the rfi may be subject to a return type debug exception and that rfci may be subject to a critical return type debug exception. for a complete description of context synchronization, refer to the eref . 6.9 process switching the following instructions are useful for restoring proper context during process switching: msync orders the effects of data memory instruction execution. all instructions previously initiated appear to have completed before the msync instruction completes, and no subsequent instructions appear to be initiated until the msync instruction completes. isync waits for all previous instructions to complete and then discards any fetched instructions, causing subsequent instructions to be fetched (or refetched) from memory and to execute in the context (privilege, translation, and protection) established by the previous instructions. stwcx. clears any outstanding reservations, ensuring that a load and reserve instruction in an old process is not paired with a store conditional instruction in a new one.
memory management unit UM0434 192/391 7 memory management unit this chapter describes the implementation details of the e200z3 core complex mmu relative to the book e architecture and the freescale book e standards. 7.1 overview the e200z3 memory management unit is a 32-bit powerpc book e?compliant implementation. 7.1.1 mmu features the mmu of the e200z3 core has the following feature set: freescale book e implementation standard (eis) mmu architecture compliant 32-bit effective address translated to 32-bit real address (using a 41-bit interim virtual address) 16-entry, fully associative, translation lookaside buffer (tlb1) that supports the nine page sizes (4 kbytes, 16 kbytes, 64 kbytes, 256 kbytes, 1 mbyte, 4 mbytes, 16 mbytes, 64 mbytes, 256 mbytes), shown in table 151 one 32-bit pid register (pid0) for supporting up to 255 translation ids at any time in the tlb no page table format defined; software is free to use its own page table format hardware assist for tlb miss exceptions tlb1 managed by tlbre , tlbwe , tlbsx , tlbsync , and tlbivax instructions and six mmu assist (mas) registers iprot bit implemented in tlb1 prevents invalidations, protecting critical entries (so designated by having the iprot bit set) from being invalidated. 7.1.2 tlb entry maintenance features summary the tlb entries of the e200z3 core complex must be loaded and maintained by the system software; this includes performing any required table search operations in memory. the e200z3 provides support for maintaining tlb entries in software with the resources shown in table 150 . note that many of these features are defined at the freescale book e level.
UM0434 memory management unit 193/391 other hardware assistance features for maintenance of the tlb on the e200z3 are described in chapter : mas register updates on page 205 .? 7.2 effective to real address translation this section describes the general principles that guide the powerpc book e definition for memory management and further describes the structure for mmus defined by the freescale book e implementation standard (eis) and the e200z3 mmu. figure 7 shows the high-level translation flow, showing that because the smallest page size supported by the e200z3 core complex is 4 kbytes, the 12 lsbs always index within the page and are untranslated. table 150. tlb maintenance programming model features description section/page tlb instructions tlbre tlb read entry instruction chapter 7.4 on page 200 tlbwe tlb write entry instruction chapter 7.4 on page 200 tlbsx r a , r b tlb search for entry instruction chapter 7.4 on page 200 tlbivax r a , r b tlb invalidate entries instruction chapter 7.4 on page 200 tlbsync tlb synchronize invalidations with other masters? instruction (privileged no-op on the e200z3) chapter 7.4 on page 200 registers pid0 process id register chapter 4.4.2 on page 45 mmucsr0 mmu control and status register chapter 4.16.1 on page 88 mmucfg mmu configuration register chapter 4.16.2 on page 89 tlb0cfg?tlb1cfg tlb configuration registers chapter 4.16.3 on page 90 mas0?mas4, mas6 mmu assist registers. note: e200z3 does not implement mas5. chapter 4.16.4 on page 91 dear data exceptio n address register chapter on page 57 interrupts instruction tlb miss exception causes instruction tlb error interrupt chapter 6.6.15 on page 179 data tlb miss exception causes data tlb error interrupt chapter 6.6.14 on page 179 instruction permission violation exception causes isi interrupt chapter 6.6.4 on page 172 data permission violation exception causes dsi interrupt chapter 6.6.3 on page 171
memory management unit UM0434 194/391 figure 7. effective to real address translation flow 32-bit effective address 32-bit real address virtual address note: n = 32?log 2 (page size) n> = 20 n = 20 for 4-kbyte page size pid effective page address offset 0n 31 tlb multiple-entry msr[is] for instruction fetch as msr[ds] for data access rpn field of matching entry n?1 real page number offset 0n 31 n?1 effective page number byte address real page number byte address 32-bit effective address (ea) 32-bit real address 15?20 bits* > 12 bits* 15?20 bits* > 12 bits* mmu (unified) three 41-bit virtual addresses (vas) 8 bits msr is ds instruction access data access as pid0 * number of bits depends on page size (4 kbytes?128 mbytes) 32-entry fully?assoc. vsp array (tlb1) mas registers
UM0434 memory management unit 195/391 7.2.1 effective addresses instruction accesses are generated by sequential instruction fetches or due to a change in program flow (branches and interrupts). data accesses are generated by load, store, and cache management instructions. the e200z3 instruction fetch, branch, and load/store units generate 32-bit effective addresses. the mmu translates these effective addresses to 32-bit physical (real) addresses that are then used for memory accesses. the powerpc book e architecture divides the effective (virtual) and real (physical) address space into pages. the page represents the granularity of effective address translation, permission control, and memory/cache attributes. the e200z3 mmu supports nine page sizes (4 kbytes to 256 mbytes, as defined in table 151 ). in order for an effective-to-real address translation to exist, a valid entry for the page containing the effective address must be in a tlb. accesses to addresses for which no tlb entry exists (a tlb miss) cause instruction or data tlb errors. 7.2.2 address spaces the powerpc book e architecture defines two effective address spaces for instruction accesses and two effective address spaces for data accesses. the current effective address space for instruction or data accesses is determined by the value of msr[is] (instruction address space bit) and msr[ds] (data address space bit), respectively. the address space indicator (the corresponding value of either msr[is] or msr[ds]) is used in addition to the effective address generated by the processor for translation into a physical address by the tlb mechanism. because msr[is] and msr[ds] are both cleared when an interrupt occurs, an address space value of 0 can be used to denote interrupt-related address spaces (or possibly all system software address spaces). an address space value of 1 can be used to denote non?interrupt-related address spaces or possibly all user address spaces. the address space associated with an instruction or data access is included as part of the virtual address in the translation process (as). 7.2.3 virtual addresses and process id the powerpc book e architecture requires a process id (pid) value to be associated with each effective address (instruction or data) generated by the processor to construct a virtual address for each access. at the book e level, a single pid register is defined as a 32-bit register, and it maintains the value of the pi d for the current process. this pid value is included as part of the virtual address in the translation process (pid0). for the e200z3 mmu, the pid is 8 bits in length. the most significant 24 bits are unimplemented and read as 0. the p_pid0[0:7] interface signals indicate the current process id. the core complex implements a single process id (pid) register, pid0, as an spr shown in chapter 4.16.5 on page 96 .? the current value in the pid regi ster is used in the tlb look-up process and compared with the tid field in all the tlb entries. if the pid value in pid0 matches with a tlb entry in which all the other match criteria are met, that entry is used for translation. note that when a tid value in a tlb entry is all zeros, it always causes a match in the pid compare (effectively ignoring the values of the pid register). thus, the operating system can set the values of all the tids to zero, effectively eliminating the pid value from all translation comparisons.
memory management unit UM0434 196/391 7.2.4 translation flow the effective address, concatenated with the address space value of the corresponding msr bit (msr[is] or msr[ds]), is compared to the appropriate number of bits of the epn field (depending on the page size) and the ts field of tlb entries. if the contents of the effective address plus the address space bit matches the epn field and ts bit of the tlb entry, that tlb entry is a candidate for a possible translation match. in addition to a match in the epn field and ts, a matching tlb entry must match with the current process id of the access (in pid0), or have a tid value of 0, indicating that the entry is globally shared among all processes. figure 8 shows the translation match logic for the effective address plus its attributes, collectively called the virtual address, and how it is compared with the corresponding fields in the tlb entries. figure 8. virtual address and tlb-entry compare process the page size defined for a tlb entry determines how many bits of the effective address are compared with the corresponding epn field in the tlb entry as shown in table 151 . on a tlb hit, the corresponding bits of the real page number (rpn) field are used to form the real address, and the generation of the physical address occurs as shown in figure 7 . table 151. page size (for e200z3 core) and epn field comparison size field page size (4 size kbytes) ea to epn comparison (bits 32?53; 2
UM0434 memory management unit 197/391 7.2.5 permissions an operating system may restrict access to vi rtual pages by selectively granting permissions for user-mode read, write, and execute, and supervisor-mode read, write, and execute on a per-page basis. these permissions can be set up for a particular system (for example, program code may be execute only, and data structures may be mapped as read/write/no- execute) and be changed by the operating system based on application requests and operating system policies. the ux, sx, uw, sw, ur, and sr access control bits are provided to support selective permissions (access control): sr?supervisor read permission. allows loads and load-type cache management instructions to access the page while in supervisor mode (msr[pr = 0]). sw?supervisor write permission. allows stores and store-type cache management instructions to access the page while in supervisor mode (msr[pr = 0]). sx?supervisor execute permission. allows instruction fetches to access the page and instructions to be executed from the page while in supervisor mode (msr[pr = 0]). ur?user read permission. allows loads and load-type cache management instructions to access the page while in user mode (msr[pr = 1]). uw?user write permission. allows stores and store-type cache management instructions to access the page while in user mode (msr[pr = 1]). ux?user execute permission. allows instruction fetches to access the page and instructions to be executed from the page while in user mode (msr[pr = 1]). if the translation match was successful, the permission bits are checked as shown in figure 9 . if the access is not allowed by the access permission mechanism, the processor generates an instruction or data storage interrupt (isi or dsi). figure 9. granting of access permission 7.3 translation lookaside buffer the eis architecture defines support for zero or more tlbs in an implementation, each with its own characteristics, and provides configuration information for software to query the existence and structure of tlbs through a set of sprs?mmucfg, tlb0cfg, tlb1cfg, and so on. by convention, tlb0 is used for a set-associative tlb with fixed page sizes, access granted instruction fetch msr[pr] tlb_entry[ux] tlb_entry[sx] tlb_entry[ur] tlb_entry[sr] tlb_entry[uw] tlb_entry[sw] load-class data access store-class data access tlb match (see figure 5-2 )
memory management unit UM0434 198/391 tlb1 is used for a fully-associative tlb with variable page sizes, and tlb2 is arbitrarily defined by an implementation. the e200z3 mmu supports a single tlb that is fully associative and supports variable page sizes; thus it corresponds to tlb1 in the programming model. for the rest of this document, tlb, tlbcam, and tlb1 are used interchangeably. the tlb on the e200z3 mmu (tlb1) consists of a 16-entry, fully-associative content- addressable memory (cam) array with support for nine page sizes. to perform a lookup, the tlb is searched in parallel for a matching tlb entry. the contents of a matching tlb entry are then concatenated with the page offset of the original effective address. the result constitutes the real (physical) address of the access. a hit to multiple tlb entries is considered to be a programming error. if this occurs, the tlb generates an invalid address and tlb entries may be corrup ted (an exception will not be reported). the structure of tlb1 is shown in figure 10 . figure 10. e200z3 tlb1 organization 7.3.1 iprot invalidation protection in tlb1 the iprot bit in tlb1 is used to protect tlb entries from invalidation. tlb1 entries with iprot set are not invalidated by a tlbivax instruction executed by this processor (even when the inv_all command is indicated), or by a flash invalidate initiated by writing to mmucsr0[tlb1_fi]. the iprot bit can be used to protect critical code and data such as interrupt vectors/handlers in order to guarantee that the instruction fetch of those vectors never takes a tlb miss exception. entries with iprot set can only be invalidated by writing a 0 to the valid bit of the entry (by using the mas registers and executing the tlbwe instruction). invalidation operations generated by execution of the tlbivax instruction are guaranteed to invalidate the entry that translates the address specified in the operand of the tlbivax instruction. additional entries may also be invalidated by this operation if they are not protected with iprot. a precise invalidation can be performed by writing a 0 to the valid bit of a tlb entry. 0 15 tlb1 compare compare rpn hit real address (translated bits, depending on page size) virtual address
UM0434 memory management unit 199/391 7.3.2 replacement algorithm for tlb1 the replacement algorithm for tlb1 must be implemented completely by system software. thus, when an entry in tlb1 is to be replaced, the software can select which entry to replace and write the entry number to the mas0[esel] field before executing a tlbwe instruction. alternately, the software can load the entry number of the next desired victim into mas0[nv]. the e200z3 t hen automatically lo ads mas0[esel] from mas0[nv] on a tlb error condition as shown in figure 11 . see table 156 for a complete description of mas register updates on various exception conditions. figure 11. victim selection 7.3.3 the g bit (of wimge) the g bit provides protection from bus accesses that could be canceled due to an exception on a prior uncompleted instruction. if g = 1 (guarded), these types of accesses must stall until the exception status of any instructions in progress is known. if g = 0 (unguarded), these accesses may be issued to the bus regardless of the completion status of other instructions. because the core does not make requests for load or st ore instructions until it is kn own that prior instructions will complete without exceptions, the g bit is essentially ignored. proper operation always occurs to guarded storage. 7.3.4 tlb entry field summary table 152 summarizes the fields of e200z3 tlb entries. note: all of these fields are defined at the freescale book e level. mas0 esel nv on tlbwe selectsentry tlb miss (tlb error interrupt) written by software table 152. tlb entry bit fields for e200z3 field description v valid bit for entry ts translation address space (compared with as bit of the current access) tid[0?7] translation id (compared wit h pid0 or tidz (all zeros)) epn[0?19] effective page number (com pared with effective address)
memory management unit UM0434 200/391 7.4 software interface and tlb instructions tlb1 is accessed indirectly through several mmu assist (mas) regist ers, which software can write and read with mtspr and mfspr instructions. mas registers contain information related to reading and writing a given entry within tlb1. data is read from the tlb into the mas registers with a tlbre (tlb read entry) instruction and is written to the tlb from the mas registers with a tlbwe (tlb write entry) instruction. certain fields of the mas registers are also written by hardware when an instruction tlb error, data tlb error, dsi, or isi interrupt occurs. on a tlb error interrupt, the mas registers are written by hardware with the proper ea, default attributes (tid, wimge, permissions, and so on), tlb selection information, and an entry in the tlb to replace. software manages this entry selection information by updating a replacement entry value during tlb miss handling. software must provide the correct rpn and permission information in one of the mas registers before executing a tlbwe instruction. on taking a dsi or isi interrupt, hardware updates only the search pid (spid) and search address space (sas) fields in the mas regist ers, using the conten ts of pid0 and the corresponding msr[is] or msr[ds] value used when the data or instruction storage interrupt was recognized. during the interrupt handler, software can issue a tlb search instruction ( tlbsx ), which uses the spid field along with the sas field, to determine the entry related to the data or instruction storage interrupt. note that it is possible that the entry that caused the data or instruction storage interrupt no longer exists in the tlb by the time rpn[0?19] real page number (translated address) size[0?3] encoded page size 0000 reserved 0001 4 kbytes 0010 16 kbytes 0011 64 kbytes 0100 256 kbytes 0101 1 mbyte 0110 4 mbytes 0111 16 mbytes 1000 64 mbytes 1001 256 mbytes all others?reserved sx, sw, sr supervisor execute, write, and read permission bits ux, uw, ur user execute, write, and read permission bits wimge memory/cache attributes (write-through, cache-inhibit, memory coherence required, guarded, endian) u0?u3 user attribute bits?used only by software iprot invalidation protection vle vle page indicator table 152. tlb entry bit fields for e200z3 (continued) field description
UM0434 memory management unit 201/391 the search occurs if a tlb invalidate or replacement removes the entry between the time the exception is recognized and when the tlbsx is executed. the supervisor instructions tlbre , tlbwe , tlbsx , tlbivax , and tlbsync are fully described in the eref . tlb read entry ( tlbre )?causes contents of the tlb entry specified by mas0[tlbsel,esel]) to be placed into mas1?mas3. table 156 describes how mas fields are updated. tlb write entry ( tlbwe )?causes the contents of certain fields within the mas1, mas2, and mas3 to be writ ten into the tlb entry spec ified by mas0[tlbsel,esel]. table 156 describes how mas fields are updated. tlb search indexed ( tlbsx )?updates the mas registers conditionally based on success or failure of a tlb lookup. the lookup is controlled by an effective address provided by r b as specified in the instruction encoding, and by mas6[sas,spid]. the values placed into mas0?mas3 differ depending on the success of the search. table 156 describes how mas fields are updated. tlb invalidate ( tlbivax )?invalidates tlb entries that correspond to the virtual address calculated by this instructio n. the address is detailed in table 153 . no other information except for that shown in table 153 is used for the invalidation (as and tid values are ignored). additional information about the targeted tlb entries is encoded in two of the lower bits of the effective address calculated by the tlbivax . ea[0?19] are used to perform the tlbivax invalidation of tlb1. t tlb synchronize ( tlbsync )?treated as a privileged no-op by the e200z3. 7.5 tlb operations this section describes how th e software (with some hardware assistance) maintains tlb1. table 153. tlbivax ea bit definitions bits field 0?19 ea[0?19] 20?27 reserved (1) 1. these bits should be zero for futu re compatibility. they are ignored. 28 tlbsel (1 = tlb1). should be set, for future compatibility and to ensure that tlb1 is targeted by the invalidate. 29 inv_all. if set, indicates that the invalidate operation needs to completely invalidate all tlb1 entries that are not marked as invalidation protected (iprot = 1) 30?31 reserved 1
memory management unit UM0434 202/391 7.5.1 translation reload the tlb reload function is performed in software with some hardware assistance. this hardware assistance consists of the following: five 32-bit mmu assist registers (mas0?mas4, mas6) for support of the tlbre , tlbwe , and tlbsx tlb management instructions. loading of mas0?mas2 based upon defaults in mas4 for tlb miss exceptions. this automatically generates most of the tlb entry. loading of the data exception address register (dear) with the ea of the load, store, or cache management instruction that caused an alignment, data tlb miss, or data storage interrupt. the tlbwe instruction. when tlbwe is executed, the new tlb entry contained in mas0? mas2 is written into the tlb. 7.5.2 reading the tlb the tlb array can be read by first writing the necessary information into mas0 using mtspr and then executing the tlbre instruction. to read an entr y from tlb1, mas0[tlbsel] must be set to 01 and mas0[esel] must be set to point to the desired entry. after tlbre executes, mas1?mas3 are updated with the data from the selected tlb entry. see chapter 7.4: software interface and tlb instructions on page 200 .? 7.5.3 writing the tlb the tlb1 array can be written by first writin g the necessary information into mas0?mas3 using mtspr and then executing the tlbwe instruction. to write an entry into tlb1, the tlbsel field in mas0 must be se t to 01, and the esel bits in mas0 must be set to point to the desired entry. when the tlbwe instruction is executed, the tlb entry information stored in mas1?mas3 is written into the selected tlb entry. see chapter 7.4: soft ware interface and tlb instructions on page 200 .? 7.5.4 searching the tlb tlb1 can be searched using a tlbsx by first writing the necessary information into mas6. the tlbsx instruction searches using epn[0?19] from the gpr selected by the instruction, sas (search as bit) in mas6, and spid in mas6. if the search is successful, the given tlb entry information is loaded into mas0?mas3. the valid bit in mas1 is used as the success flag. if the search is successful, the valid bit in mas1 is set; if unsuccessful, it is cleared. the tlbsx instruction is useful for finding the tlb entry that caused a data or instruction storage interrupt. see chapter 7.4: software interface and tlb instructions on page 200 .? 7.5.5 tlb coherency control the e200z3 core provides the ability to invalidate a tlb entry as described in the book e powerpc architecture. the tlbivax instruction invalidates local tlb entries only. no broadcast is performed, as no hardware -based coherency support is provided. the tlbivax instruction invalidates by effective addr ess only. this means that only the tlb entry?s epn bits are used to determine if the tlb entry should be invalidated. therefore, a single tlbivax can invalidate multiple tlb entries, because the as and tid fields of the entries are ignored.
UM0434 memory management unit 203/391 7.5.6 tlb miss exception update when a tlb miss exception occurs, mas0?mas3 are updated with the defaults specified in mas4 and the as and epn[0?19] of the access that caused the exception. in addition, the esel bits are updated with the re placement entry value. this se ts up all the tlb entry data necessary for a tlb write except for the rpn[0?19], the u0?u3 user bits, and the ux/sx/uw/sw/ur/sr permission bits, all of which are stored in mas3. thus, if the defaults stored in mas4 are applicable to the tlb entry to be loaded, the tlb miss exception handler only has to update mas3 through mtspr before executing tlbwe . if the defaults are not applicable to the tlb entry being loaded, the tlb miss handler must update mas0? mas2 before performing the tlb write. see table 156 for more details on the automatic updates to the mas registers on exceptions. 7.5.7 tlb load on reset during reset, all tlb entries except entry 0 are automatically invalidated by the hardware. tlb entry 0 is also loaded with the default values in table 154 . 7.6 mmu configuration and control registers information about the configuration for a given mmu implementation is available to system software by reading the contents of the mmu configuration sprs. these sprs describe the architectural version of the mmu, the number of tlb arrays, and the characteristics of each tlb array. additionally, there are a number of mmu control and assist registers summarized in chapter 4.16.4: mmu assist registers (mas0?mas4, mas6) on page 91 .? table 154. tlb entry 0 values after reset field reset value comments valid 1 entry is valid. ts 0 address space 0 tid[0?7] 0x00 tid value for shared (global) page epn[0?19] p_rstbase[0:19] value page address present on p_rstbase[0:19] . see chapter 9: external core complex interfaces .? rpn[0?19] p_rstbase[0:19] value page address present on p_rstbase[0:19] . see chapter 9: external core complex interfaces .? size[0?3] 0001 4kb page size sx/sw/sr 111 full supervisor mode access allowed ux/uw/ur 111 full user mode access allowed wimg 0100 cache-inhibited, non-coherent e p_rst_endmode value value present on p_rst_endmode . see chapter 9: external core complex interfaces .? u0?u3 0000 user bits iprot 1 page is protected from invalidation. vle p_rst_vlemode value value present on p_rst_vlemode signal . see table 167 for more information.
memory management unit UM0434 204/391 7.6.1 mmu configurati on register (mmucfg) mmucfg provides configuration information for the mmu supplied with this version of the e200z3 cpu core. see chapter 4.16.2: mmu configuration register (mmucfg) .? 7.6.2 tlb0 and tlb1 configuration registers tlb0cfg and tlb1cfg provide configuration information for the mmu tlbs supplied with this version of the e200z3 cpu core. see chapter 4.16.3: tlb configuration registers (tlbncfg) .? 7.6.3 data exception ad dress register (dear) dear, described in chapter : data exception address register (dear) ,? is loaded with the effective address of the data access that results in an alignment, data tlb miss, or data storage interrupt. 7.6.4 mmu control and stat us register 0 (mmucsr0) mmucsr0, shown in chapter 4.16.1 ,? controls the state of the mmu. 7.6.5 mmu assist registers (mas) the e200z3 uses mas0?mas4 and mas6 sprs to facilitate readin g, writing, and searching the tlbs. the e200z3 does not implement mas5, because the tlbsx instruction only searches based on a single spid value. mas registers are described in chapter 4.16.4 .? mas registers summary the fields of the mas registers are summarized in table 155 . table 155. mmu assist registers summary 32 33 34 35 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 46 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 58 59 60 61 62 63 mas 0 ? tlbse l ?esel ? nv mas 1 vali d ipro t ?tid? t s tsiz ? mas 2 epn ? vle w i m g e mas 3 rpn ? u 0 u 1 u 2 u 3 ux sx u w s w u r sr mas 4 ? tbsel d ? tidseld ? tsized ? vle d w d id m d g d ed mas 6 ? spid ? sa s
UM0434 memory management unit 205/391 mas register updates table 156 details the updates to each mas register field for each update type. 7.7 effect of hardware debug on mmu operation hardware debug facilities use normal cpu inst ructions to access register and memory contents during a debug session. if desired, the debug firmware may disable the translation process and may substitute default values for the access protection (ux, ur, uw, sx, sr, sw) bits and values obtained from the once control register for page attribute (w,i,m,g,e) bits normally provided by a matching tlb entry. in addition, no address translation is performed; instead, a 1:1 mapping of effective-to-real addresses is performed. when disabled during the debug, no tlb miss or tlb access protection related dsi conditions occur. if there is a need for the debugger to use normal translation process, the mmu may be left enabled in the once ocr, and normal translation (i ncluding the possibility of a tlb miss or dsi) remains in effect. see: chapter : once control register (ocr) ,? for details on controlling mmu operation during debug sessions. table 156. mmu assist register field updates bit/field mas affected itlb/dtlb error tlbsx hit tlbsx miss tlbre tlbwe isi/ds i tlbsel 0 tlbseld ?01? tlbseld nc (1) nc nc esel 0 nv matched entry nv nc nc nc nv 0 nc nc nc nc nc nc valid 1 1 1 0 v(array) nc nc iprot 1 0 matched iprot 0 iprot(array) nc nc tid[0?7] 1 tidseld (pid0,tidz) tid(array) spid tid(array) nc nc ts 1 msr(is/ds) sas sas ts(array) nc nc tsize[0?3] 1 tsized tsize(arr ay) tsized tsize(array) nc nc epn[0?19] 2 i/d epn epn(array) tlbsx epn epn(array) nc nc wimge 2 default values wimge(array) default values wimge(array) nc nc rpn[0?19] 3 zeroed rpn(array) zeroed rpn(array) nc nc access (permiss + u0?u3) 3 zeroed access(array) zeroed access(array) nc nc tlbseld 4 nc nc nc nc nc nc tidseld[0?1] 4 nc nc nc nc nc nc tsized[0?3] 4 nc nc nc nc nc nc default wimge 4 nc nc nc nc nc nc spid 6 pid0 nc nc nc nc nc sas 6 msr(is/ds) nc nc nc nc nc 1. nc?no change
instruction pipeline a nd execution timing UM0434 206/391 8 instruction pipeline and execution timing this chapter describes the instruction pipeline and instruction timing information. the core is partitioned into the following systems: instruction unit control unit integer unit load/store unit core interface 8.1 overview of operation figure 12 shows a block diagram of the e200z3 core. the instruction fetch unit prefetches instructions from memory into the instruction buffers. the decode unit decodes each instruction and generates information needed by the branch and execution units. branch target instructions are written into the branch target prefetch buffers; sequentially prefetched instructions are written in to the instruction buffers. the instruction fetch unit attempts to supply a constant stream of instructions to the execution pipeline. it does so by decoding and detecting branches early in the instruction buffer, making branch predictions, and prefetching their branch targets into the instruction buffer. by prefetching the branch targets early, some or all of the branch pipeline bubbles can be hidden from the execution pipeline. the instruction issue unit attempts to issue a single instruction each cycle to one of the execution units. source operands for each of the instructions are provided from the gprs or from the operand feed-forward muxes. data or resource hazards may create conditions that stall instruction issue until the hazard is eliminated. the execution units write the result of a finished instruction onto the proper result bus and into the destination registers. the writeback logic retires an instruction when the instruction has finished execution. up to two results can be simultaneously written.
UM0434 instruction pipeline and execution timing 207/391 figure 12. e200z3 block diagram 8.1.1 control unit the control unit coordinates the instruction fetc h unit, branch unit, instruction decode unit, instruction issue unit, completion unit, and exception handling logic. 8.1.2 instruction unit the instruction unit controls the flow of instructions to the instruction buffers and decode unit. six prefetch buffers allow the instruction unit to fetch instructions ahead of actual execution, and serve to decouple memory and the execution pipeline. cpu load/ data memory address store unit instruction unit branch unit pc unit instruction buffer gpr cr spr multiply unit data bus interface unit control 32 64 n once/nexus interface control data ( mtspr/mfspr ) integer execution unit external spr ctr xer lr data address instruction bus interface unit control 32 64 n control logic control logic management unit
instruction pipeline a nd execution timing UM0434 208/391 8.1.3 branch unit the branch unit contains an eight-entry branch target buffer (btb) to accelerate execution of branch instructions. untaken conditional branches execute in a single clock. branches with successful target prefetching have an effective execution time of one clock cycle. all other taken branches have an execution time of two clocks. 8.1.4 instruction decode unit the decode unit includes the instruction buffers. a single instruction can be decoded each cycle. the major functions of the decode logic are as follows: opcode decoding to determine the instruction class and resource requirements for each instruction being decoded. source and destination register dependency checking. execution unit assignment. determine any decode serializations and inhibit subsequent instruction decoding. the decode unit operates in a single processor clock cycle. 8.1.5 exception handling the exception handling unit includes logic to handle exceptions, interrupts, and traps. 8.2 execution units the core data execution units consist of the integer unit and the load/store unit. included in the execution units section are the general purpose registers (gprs). instructions with data dependencies begin execution when all such dependencies are resolved. 8.2.1 integer execution unit the integer execution unit is used to process arithmetic and logical instructions. adds, subtracts, compares, count leading zeros, shifts, and rotates execute in a single cycle. multiply instructions have a late ncy and throughput rate of 1 cycle. divide instructions have a variable latency (6?16 cycles) depending on the operand data. the worst case integer divide requires 16 cycles. while the divide is running, the rest of the pipeline is unavailable for additiona l instructions (blocking divide). 8.2.2 load/store unit the load/store unit executes instructions that move data between the gprs and the memory subsystem. a load followed by a dependent instruction does not incur any pipeline stall, except when the dependent instruction is a load/store instruction, and the latter instruction is using the previous load data for its effective address (ea) calculation. loads, when free of the above ea calculation dependency, execute with a maximum throughput of one per cycle and one-cycle latency. store data can be fed forward from an immediately preceding load with no stall.
UM0434 instruction pipeline and execution timing 209/391 8.3 instruction pipeline the four-stage processor pipe line consists of stages for instruction fetch (ifetch), instruction decode (decode), execution (e xecute), and result writeback (wb). for memory operations, the ea generation occurs in the decode stage, while the memory access occurs in the execute stage. the processor also contains an instruction prefetch buffer to allow buffering of instructions prior to the decode stage. instructions proceed from this buffer to the instruction decode stage by entering the instruction decode register ir. figure 13. pipeline diagram 8.3.1 description of pipeline stages the fetch pipeline stages retrieve instructions from the memory system and determine where the next instruction fetch is performed. up to two instructions every cycle are sent from memory to the instruction buffers. the decode stage decodes instructions and pe rforms dependency checking. simple integer instructions complete execution in the execute stage of the pipeline. execution of load/store instructions is pipelined. the ea calculations for load/store instructions are performed in the decode stage. this ea is driven out to the data memory in the same stage. the actual memory access occurs in the execute stage. load-to-use dependencies do not incur pipeline bubbles except when the dependent instruction is a load or store instruction, and the latter instruction is dependent on its previous load data for ea calculation. if an alu instruction is dependent on a load table 157. pipeline stages stage description ifetch1 instruction fetch from memory decode/ea instruction decode/register read/operand forwarding/ea calculation execute/mem instruction execution/memory access wb write back to registers ifetch decode execute writeback i1 i2 ifetch decode/ea calc/drive address memory access/drive data back l1 l2 l1 l2 l1 l2 writeback l1 l2 simple instruction load/store instruction i1 i2 i1 i2 i1 i2
instruction pipeline a nd execution timing UM0434 210/391 instruction, the data is fed directly into the alu for execution. no pipeline bubble is incurred in this case. multiply instructions require one clock to execute. all conditi on-setting instructions complete in the execute stage of the pipeline. feed-forwarding allows the result of one instruction to be made available as the source operand(s) of a subsequent instruction so th at data-dependent instructions can execute without waiting for previous instruct ions to write back their results. 8.3.2 instruction buffers the e200z3 contains a set of instruction buffers that supply instructions into the instruction register (ir) for decoding. instruction prefetches request a 64-bit double word and the buffer is filled with a pair of instructions at a time, except for the case of a change of flow fetch where the target is to the second (odd) word. in that case, only a 32-bit prefetch is performed to load the instruction buffer. this 32-bit fetch may be immediately follo wed by a 64-bit prefetch to fill slots 0 and 1 in the event that the branch is resolved to be taken. in normal sequential execution, instructions are loaded into the ir from slot 0, and as a pair of slots are emptied, they are refilled. whenever a pair of sl ots is empty, a 64-bit prefetch is initiated that fills the earliest empty slot pairs beginning with slot 0. if the instruction buffer empties, instruction issue stalls, and th e buffer is refilled. the first returned instruction is forwarded directly to the ir. figure 14. instruction buffers slot0 decode . . mux ir data 0:63 slot1 slot2 slot3
UM0434 instruction pipeline and execution timing 211/391 hid0[bpred] controls if prediction is made for forward or backward branches (or both). to resolve branch instructions and improve the accuracy of branch predictions, the e200z3 implements a dynamic branch prediction mechanism using an 8-entry branch target buffer (btb), a fully associative address cache of branch target addresses. the btb is purposefully small to reduce cost and power. it is expected to accelerate the execution of loops with some potential change of flow within the loop body. an entry is allocated in the btb whenever a branch resolves as taken and the btb is enabled. branches that have not been allocated are always predicted as not taken. btb entries are allocated on taken branches using a fifo replacement algorithm. each btb entry holds a 2-bit branch history counter, whose value is incremented or decremented on a btb hit, depending on whether the branch was taken. the counter can assume four different values: strongly taken, weakly taken, weakly not taken, and strongly not taken. a branch is predicted as taken on a hit in the btb with a counter value of strongly or weakly taken. in this case, the target address c ontained in the btb is used to redirect the instruction fetch stream to the target of the branch prior to the branch reaching the instruction decode stage. in the case of a mispredicted branch, the instruction fetch stream returns to the sequential instruction stream after the branch has been resolved. when a branch is predicted taken and the branch is later resolved (in the branch decode stage), the value of the counter is updated. a branch whose counter indicates weakly taken is resolved as taken, the counter increments so that the prediction becomes strongly taken. if the branch resolves as not taken, the prediction changes to weakly not-taken. the counter saturates in the strongly taken states when the prediction is correct. the e200z3 does not implement the static branch prediction that is defined by the powerpc architecture. the bo prediction bit in branch encodings is ignored. dynamic branch prediction is enabled by setting bucsr[bpen]. clearing bucsr[bpen] disables dynamic branch prediction, in which case the e200z3 predicts every branch as not taken. additional control is available in the hid0[bpred] field to control whether forward or backward branches (or both) are candidates for entry into the btb, and thus for branch prediction. once a branch is in the btb, hid0[bpred] has no further effect on that entry. the btb uses virtual addresses for performing tag comparisons. on allocation of a btb entry, the ea of a taken branch, along with the current instruction space (as indicated by msr[is]) is loaded into the entry, and the counter value is set to weakly taken. the current pid value is not maintained as part of the tag information. the btb is automatically flushed when the current pid value is updated by an mtspr pid instruction. software is otherwise responsible for maintaining coherency in the btb when a change in effective-to-real (virtual-to-physical) address mapping is changed. this is supported by the bucsr[bbfi] control bit.
instruction pipeline a nd execution timing UM0434 212/391 figure 15. branch target buffer 8.3.3 single-cycle instru ction pipeline operation sequences of single-cycle execution instructions follow the flow in figure 16 . instructions are issued and completed in program order. most arithmetic and logical instructions fall into this category. figure 16. basic pipeline flow, single-cycle instructions 8.3.4 basic load and store instruction pipeline operation the ea calculations for load and store instructions are performed in the decode stage. the memory access occurs in the execution stage. if a load instruction is followed by a dependent alu instruction, the load data is driven from the memory in the mem stage and feed-forwarded into the dependent alu instruction in the following cycle. as a result, there is no load-to-use pipeline bubble. figure 17 shows the instruction flow for a load instruction followed by a dependent add instruction. figure 17. a load followed by a dependent add instruction tag data is counter counter counter 3 is = instruction space ... ... ... ... 2 is 1 branch addr[0:29] branch addr[0:29] branch addr[0:29] target address[0:29] target address[0:29] target address[0:29] is entry entry entry entry 0 ifetch decode execute first inst. time slot ffwd/wb second instruction third instruction ifetch decode execute ffwd/wb ifetch decode execute ffwd/wb dec/ea mem first load instruction time slot mem second add instruction decode execute mem ifetch ifetch feedforward
UM0434 instruction pipeline and execution timing 213/391 back-to-back load/store instructions are executed in a pipelined fashion, provided that their ea calculations are not dependent on their previous load instructions. figure 18 shows the basic pipeline flow for two back-to-back load instructions. in this case, the second load does not depend on its previous load data for its ea calculation. notice that the memory access of the first load instruction overlaps in time with the ea calculation of the second load instruction. figure 18. back-to-back load instructions when a load is followed by a load or a store instruction that depends on the first load data for ea calculation, a pipeline stall is incurred. figure 19 shows the instruction flow for a load instruction followed by a dependent store instruction through ea calculation. the second store instruction in this case is dependent on the first load instruction for its ea calculation. figure 19. a load followed by a dependent store instruction a store instruction that depends on its previous load for its stored data, does not stall the pipeline. 8.3.5 change-of-flow inst ruction pipeline operation a branch instruction takes either one or 2 cycles to execute. simple change of flow instructions require 2 cycles to refill the pi peline with the target instruction for taken branches and branch and link instructions with no prediction. for branch-type instructions, in some situations, this 2-cycle timing may be reduced by performing the target fetch speculatively while the branch instruction is still being fetched into the instruction buffer. the branch target address is obtained from the btb. the resulting branch timing reduces to a single clock when the target fetch is initiated early enough and the branch is taken. figure 20 shows basic pipeline flow for branch instructions. dec / ea mem first load instruction time slot wb second load instruction dec / ea mem wb ifetch ifetch decode execute first load instruction time slot wb second store instruction decode ea calc mem ifetch ifetch wb feedforward
instruction pipeline a nd execution timing UM0434 214/391 figure 20. basic pipeline flow, branch instructions figure 21 shows basic pipeline flow for branch speculation. figure 21. basic pipeline flow, branch speculation 8.3.6 basic multi-cycle i nstruction pipeline operation the divide instructions and the load and store mu ltiple instructions requ ire multiple cycles in the execute stage. figure 22. basic pipeline flow, multi-cycle instructions instructions must complete and write back resu lts in order. a single cycle instruction that follows a multi-cycle instruction must wait for co mpletion of the multi-cycle instruction prior to its writeback in order to meet the in-order requirement. result feed-forward paths are provided so that execution may c ontinue prior to result writeback. 8.3.7 additional examples of instruct ion pipeline operati on for load & store figure 23 shows an example of pipelining two non?data-dependent load or store instructions with a following data-dependent single -cycle instruction. while the first load or store begins accessing memory in the mem stage, the next load or store can be calculating a new ea in the dec/ea stage. the add in this example does not stall despite a data dependency on its preceding load instruction. decode exec br inst. time slot target instruction exec wb . . . ifetch slot0 ifetch decode ifetch decode branch instruction time slot target instruction slot0 decode exec (speculative fetch) btb hit tfetch slot0 . . . exec ifetch decode wb load/store multiple word/divide instruction time slot exec0 execn . . .
UM0434 instruction pipeline and execution timing 215/391 figure 23. pipelined load/store instructions for memory access instructions, wait states may occur. this causes a following memory access instruction to stall since the following memory access may not be initiated as shown in figure 24 . here, the first ld/st instruction incurs a wait state on the bus interface, causing succeeding instruct ions to stall. figure 24. pipelined load/store instructions with wait-state 8.3.8 move to/from spr inst ruction pipeline operation most mtspr and mfspr instructions are treated like single -cycle instructions in the pipeline and do not cause stalls. exceptions are for the msr, the debug sprs, the embedded floating-point apus, and mmu sprs, which do cause stalls. figure 25 through figure 25 show examples of mtspr and mfspr instruction timing. figure 25 applies to the debug sprs and the efpu?s efscr. these instructions do not begin execution until all previous instructions have finished their execute stage. if a multicycle instruction precedes an mfspr or mtspr instruction, the mfspr or mtspr instruction does not begin exec ution until the preceding multicycle instruction moves into the writeback stage as shown in figure 25 . in addition, execution of subsequent instructions stalls until the mfspr and mtspr instructions complete. first load/store instruction (no wait) time slot second load/store instruction (no wait) add instruction ifetch wb dec/ea ifetch mem wb dec/ea wb ifetch execute dec mem first load/store instruction (with wait) time slot second load/store instruction (no wait) add instruction ifetch stall (wait) dec/ea wb ifetch stall mem dec / ea wb execute ifetch dec stall wb mem
instruction pipeline a nd execution timing UM0434 216/391 figure 25. mtspr, mfspr instruction execution?(1) figure 26 applies to the mtmsr, wrtee , and wrteei instructions. execution of subsequent instructions stalls until th ese instructions writeback. figure 26. mtmysr, wrtee, wrteei instruction execution access to mmu sprs stalls until all outsta nding bus accesses comp lete and the mmu is idle ( p_[i,d]_cmbusy negated) to allow an access window where no translations or cache cycles are required. figure 27 shows an example where an outstanding bus access delays mtspr / mfspr execution until the bus becomes idle. processor access requests are held off during execution of an mmu spr instruction. a subsequent access request may be generated in the wb cycle. this same protocol applies to mmu management instructions (such as tlbre , tlbwe , etc.) as well as to the dcrs. time slot mtspr , mfspr dec exe1 ifetch wb previous instruction (multicycle) dec exe ifetch wb dec stall ifetch exe wb next instruction exen . . . . . . . . . stall stall time slot mtmsr , wrtee , wrteei dec exe ifetch previous instruction dec exe ifetch wb dec stall ifetch exe wb next instruction wb
UM0434 instruction pipeline and execution timing 217/391 figure 27. dcr, mmu mtspr, mfspr, an d mmu management in struction execution 8.4 stalls caused by accessing sprs an mfspr instruction preceded by an mtspr instruction cannot be issued until the mtspr completes. 8.5 instruction serialization the core requires three types of serialization: completion serialization. a comp letion-serialized instruction is held for execution until all prior instructions have completed. the instruction executes when it is next to complete in program order. results from these instructions are not available for or forwarded to subsequent instructions unt il the instruction comp letes. the following instructions are completion-serialized: ? instructions that access or modify system control or status registers? mcrxr , mtmsr , wrtee , wrteei , mtspr , mfspr (except to ctr/lr) ? instructions that manage tlbs ? instructions defined by the architecture as context or execution synchronizing: isync , msync , rfi , rfci , rfdi , and sc dispatch (decode/issue) serialization. some instructions are dispatch-serialized by the core. an instruction that is dispatch-serialized prevents the next instruction from decoding until all instructions up to and including the dispatch-serialized instruction time slot dec exe wb ifetch ... ... single-cycle instruction dec stall ifetch stall exe wb next instruction p_[i,d]_treq_b p_[i,d]_tbusy[0]_b p_[i,d]_ta_b p_rd_spr, p_wr_spr p_[i,d]_cmbusy mtspr , mfspr dec stall ifetch stall exe wb
instruction pipeline a nd execution timing UM0434 218/391 completes. the isync , mbar , msync , rfi , rfci , rfdi , and sc instructions are dispatch- serialized. refetch serialization. refetch-serialized instructions inhibit dispatching of subsequent instructions and force a pipeline refill to refetch subsequent instructions after completion. these include the following: ? the context synchronizing instruction isync ?the rfi , rfci , rfdi , and sc instructions. 8.6 interrupt recognition and exception processing figure 28 shows timing for interrupt recognition and exception processing overhead. this example shows best-case response timing when an interrupt is received and processed during execution of a sequence of single-cycle instructions. figure 28. interrupt recognition and handler instruction execution time slot ifetch exe wb dec single cycle instructions dec/ -- ifetch -- p_extint_b final sample point p_iack ifetch exe wb dec 1st instruction of handler 12345678910 e c_excp_detected* update_esr* update_msr* * - internal operations oldpc_-> srr0 * oldmsr_-> srr1 * abort
UM0434 instruction pipeline and execution timing 219/391 figure 29 below, shows timing for interrupt recognition and exception processing overhead. this example shows best-case response timing when an interrupt is received and processed during execution of a load or store instruction. the fetch for the handler is delayed until completion of the load or store, regardless of the number of wait-states. figure 29. interrupt recog. & handler instruction exe-load/store in progress time slot dec/ea wait wait mem load/store instructions ifetch abort -- dec -- p_extint_b final sample point p_iack ifetch exe wb dec first instruction of handler 12345678910 ifetch stall stall dec/ stall ec_excp_detected* oldpc_-> srr0 * oldmsr_-> srr1 * update_esr* update_msr* * internal operations 11 wb abort
instruction pipeline a nd execution timing UM0434 220/391 figure 30 below, shows timing for interrupt recognition and exception processing overhead. this example shows best-case response timing when an interrupt is received and processed during execution of a multicycle interruptible instruction. figure 30. interrupt recog. & handler instruction exe-multi-cycle instruction abort 8.7 instruction timings table shows instruction timing for various instru ction classes. pipelin ed instructions are shown with cycles of total latency and throughput. divide instructions are not pipelined and block other instructions from executing during divide execution. load/store multiple instructio n cycles are represented as a fixed number of cycles plus a variable number of cycles where ?n? is the nu mber of words accessed by the instruction. additionally, cycle times marked with an ampe rsand (&) require additional cycles due to serialization. time slot next instruction ifetch exe abort dec -- -- multi-cycle interruptible ifetch abort -- dec -- 12345678910 p_extint_b final sample point p_iack ifetch exe wb dec first instruction of handler e c_excp_detected* oldpc_-> srr0 * oldmsr_-> srr1 * update_esr* update_msr* * internal operations instruction
UM0434 instruction pipeline and execution timing 221/391 instruction class cycle counts class of instructions latency throughput special notes integer: add , sub , shift , rotate , logical , cntlzw 11 integer: compare 1 1 branch 2/1 2/1 branches take between 1 and 2 cycles to execute. multiply 1 1 divide 6?16 6?16 data dependent timing cr logical 1 1 loads (non-multiple) 1 1 load multiple 1 + n/2 (max) 1 + n/2 (max) timing depends on n and address alignment. stores (non-multiple) 1 1 store multiple 1 + n/2 (max) 1 + n/2 (max) timing depends on n and address alignment. mtmsr , wrtee , wrteei 2& 2 mcrf 11 mfspr , mtspr 2& 2& applies to debug sprs, optional unit sprs mfspr , mfmsr 1 1 applies to internal, non-debug sprs mfcr , mtcr 11 rfi , rfci , rfdi 3- sc 3- tw , twi 3 - trap taken timing
instruction pipeline a nd execution timing UM0434 222/391 table 158 shows detailed timing for each instruction mnemonic along with serialization requirements. as this table shows, the vle instructions have the same latencies and serialization as their equivalents in the powe rpc architecture. those instructions are listed by their root mnemonic. table 158. instruction timing by mnemonic mnemonic latency serialization comments addc [ o ][ . ]1none adde [ o ][ . ]1none addi , e_addi [ . ], e_add16i , e_add2i. , se_addi 1 none addic [ . ], e_addic[.] 1none addis , e_add2is 1none addme [ o ][ . ]1none addze [ o ][ . ]1none add [ o ][ . ], se_add 1none andc [ . ], se_andc 1none andi. , e_andi [ . ], e_and2i. , se_andi 1none andis. , e_and2is. 1none and [ . ], se_and [ . ] 1none bcctr [ l ]2none bclr [ l ]2none bc [ l ][ a ], e_bc , e_bcl , se_bc , se_bclri , se_bctr , se_bctrl 2/1 none b [ l ][ a ], e_b , e_bl , se_b , se_bl , se_blr , se_blrl , se_bgeni 2/1 none cmp , e_cmph , e_cmph16i , se_cmp 1none cmpi , e_cmphl , e_cmphl16i , se_cmph , se_cmphl 1none cmpl , e_cmpi , e_cmp16i , se_cmpi 1none cmpli , e_cmpli , e_cmpl16i , se_cmpl , se_cmpli 1none cntlzw [ . ] 1none crand , e_crand 1none crandc , e_crandc 1none creqv , e_creqv 1none crnand , e_crnand 1none crnor , e_crnor 1none cror , e_cror 1none crorc , e_crorc 1none
UM0434 instruction pipeline and execution timing 223/391 crxor , e_crxor 1none divwu [ o ][ . ] 6?16 none divw [ o ][ . ] 6?16 none with early-out capability timing is data dependent eqv [ . ]1none extsb [ . ], se_extsb 1none extsh [ . ], se_extsh 1none e_li , e_lis , se_li 1none the uisa defines li as a simplified, mnemonic for addi . e_rlw , e_rlwi 1none isel 1none isync , se_isync 3 refetch plus additional synchronization time lbz , e_lbz , se_lbz 1 none aligned lbzu , e_lbzu 1 none aligned lbzux , e_lha 1 none aligned lbzx , e_lhau 1 none aligned lha , e_lhz 1 none aligned lhau , e_lhzu 1 none aligned lhaux 1 none aligned lhax 1 none aligned lhbrx 1 none aligned lhz , se_lhz 1 none aligned lhzu 1 none aligned lhzux 1 none aligned lhzx 1 none aligned lmw , e_lmw 1 +(n/2) none lwarx 1none lwbrx 1 none aligned lwz , e_lwz , se_lwz 1 none aligned lwzu , e_lwzu 1 none aligned table 158. instruction timing by mnemonic (continued) mnemonic latency serialization comments
instruction pipeline a nd execution timing UM0434 224/391 lwzux 1 none aligned lwzx 1 none aligned mbar 1 completion plus additional synchronization time mcrf , e_mcrf 1none mcrxr 1 completion mfcr 1none mfmsr 1none mfspr (except, debug, mmu), se_mfctr , se_mflr 1none mfspr , (debug, mmu) 3 completion plus additional synchronization time msync 1 completion plus additional synchronization time mtcrf 2none mtmsr 2 completion plus additional synchronization time mtspr , (debug, mmu), se_mtctr , se_mtlr 2 completion plus additional synchronization time mtspr , (except, debug, mmu) 1 none mulhwu [ . ] 1none mulhw [ . ] 1none mulli , e_mulli , e_mull2i 1none mullw [ o ][ . ], se_mullw 1none nand [ . ] 1none neg [ o ][ . ], se_neg 1none nop , (ori , r0r00) 1none nor [ . ], e_ori [ . ], e_or2i , e_or2is 1none orc [ . ] 1none ori 1none oris 1none or [ . ], se_or 1none rfci 3 refetch table 158. instruction timing by mnemonic (continued) mnemonic latency serialization comments
UM0434 instruction pipeline and execution timing 225/391 rfdi 3 refetch rfi 3 refetch rlwimi [ . ], e_rlwimi 1none rlwinm [ . ], e_rlwinm 1none rlwnm [ . ]1none sc 3 refetch se_bmski 1 none se_bseti 1none se_btsti 1none se_extzb , se_extzh 1none se_mfar 1none se_mr 1 none the uisa defines mr as a simplified, mnemonic for or . se_mtar 1none se_not 1none slw [ . ], se_slw , e_slwi , se_slwi 1none srawi [ . ], se_srawi 1none sraw [ . ], se_sraw 1none srw [ . ], se_srw , e_srwi , se_srwi 1none stb , e_stb , se_stb 1 none aligned stbu , e_stbu 1 none aligned stbux 1 none aligned stbx 1 none aligned sth , sth , e_sth , se_sth , e_sthu 1 none aligned sthbrx 1 none aligned sthu 1 none aligned sthux 1 none aligned sthx 1 none aligned stmw , e_stmw 1 + (n/2) none stw , e_stw , se_stw 1 none aligned stwbrx 1 none aligned stwcx. 1none table 158. instruction timing by mnemonic (continued) mnemonic latency serialization comments
instruction pipeline a nd execution timing UM0434 226/391 8.7.1 spe and embed ded floating-point in struction timing the tables in this section show instruction timing for spe and embedded floating-point apu instructions. pipelined instructions are shown with cycles of total latency and throughput cycles. divide instructions are not pipelined and block other instructions from executing during divide execution. instruction pipelining is affected by the possibilit y of a floating-point inst ruction generating an exception. a load or store clas s instruction that follows an spe fpu instruction stalls until it can be ensured that no previous instruction can generate a floating-point exception. this determination is based on which floating-point exception enable bits are set (finve, fovfe, funfe, fdbze, and finxe) and at what point in the fpu pipeline an exception can be guaranteed to not occur. invalid input operands are detected in the first stage of the pipeline, while underflow, overflow, and inexac tness are determined later in the pipeline. best overall performance occurs when either floating-point exceptions are disabled, or when load and store class instructions are scheduled such that previous floating-point instructions have already resolved the poss ibility of exceptional results. spe integer simple instructions timing instruction timing for spe integer simple instructions is shown in table 159 . the table is sorted by opcode. these instructions are issued as a pair of operations. stwu , e_stwu 1 none aligned stwux 1 none aligned stwx 1 none aligned subfc [ o ][ . ]1none subfe [ o ][ . ]1none subfic , e_subfic [ . ], se_subi [ . ]1none subfme [ o ][ . ]1none subfze [ o ][ . ]1none subf [ o ][ . ], se_subf , se_sub 1none tw 3none twi 3none wrtee 2 completion wrteei 2 completion xori , e_xori [ . ]1none xoris 1none xor [ . ]1none table 158. instruction timing by mnemonic (continued) mnemonic latency serialization comments
UM0434 instruction pipeline and execution timing 227/391 table 159. timing for integer simple instructions instruction latency throughput comments brinc 11 evabs 11 evaddiw 11 evaddw 11 evand 11 evandc 11 evcmpeq 11 evcmpgts 11 evcmpgtu 11 evcmplts 11 evcmpltu 11 evcntlsw 11 evcntlzw 11 eveqv 11 evextsb 11 evextsh 11 evmergehi 11 evmergehilo 11 evmergelo 11 evmergelohi 11 evnand 11 evneg 11 evnor 11 evor 11 evorc 11 evrlw 11 evrlwi 11 evrndw 11 evsel 11 evslw 11 evslwi 11 evsplatfi 11 evsplati 11 evsrwis 11 evsrwiu 11
instruction pipeline a nd execution timing UM0434 228/391 spe load and store instruction timing instruction timing for spe load and store instructions is shown in table 160 . the table is sorted by opcode. actual timing depends on alignment; the table indicates timing for aligned operands. evsrws 11 evsrwu 11 evsubfw 11 evsubifw 11 evxor 11 table 160. spe load and st ore instruct ion timing instruction latency throughput comments evldd 11 evlddx 11 evldh 11 evldhx 11 evldw 11 evldwx 11 evlhhesplat 11 evlhhesplatx 11 evlhhossplat 11 evlhhossplatx 11 evlhhousplat 11 evlhhousplatx 11 evlwhe 11 evlwhex 11 evlwhos 11 evlwhosx 11 evlwhou 11 evlwhoux 11 evlwhsplat 11 evlwhsplatx 11 evlwwsplat 11 evlwwsplatx 11 evstdd 11 table 159. timing for integer simple instructions (continued) instruction latency throughput comments
UM0434 instruction pipeline and execution timing 229/391 spe complex integer instruction timing timings for spe complex integer instructions are shown in table 161 . the table is sorted by opcode. for the divide instructions, the numb er of stall cycles is (latency) for following instructions. evstddx 11 evstdh 11 evstdhx 11 evstdw 11 evstdwx 11 evstwhe 11 evstwhex 11 evstwho 11 evstwhox 11 evstwwe 11 evstwwex 11 evstwwo 11 evstwwox 11 table 161. spe complex inte ger instruction timing instruction latency throughput comments evaddsmiaaw 11 evaddssiaaw 11 evaddumiaaw 11 evaddusiaaw 11 evdivws 12?32 12?32 timings are data dependent evdivwu 12?32 12?32 timings are data dependent evmhegsmfaa 11 evmhegsmfan 11 evmhegsmiaa 11 evmhegsmian 11 evmhegumiaa 11 evmhegumian 11 evmhesmf 11 evmhesmfa 11 evmhesmfaaw 11 table 160. spe load and store instruction ti ming (continued) instruction latency throughput comments
instruction pipeline a nd execution timing UM0434 230/391 evmhesmfanw 11 evmhesmi 11 evmhesmia 11 evmhesmiaaw 11 evmhesmianw 11 evmhessf 11 evmhessfa 11 evmhessfaaw 11 evmhessfanw 11 evmhessiaaw 11 evmhessianw 11 evmheumi 11 evmheumia 11 evmheumiaaw 11 evmheumianw 11 evmheusiaaw 11 evmheusianw 11 evmhogsmfaa 11 evmhogsmfan 11 evmhogsmiaa 11 evmhogsmian 11 evmhogumiaa 11 evmhogumian 11 evmhosmf 11 evmhosmfa 11 evmhosmfaaw 11 evmhosmfanw 11 evmhosmi 11 evmhosmia 11 evmhosmiaaw 11 evmhosmianw 11 evmhossf 11 evmhossfa 11 evmhossfaaw 11 evmhossfanw 11 table 161. spe complex integer in struction timing (continued) instruction latency throughput comments
UM0434 instruction pipeline and execution timing 231/391 evmhossiaaw 11 evmhossianw 11 evmhoumi 11 evmhoumia 11 evmhoumiaaw 11 evmhoumianw 11 evmhousiaaw 11 evmhousianw 11 evmra 11 evmwhsmf 11 evmwhsmfa 11 evmwhsmi 11 evmwhsmia 11 evmwhssf 11 evmwhssfa 11 evmwhumi 11 evmwhumia 11 evmwlsmiaaw 11 evmwlsmianw 11 evmwlssiaaw 11 evmwlssianw 11 evmwlumi 11 evmwlumia 11 evmwlumiaaw 11 evmwlumianw 11 evmwlusiaaw 11 evmwlusianw 11 evmwsmf 11 evmwsmfa 11 evmwsmfaa 11 evmwsmfan 11 evmwsmi 11 evmwsmia 11 evmwsmiaa 11 evmwsmian 11 table 161. spe complex integer in struction timing (continued) instruction latency throughput comments
instruction pipeline a nd execution timing UM0434 232/391 vector floating-point apu instruction timing timings for embedded vector single-precision floating-point instructions are shown in table 159 . the number of stall cycles for evfsdiv is (latency) cycles. evmwssf 11 evmwssfa 11 evmwssfaa 11 evmwssfan 11 evmwumi 11 evmwumia 11 evmwumiaa 11 evmwumian 11 evsubfsmiaaw 11 evsubfssiaaw 11 evsubfumiaaw 11 evsubfusiaaw 11 table 162. spe vector floating -point instruction timing instruction latency throughput comments evfsabs 11 evfsadd 11 evfscfsf 11 evfscfsi 11 evfscfuf 11 evfscfui 11 evfscmpeq 11 evfscmpgt 11 evfscmplt 11 evfsctsf 11 evfsctsi 11 evfsctsiz 11 evfsctuf 11 evfsctui 11 evfsctuiz 11 evfsdiv 12 12 blocking, no overlap with next instruction evfsmadd 1 1 destination also used as source table 161. spe complex integer in struction timing (continued) instruction latency throughput comments
UM0434 instruction pipeline and execution timing 233/391 spe scalar floating-point instruction timing timings for embedded scalar single-precision floating-point apu instructions are shown in table 163 . the table is sorted by opcode. evfsmsub 1 1 destination also used as source evfsmul 11 evfsnabs 11 evfsneg 11 evfsnmadd 1 1 destination also used as source evfsnmsub 1 1 destination also used as source evfssub 11 evfststeq 11 evfststgt 11 evfststlt 11 table 163. scalar spe floati ng-point instru ction timing instruction latency throughput comments efsabs 11 efsadd 11 efscfsf 11 efscfsi 11 efscfuf 11 efscfui 11 efscmpeq 11 efscmpgt 11 efscmplt 11 efsctsf 11 efsctsi 11 efsctsiz 11 efsctuf 11 efsctui 11 efsctuiz 11 efsdiv 12 12 blocking, no execution overlap with next instruction efsdiv 12 12 blocking, no execution overlap with next instruction efsmadd 1 1 destination also used as source efsmsub 1 1 destination also used as source table 162. spe vector floa ting-point instruct ion timing (continued) instruction latency throughput comments
instruction pipeline a nd execution timing UM0434 234/391 8.8 operand placement on performance the placement (location and alignment) of operands in memory affects relative performance of memory accesses, and in some cases, affects it significantly. table 164 indicates the effects for the e200z3 core. in table 164 , ?optimal? means that one ea calculation occurs during the operation; ?good? means that multiple ea calculations occur during the memory operation, which may cause additional bus activities with multiple bus transfers; ?poor? means that the access generates an alignment interrupt. efsmul 11 efsnabs 11 efsneg 11 efsnmadd 1 1 destination also used as source efsnmsub 1 1 destination also used as source efssub 11 efststeq 11 efststgt 11 efststlt 11 table 163. scalar spe fl oating-point instruct ion timing (continued) instruction latency throughput comments table 164. performance effects of storage operand placement operand boundary crossing* size byte alignment none cache line protection boundary 4 byte 4 <4 optimal good -- good -- good 2 byte 2 <2 optimal good -- good -- good 1 byte 1 optimal -- -- lmw , stmw 4 <4 good poor good poor good poor string n/a optimal: one ea calculation occurs. good: multiple ea calculations occur, which may c ause additional bus activiti es with multiple bus transfers. poor: alignment interrupt occurs.
UM0434 external core complex interfaces 235/391 9 external core complex interfaces this chapter describes the external interfaces of the e200z3 core complex. signal descriptions as well as data transfer protocol s are documented in the following subsections. chapter 9.4: internal signals on page 265 ,? describes a number of internal signals that are not directly accessible to users, but they are mentioned in various chapters in this manual and aid in understanding the behavior of the core. 9.1 overview the external interfaces encompass the following: control and data signals supporting instruction and data transfers support for interrupts, including vectored interrupt logic reset support power management interface signals debug event signals time base control and status information processor state information nexus 1/3/once/jtag interface signals a test interface the memory interface that the biu supports is based on the amba ahb-lite subset of the amba 2.0 ahb, with v6 amba extensions. (ref. documents arm ihi 0011a, arm dvi 0044a, and arm pr022-genc-001011 0.4). sideband signals, described in this chapter, support additional control functions. a 64-bit data bus is implemented. the pipelined memory interface supports read and write transfers of 8, 16, 24, 32, and 64 bits, misaligned transfers, burst transfers of four double words, and true big- and little-endian operation. note: the amba ahb bit and byte ordering reflect a natural little-endian ordering that amba documentation uses. the biu automatically perfo rms byte lane conversions to support big- endian transfers. memories and peripheral devic es/interfaces should be wired according to byte lane addresses defined in table 170 . single-beat and misaligned transfers are supported for cache-inhibited read and write cycles, and write-buffer writes. burst transfers (double-word?aligned) of 4 double words are supported for cache line-fill and copyback operations. misaligned accesses are supported with one or more transfers to the core interface. if an access is misaligned but lies within an aligned 64-bit double word, the core performs a single transfer. the memory interface delivers (reads) or accepts (writes) the data that corresponds to the size- and byte-enable signals aligned according to the 3 low-order address bits. if an access is misaligned and crosses a 64-bit boundary, the biu performs a pair of transfers beginning at the effective address, requesting the original data size (either half word or word) for the first transfer, along with appropriate byte enables. for the second transfer, the address is incremented to the next 64-bit boundary, and the size and byte enable signals are driven to correspond to the number of remaining bytes to be transferred.
external core complex interfaces UM0434 236/391 9.2 signal index this section contains an index of the core signals. the following prefixes are used for signal mnemonics: 'm_' denotes master clock and reset signals. 'p_' denotes processor or core-related signals. 'j_' denotes jtag mode signals. 'jd_' denotes jtag and debug mode signals. 'ipt_' denotes scan and test mode signals. 'nex_' denotes nexus3 signals. note: the ?_b? suffix denotes active low signal. si gnals with no active-low suffix are active high. figure 31 groups core bus and control signals by function.
UM0434 external core complex interfaces 237/391 figure 31. core signal groups transfer transfer transfer control attributes p_htrans[1:0] p_[d,i]_hburst[2:0] p_[d,i]_hbstrb[7:0] data bus p_doze, p_nap, p_sleep p_reset_b reset- power address bus p_wakeup p_haddr[31:0] management * t these signals are internal to the core. note: e200z3 cpu p_pstat[0:6], p_brstat[0:1] processor status p_devt2 p_devt1 p_ude p_halt, p_stop p_halted, p_stopped p_[d,i]_hwrite p_[d,i]_hprot[5:0] p_[d,i]_hsize[1:0] p_[d,i]_hunalign reservation signals p_rsrv p_rsrv_clr p_tbint p_tbclk time base p_tbdisable signals debug support e200z3 module jd_debug_b dbg_dbgrq * cpu_dbgack * once control * jtag interface jd_de_b test interface jd_de_en jd_en_once jd_watchot[0:n] jd_mclk_on j_en_once_regsel m_por p_resetout_b p_rstbase[0:19] related signals (once/debug) p_d_hwdata[63:0] p_[d,i]_hrdata[63:0] p_cpuid[0:7] miscellaneous p_sysvers[0:31] p_pvrin[16:31] signals processor p_[d,i]_hresp[2:0] p_[d,i]hready status termination/ p_mcp_b p_chkstop machine check interrupt p_extint_b p_critint_b p_avec_b p_voffset[0:15] p_iack k signals p_ipend dev support e200z3 module nex_mseo_b[1:0] nex_evti_b nex_mdo[n:0] nex_mcko nex_rdy_b nex_evto_b clock m_clk p_rst_endmode p_[d,i]_hmaster[3:0] masterid nex_masterid[3:0] p_masterid[3:0] config p_mcp_out nexus3 nexus1 p_rst_vlemode
external core complex interfaces UM0434 238/391 table 165 below, shows the core signal function and type, signal definition, and reset value. signals are presented in functional groups. table 165. interface signal definitions signal name i/o reset definition clock and signals related to reset m_clk i global system clock m_por i power-on reset p_reset_b i processor reset input p_resetout_b o processor reset output p_rstbase[0:19] i reset exception handler base address, value to be loaded into tlb entry 0 on reset. p_rst_endmode i reset endian mode select, value to be loaded into tlb entry 0 on reset. p_rst_vlemode i reset vle mode select, value to be loaded into tlb entry 0 on reset. memory interface signals p_i_hmaster[3:0], p_d_hmaster[3:0] o?master id p_ i_ haddr[31:0], p_d_haddr[31:0] o ? address bus p_ i_ hwrite, p_d_hwrite o 0 write signal (always driven low for p_i_hwrite ) p_ i_ hprot[5:0], p_d_hprot[5:0] o ? protection codes p_ i_ htrans[1:0], p_d_htrans[1:0] o ? transfer type p_ i_ hburst[2:0] , p_d_hburst[2:0] o?burst type p_ i_ hsize[1:0], p_d_hsize[1:0] o ? transfer size p_ i_ hunalign, p_d_hunalign o ? indicates that the current data access is misaligned p_ i_ hbstrb[7:0] , p_d_hbstrb[7:0] o 0 byte strobes p_ i_ hrdata[63:0], p_d_hrdata[63:0] i read data bus p_d_hwdata[63:0] o ? write data bus p_ i_ hready, p_d_hready i transfer ready p_ i_ hresp[2:0], p_d_hresp[2:0] i transfer response
UM0434 external core complex interfaces 239/391 master id configuration signals p_masterid[3:0] i ? cpu master id configuration nex_masterid[3:0] i ? nexus3 master id configuration interrupt inte rface signals p_extint_b i external input interrupt request p_critint_b i critical input interrupt request p_avec_b i autovector request. use internal interrupt vector offset. p_voffset[0:15] i interrupt vector offset for vectored interrupts p_iack o0 interrupt acknowledge. indicates an interrupt is being acknowledged. p_ipend o 0 interrupt pending. indicates an interrupt is pending internally. p_mcp_b i machine check input request time base signals p_tbint o 0 time base interrupt p_tbdisable i ? time base disable input p_tbclk i ? time base clock input misc. cpu signals p_cpuid[0:7] i cpu id input p_sysvers[0:31] i system version inputs (for svr) p_pvrin[16:31] i inputs for pvr p_pid0[0:7] o 0 pid0[24:31] outputs p_pid0_updt o 0 pid0 update status cpu reservation signals p_rsrv o 0 reservation status p_rsrv_clr i clear reservation flag cpu state signals p_pstat[0:6] o 0 processor status p_brstat[0:1] o 0 branch prediction status p_mcp_out o 0 machine check occurred p_chkstop o 0 checkstop occurred p_doze o 0 low-power doze mode of operation p_nap o 0 low-power nap mode of operation p_sleep o 0 low-power sleep mode of operation table 165. interface signal definitions (continued) signal name i/o reset definition
external core complex interfaces UM0434 240/391 p_wakeup o0 indicates to external clock control module to enable clocks and exit from low-power mode p_halt i cpu halt request p_halted o 0 cpu halted p_stop i cpu stop request p_stopped o 0 cpu stopped cpu debug event signals p_ude i unconditional debug event p_devt1 i debug event 1 input p_devt2 i debug event 2 input debug/emulation support signals (nexus 1/once) jd_en_once i enable full once operation jd_debug_b o 1 processor entered debug session jd_de_b i debug request jd_de_en o 0 active-high output enable for de_b open-drain io cell jd_mclk_on i system clock controller actively toggling m_clk jd_watchpt[0:7] o 0 address watchpoint occurred development support signals (nexus 3) nex_mcko o nexus3 clock output nex_rdy_b o nexus3 ready output nex_evto_b o nexus3 event-out output nex_evt i_ b i nexus3 event-in input nex_mdo[n:0] o nexus3 message data output nex_mseo_b[1:0] o nexus3 message start/end output jtag-related signals j_trst_b i jtag test reset from pad j_tclk i jtag test clock from pad j_tms i jtag test mode select from pad j_tdi i jtag test data input from pad j_tdo o 0 jtag test data out to master controller or pad j_tdo_en o 0 enables tdo output buffer j_tst_log_rst o 0 test-logic-reset state of jtag controller j_capture_ir o 0 capture_ir state of jtag controller j_update_ir o 0 update_ir state of jtag controller table 165. interface signal definitions (continued) signal name i/o reset definition
UM0434 external core complex interfaces 241/391 9.3 signal descriptions table 166 describes the processor clock, m_clk . table 167 describes signals that are related to reset. the core supports several reset input signals for the cpu and jtag/once control logic: m_por , p_reset_b , and j_trst_b . the reset domains are partitioned such that the cpu p_reset_b signal does not affect jtag/once logic and j_trst_b does not affect processor logic. it is possible and desirable to access once registers while the processor is running or in reset. it is also possible and desirable to assert j_trst_b and clear the jtag/once logic without affecting the processor state. the synchronization logic between the processor and debug module requires an assertion of either j_trst_b or m_por during initial processor power-on reset to ensure proper operation. if the pin associated with j_trst_b is designed with a pull-up resistor and left floating, assertion of m_por is required during the initial power-on processor reset. similarly, for those systems that do not have a power-on reset circuit and choose to tie m_por low, it is required to assert j_trst_b during processor power-up reset. when a power-up reset is achieved, the two resets can be asserted independently. a reset output signal, p_resetout_b , is also provided. j_shift_ir o 0 shift_ir state of jtag controller j_capture_dr o 0 parallel test data register load state of jtag controller j_shift_dr o 0 tap controller in shift dr state j_update_gp_reg o 0 updates jtag controll er test data register j_rti o 0 jtag controller run-test-idle state j_key_in i input for providing data to be shifted out during shift_ir state when jd_en_once is negated j_en_once_regsel o 0 external enable once register select j_nexus_regsel o 0 external nexus register select j_lsrl_regsel o 0 external lsrl register select j_gp_regsel[0:11] o 0 general-purpose external jtag register select j_id_sequence[0:1] i jtag id register (2 msbs of sequence field) j_id_version[0:3] i jtag id register version field j_serial_data i serial data from external jtag registers table 165. interface signal definitions (continued) signal name i/o reset definition table 166. processor clock signal description signal i/o signal description m_clk i processor clock. the synchronous clock source for the core. because the core is designed for static operation, m_clk can be gated off to lower power dissipation (for example, during low-power stopped states).
external core complex interfaces UM0434 242/391 a set of input signals ( p_rstbase[0:19] , p_rst_endmode ) is provided to relocate the reset exception handler to allow for flexible placement of boot code and to select the default endian mode and vle mode of the core out of reset. table 167. descriptions of signals related to reset signal i/o signal description m_por i power-on reset. serves the following purposes: ? m_por is ored with j_trst_b and the resulting signal clears the jtag tap controller and associated registers as well as the once state machine. this signal is an asynchronous clear with a short assertion time requirement. ? m_por is ored with the p_reset_b function, and the resulting signal clears certain cpu registers. this is an asynchronous clear with a short assertion time requirement. reset values for other registers are listed in chapter 4.18.4: reset settings on page 101 .? state meaning asserted?power-on reset is requested. negated?power-on reset is not requested. p_reset_b i reset. treated as an asynchronous input and is sampled by the clock control logic in the debug module. state meaning asserted?reset is requested. negated?reset is not requested. p_resetout_b o reset out. conditionally asserted by either the watchdog timer ( chapter 4.11.1: timer control register (tcr) on page 64 ? ) or debug control logic. p_resetout_b is not asserted by p_reset_b . p_rstbase[0:19] i reset base. allows system integrators to specif y or relocate the base address of the reset exception handler. state meaning forms the upper 20 bits of the instru ction access following negation of reset, which is used to fetch the initial instruction of the reset exception handler. these bits should be driven to a value corresponding to the desired boot memory device in the system. these inputs are also used by the mmu during reset to form a default tlb entry 0 for translation of the reset vector fetch.the initial instruction fetch occurs to the location [p_rstbase[0:19]] || 0xffc. timing must remain stable in a window beginning 2 clocks before the negation of reset and extending into the cycle in which the reset vector fetch is initiated. p_rst_endmode i reset endian mode. used by the mmu during reset to form the e bit of the default tlb entry 0 for translation of the reset vector fetch. state meaning high?causes the resultant entry e bit to be set, indicating a little-endian page. low?causes the resultant entry e bit to be cleared, indicating a big-endian page. p_rst_vlemode i used by the mmu during reset to form the vle bit of the default tlb entry 0 for translation of the reset vector fetch. state meaning a low logic level causes the resultant entry vle bit to be cleared, indicating a book e page. a high logic level causes the resultant entry vle bit to be set, indicating a vle page.
UM0434 external core complex interfaces 243/391 table 168 describes signals for the address and data buses. these outputs provide the address for a bus transfer. according to the ahb definition, p_haddr31 is the msb and p_haddr0 is the lsb. j_trst_b i jtag/once reset (ieee 1149.1 jtag specification trst ). state meaning asynchronous reset with a short assertion time requirement. it is ored with the m_por function, and the resulting signal clears the once tap controller and associated registers and the once state machine. table 167. descriptions of signals related to reset (continued) signal i/o signal description table 168. descriptions of signals for the address and data buses signal i/o signal description p_[d,i]_haddr[31:0] o address bus. provides the address for a bus transfer. according to the ahb definition, p_[d,i]_haddr[31] is the msb and p_[d,i]_haddr[0] is the lsb. p_[d,i]_hrdata[63:0] i read data bus. provides data to the core on read transfers. the read data bus can transfer 8, 16, 24, 32, or 64 bits per tr ansfer. according to the ahb definition, p_[d,i]_hrdata63 is the msb and p_[d,i]_hrdata0 is the lsb. memory byte addresswired to p_[d,i]_hrdata bits 0007:0 00115:8 01023:16 01131:24 10039:32 10147:40 11055:48 11163:56 p_d_hwdata[63:0] o write data bus. transfers data from the core on write transfers. the write data bus can transfer 8, 16, 24, 32, or 64 bits of data per bus transfer. according to the ahb definition, p_d_hwdata[63] is the msb and p_d_hwdata[0] is the lsb. memory byte addresswired to p_d_hwdata bits 0007:0 00115:8 01023:16 01131:24 10039:32 10147:40 11055:48 11163:56
external core complex interfaces UM0434 244/391 table 169 describes transfer attribute signals, which provide additional information about the bus transfer cycle. attributes are driven with the address at the start of a transfer. table 169. descriptions of transfer attribute signals signal i/o signal description p_[d,i]_htrans[1:0] o transfer type. the processor drives p_[d,i]_htrans[1:0] to indicate the current transfer type as follows: 00 dle?no data transfer is required. slaves must terminate idle transfers with a zero wait-state okay response and ignore the (non-existent) transfer. 01 busy?(the core does not use the busy encoding and does not present this type of transfer to a bus slave.) master is busy; burst transfer continues. 10 nonseq?indicates the first transfer of a burst, or a single transfer. address and control signals are unrelated to the previous transfer. 11 seq?indicates the continuation of a burst. address and control signals are related to the previous transfer. control signals are the same. address was incremented by the size of the data transferred (optionally wrapped). if the p_[d,i]_htrans[1:0] encoding is not idle or busy, a transfer is being requested. p_[d,i]_hwrite o write. defines the data transfer direction for the current bus cycle. state meaning asserted?the current bus cycle is a write. negated?the current bus cycle is a read. p_[d,i]_hsize[1:0] o transfer size. for misaligned transfers, size may exceed the requested size to ensure that all asserted byte strobes are within the container defined by p_[d,i]_hsize[1:0] . table 171 and table 172 show p_[d,i]_hsize encodings for aligned and misaligned transfers. 00 byte 01 half word (2 bytes) 10 word (4 bytes) 11 double word (8 bytes)
UM0434 external core complex interfaces 245/391 p_[d,i]_hburst[2:0]] o burst type. the core uses only single and wrap4 burst types. 000 single?no burst, single beat only 001 incr?incrementing burst of unspecified length. not used by the core. p_[d,i]_hprot[5:0] o protection control. the core drives the p_[d,i]_hprot[5:0] signals to indicate the type of access for the current bus cycle. p_[d,i]_hprot[0] indicates instruction/data, p_[d,i]_hprot[1 ] indicates user/supervisor. p_[d,i]_hprot[5] indicates whethe r the access is exclusive (that is, for an lwarx or stwcx. ). p_[d,i]_hprot[4:2 ] (allocate, cacheable, bufferable) indicate particular cache attributes for the access. the following table shows the definitions of the p_[d,i]_hprot[5:0] signals. p_hprot5 p_hprot4 p_hprot3 p_hprot2 p_hprot1 p_hprot0 transfer type ? ? ? ? ? 0 instruction access ? ? ? ? ? 1 data access ? ? ? ? 0 ? user mode access ? ? ? ? 1 ? supervisor mode access ? 0 0 0 ? ? cache-inhibited ? 0 0 1 ? ? guarded, not cache-inhibited ?010??reserved ?011??reserved ?100??reserved ?101??reserved ? 1 1 0 ? ? cacheable, writethrough ? 1 1 1 ? ? cacheable, writeback 0 ? ? ? ? ? not exclusive 1 ? ? ? ? ? exclusive access the core maps book e stora ge attributes to the ahb hprot signals as described in the following. for buffered stores, p_[d,i]_hprot[1] is driven with the user/supervisor mode attribute associated with th e store at the time it was buffered. for cache line pushes/copybacks, p_[d,i]_hprot[1] indicates supervisor access . in both of these cases, p_[d,i]_hprot0 indicates a data access. tlb[i] tlb[g] tlb[w]||!l1csr0[cwm] p_hprot[4:2] transfer type 0 0 0 111 cacheable, writeback 0 0 1 110 cacheable, writethrough 0 1 ? 001 guarded, not cache-inhibited 1 ? ? 000 cache-inhibited ? ? ? 001 buffered store, page marked guarded ? ? ? 110 buffered store and page marked writethrough or l1csr0[cwm]=0, and non- guarded ? ? ? 111 buffered store and page marked copyback and l1csr0[cwm]=1, and non- guarded ? ? ? 111 dirty line push table 169. descriptions of transfer attribute signals (continued) signal i/o signal description
external core complex interfaces UM0434 246/391 table 170 describes signals for byte lane specification. r ead transactions transfer from 1?8 bytes of data on the p_[d,i]_hrdata[63:0] bus. the lanes involved in the transfer are determined by the starting byte number specified by the lower address bits with the tr ansfer size and byte strobes. byte lane addressing is shown big-endian (left to right) regardless of the core?s endian mode. the byte in memory corresponding to address 0 is connected to b0 ( p_h{r,w}data[7:0] ) and the byte corresponding to address 7 is connected to b7 ( p_h{r,w}data[63:56] ). the cpu internally permutes read data as required for the endian mode of the current access. assertion of p_[d,i]_hunalign indicates misaligned transfers and that byte strobes do not correspond exactly to size and low-order address bits. table 171 lists all data transfer permutations. note that misaligned data requests that cross a 64-bit boundary are broken into two bus transactions, and the address value and size encoding for the first transfer are not modified. the table is arranged in a big-endian fashion, but the active lanes are the same regardless of the endian-mode of the access. the core performs the proper byte routing internally based on endianness. table 170. descriptions of signals for byte lane specification signal i/o signal description p_ [d,i]_ hunalign o unaligned access. indicates whether the current access is misaligned. state meaning asserted?asserted for misaligned data accesses and for misaligned instruction accesses from vle pages. normal book e instruction pages are always aligned. when p_[d,i]_hunalign is asserted, the p_[d,i]_hbstrb[7:0] byte strobe signals indicate the selected bytes involved in the current portion of the misaligned access, which may not include all bytes defined by the size and low-order address signals. aligned transfers also assert the byte strobes, but in a manner corresponding to size and low-order address bits. negated?no misaligned data access is occurring. timing the timing of this signal is approximately the same as address timing. p_ [d,i]_ hbstrb[7:0] o byte strobes. indicate the bytes selected for the current transfer. for a misaligned access, the current transfer may not include all byte s defined by the size and low-order address signals. for aligned transfers, the byte strobe signals correspond to the bytes that size and low-order address signals define. the relationships of byte addresses to the byte strobe signals are as follows. memory byte address wired to p_h{r,w}data bits corresponding byte strobe signal 000 7:0 p_[d,i]_hbstrb[0] 001 15:8 p_[d,i]_hbstrb[1] 010 23:16 p_[d,i]_hbstrb[2] 011 31:24 p_[d,i]_hbstrb[3] 100 39:32 p_[d,i]_hbstrb[4] 101 47:40 p_[d,i]_hbstrb[5] 110 55:48 p_[d,i]_hbstrb[6] 111 63:56 p_[d,i]_hbstrb[7] table 171. byte strobe assertion for transfers program size and byte offset a(2:0) hsize [1:0] data bus byte strobes hunalign b0 b1 b2 b3 b4 b5 b6 b7 byte @000 0 0 0 0 0 x ??????? 0 byte @001 0 0 1 0 0 ? x ? ? ? ? ? ? 0 byte @010 0 1 0 0 0 ? ? x ? ? ? ? ? 0
UM0434 external core complex interfaces 247/391 table 172 shows the final layout in memory for data transferred from a 64-bit gpr containing the bytes ?a b c d e f g h? to memory. the core breaks misaligned accesses that cross a double-word boundary into a pair of accesses. double-word transfers are always double-word?aligned. byte @011 0 1 1 0 0 ? ? ? x ? ? ? ? 0 byte @100 1 0 0 0 0 ? ? ? ? x ? ? ? 0 byte @101 1 0 1 0 0 ????? x ?? 0 byte @110 1 1 0 0 0 ?????? x ? 0 byte @111 1 1 1 0 0 ??????? x 0 half @000 0 0 0 0 1 x x ? ? ? ? ? ? 0 half @001 0 0 1 1 0 (1) ? x x ????? 1 half @010 0 1 0 0 1 ? ? x x ? ? ? ? 0 half @011 0 1 1 1 1 1 ??? x x ??? 1 half @100 1 0 0 0 1 ? ? ? ? x x ? ? 0 half @101 1 0 1 1 0 1 ????? x x ? 1 half @110 1 1 0 0 1 ?????? x x 0 half @111 (two bus transfers) 1 1 1 0 0 0 0 1 (2) 0 0 ? x ? ? ? ? ? ? ? ? ? ? ? ? x ? 1 0 word @000 0 0 0 1 0 x x x x ? ? ? ? 0 word @001 0 0 1 1 1 1 ?xxxx??? 1 word @010 0 1 0 1 1 1 ??xxxx?? 1 word @011 0 1 1 1 1 1 ??? x x x x ? 1 word @100 1 0 0 1 0 ? ? ? ? x x x x 0 word @101 (two bus transfers) 1 0 1 0 0 0 1 0 0 0 ? x ? ? ? ? ? ? ? ? x ? x ? x ? 1 0 word @110 (two bus transfers) 1 1 0 0 0 0 1 0 2 0 1 ? x ? x ? ? ? ? ? ? ? ? x ? x ? 1 0 word @111 (two bus transfers) 1 1 1 0 0 0 1 0 2 1 0 ? x ? x ? x ? ? ? ? ? ? ? ? x ? 1 1 double word 0 0 0 1 1 xxxxxxxx 0 1. these misaligned transfers drive size according to the size of the power of two aligned containers in which the byte strobes are asserted. 2. these misaligned cases drive request si ze according to the size specifi ed by the load or store instruction. table 171. byte strobe assertion for transfers (continued) program size and byte offset a(2:0) hsize [1:0] data bus byte strobes hunalign b0 b1 b2 b3 b4 b5 b6 b7
external core complex interfaces UM0434 248/391 table 172. big-and little-endian storage (64-bit gpr contains ?a b c d e f g h?) program size and byte offset a(3:0) hsize (1:0) even double word? 0 0dd double word?1 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 byte @0000 0 0 0 0 0 0 h ??????????????? byte @0001 0 0 0 1 0 0 ? h ?????????????? byte @0010 0 0 1 0 0 0 ?? h ????????????? byte @0011 0 0 1 1 0 0 ??? h ???????????? byte @0100 0 1 0 0 0 0 ???? h ??????????? byte @0101 0 1 0 1 0 0 ????? h ?????????? byte @0110 0 1 1 0 0 0 ?????? h ????????? byte @0111 0 1 1 1 0 0 ??????? h ???????? byte @1000 1 0 0 0 0 0 ???????? h ??????? byte @1001 1 0 0 1 0 0 ????????? h ?????? byte @1010 1 0 1 0 0 0 ?????????? h ????? byte @1011 1 0 1 1 0 0 ??????????? h ???? byte @1100 1 1 0 0 0 0 ???????????? h ??? byte @1101 1 1 0 1 0 0 ????????????? h ?? byte @1110 1 1 1 0 0 0 ?????????????? h ? byte @1111 1 1 1 1 0 0 ??????????????? h b. e. half @0000 0 0 0 0 0 1 g h ?????????????? b. e. half @0001 0 0 0 1 1 0 (1) ? g h ????????????? b. e. half @0010 0 0 1 0 0 1 ?? g h ???????????? b. e. half @0011 0 0 1 1 1 1 1 ??? g h ??????????? b. e. half @0100 0 1 0 0 0 1 ???? g h ?????????? b. e. half @0101 0 1 0 1 1 0 1 ????? g h ????????? b. e. half @0110 0 1 1 0 0 1 ?????? g h ???????? b. e. half @0111 0 1 1 1 0 1 ??????? g ???????? 1 0 0 0 0 0 ???????? h ??????? b. e. half @1000 1 0 0 0 0 1 ???????? g h ?????? b. e. half @1001 1 0 0 1 1 0 1 ????????? g h ????? b. e. half @1010 1 0 1 0 0 1 ?????????? g h ???? b. e. half @1011 1 0 1 1 1 1 1 ??????????? g h ??? b. e. half @1100 1 1 0 0 0 1 ???????????? g h ?? b. e. half @1101 1 1 0 1 1 0 1 ????????????? g h ? b. e. half @1110 1 1 1 0 0 1 ?????????????? g h
UM0434 external core complex interfaces 249/391 b. e. half @1111 1 1 1 1 0 1 ??????????????? g 0 0 0 0 (next dword) 0 0 h ??????????????? l e. half @0000 0 0 0 0 0 1 h g ? ? ? ? ? ? ? ? ? ? ? ? ? ? l. e. half @0001 0 0 0 1 1 0 1 ? h g ????????????? l. e. half @0010 0 0 1 0 0 1 ?? h g ???????????? l. e. half @0011 0 0 1 1 1 1 1 ??? h g ??????????? l. e. half @0100 0 1 0 0 0 1 ???? h g ?????????? l. e. half @0101 0 1 0 1 1 0 1 ????? h g ????????? l. e. half @0110 0 1 1 0 0 1 ?????? h g ???????? l. e. half @0111 0 1 1 1 0 1 ??????? h ???????? 1 0 0 0 0 0 ???????? g ??????? l. e. half @1000 1 0 0 0 0 1 ???????? h g ?????? l. e. half @1001 1 0 0 1 1 0 1 ????????? h g ????? l. e. half @1010 1 0 1 0 0 1 ?????????? h g ???? l. e. half @1011 1 0 1 1 1 1 1 ??????????? h g ??? l. e. half @1100 1 1 0 0 0 1 ???????????? h g ?? l. e. half @1101 1 1 0 1 1 0 1 ????????????? h g ? l. e. half @1110 1 1 1 0 0 1 ?????????????? h g l. e. half @1111 1 1 1 1 0 1 ??????????????? h + 0 0 0 0 (next dword) 0 0 g ??????????????? b. e. word @0000 0 0 0 0 1 0 e f g h ???????????? b. e. word @0001 0 0 0 1 1 1 1 ? e f g h ??????????? b. e. word @0010 0 0 1 0 1 1 1 ?? e f g h ?????????? b. e. word @0011 0 0 1 1 1 1 1 ??? e f g h ????????? b. e. word @0100 0 1 0 0 1 0 ? ? ? ? e f g h ? ? ? ? ? ? ? ? b. e. word @0101 0 1 0 1 1 0 ????? e f g ???????? 1 0 0 0 0 0 ???????? h ??????? b. e. word @0110 0 1 1 0 1 0 ?????? e f ???????? 1 0 0 0 0 1 ???????? g h ?????? b. e. word @0111 0 1 1 1 1 0 ??????? e ???????? 1 0 0 0 1 0 ? ? ? ? ? ? ? ? f g h ? ? ? ? ? b. e. word @1000 1 0 0 0 1 0 ? ? ? ? ? ? ? ? e f g h ? ? ? ? table 172. big-and little-endian storage (64-bit gpr contains ?a b c d e f g h?) (continued) program size and byte offset a(3:0) hsize (1:0) even double word? 0 0dd double word?1 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
external core complex interfaces UM0434 250/391 b. e. word @1001 1 0 0 1 1 1 1 ????????? e f g h ??? b. e. word @1010 1 0 1 0 1 1 1 ?????????? e f g h ?? b. e. word @1011 1 0 1 1 1 1 1 ??????????? e f g h ? b. e. word @1100 1 1 0 0 1 0 ???????????? e f g h b. e. word @1101 1 1 0 1 1 0 ????????????? e f g + 0 0 0 0 (next dword) 0 0 h ??????????????? b. e. word @1110 1 1 1 0 1 0 ?????????????? e f + 0 0 0 0 (next dword) 0 1 g h ?????????????? b. e. word @1111 1 1 1 1 1 0 ??????????????? e + 0 0 0 0 (next dword) 1 0 f g h ????????????? l. e. word @0000 0 0 0 0 1 0 h g f e ???????????? l. e. word @0001 0 0 0 1 1 1 1 ? h g f e ??????????? l. e. word @0010 0 0 1 0 1 1 1 ?? h g f e ?????????? l. e. word @0011 0 0 1 1 1 1 1 ??? h g f e ????????? l. e. word @0100 0 1 0 0 1 0 ? ? ? ? h g f e ? ? ? ? ? ? ? ? l. e. word @0101 0 1 0 1 1 0 ????? h g f ???????? 1 0 0 0 0 0 ???????? e ??????? l. e. word @0110 0 1 1 0 1 0 ?????? h g ???????? 1 0 0 0 0 1 ???????? f e ?????? l. e. word @0111 0 1 1 1 1 0 ??????? h ???????? 1 0 0 0 1 0 ? ? ? ? ? ? ? ? g f e ? ? ? ? ? l. e. word @1000 1 0 0 0 1 0 ? ? ? ? ? ? ? ? h g f e ? ? ? ? l. e. word @1001 1 0 0 1 1 1 1 ????????? h g f e ??? l. e. word @1010 1 0 1 0 1 1 1 ?????????? h g f e ?? l. e. word @1011 1 0 1 1 1 1 1 ??????????? h g f e ? l. e. word @1100 1 1 0 0 1 0 ???????????? h g f e l. e. word @1101 1 1 0 1 1 0 ????????????? h g f + 0 0 0 0 (next dword) 0 0 e ??????????????? l. e. word @1110 1 1 1 0 1 0 ?????????????? h g + 0 0 0 0 (next dword) 0 1 f e ?????????????? table 172. big-and little-endian storage (64-bit gpr contains ?a b c d e f g h?) (continued) program size and byte offset a(3:0) hsize (1:0) even double word? 0 0dd double word?1 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
UM0434 external core complex interfaces 251/391 table 173 describes the transfer control signals. table 174 describes the master id configuration signals. these inputs drive the p_[d,i]_hmaster[3:0] outputs when a bus cycle is active. table 175 describes interrupt control signals. interrupt request inputs ( p_extint_b, p_critint_b, and p_mcp_b ) to the core are level-sensitive. the interrupt controller must keep the interrupt request and any l. e. word @1111 1 1 1 1 1 0 ??????????????? h + 0 0 0 0 (next dword) 1 0 g f e ????????????? b.e. double word - 0 0 0 1 1 a b c d e f g h ???????? l.e. double word - 0 0 0 1 1 h g f e d c b a ? ? ? ? ? ? ? ? 1. these misaligned transfers drive size according to the size of the power of two aligned containers in which the byte strobes are asserted. table 172. big-and little-endian storage (64-bit gpr contains ?a b c d e f g h?) (continued) program size and byte offset a(3:0) hsize (1:0) even double word? 0 0dd double word?1 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 table 173. descriptions of signals for transfer control signals signal i/o signal description p_ [d,i]_ hready i transfer ready. indicates whether a requested transfer operation has completed. an external device asserts p_[d,i]_hready to terminate the transfer. p_hresp[2:0] indicate the transfer status. state meaning asserted?a requested transfer operation has completed. an external device asserts p_[d,i]_hready to terminate the transfer. negated?a requested transfer operation has not completed. p_hresp[2:0] i transfer response. indicate status of a terminating transfer. 000 okay?transfer terminated normally. 001 error?transfer terminated abnormally. see note for assertion. 010 reserved (retry not supported in ahb-lite protocol) 011 reserved (split not supported in ahb-lite protocol) 100 xfail?exclusive store failed ( stwcx. did not complete successfully). see note for assertion. (signaled to the cpu using the p_xfail_b internal signal. see table 190 .) 101?111 reserved timing assertion?error and xfail are required to be 2-cycle responses that must be signaled one cycle before assertion of p_[d,i]_hready and must remain unchanged during the cycle p_[d,i]_hready is asserted. the xfail response is signaled to the cpu using the p_xfail_b internal signal. table 174. descriptions of master id configuration signals signal i/o signal description p_masterid[3:0] i cpu master. configures the master id for the cpu. driven on p_[d,i]_hmaster[3:0] for a cpu-initiated bus cycle. nex_masterid[3:0] i nexus3 master. configure the master id for the nexus3 unit. driven on p_[d,i]_hmaster[3:0] for a nexus3-initiated bus cycle.
external core complex interfaces UM0434 252/391 p_voffset or p_avec_b inputs (as appropriate) asserted until the interrupt is serviced to guarantee that the core recognizes the re quest. on the other hand, when a request is generate d, the core may still not recognize the interrupt request, even if it is removed later. requests must be held stable to avoid spurious responses. table 175. descriptions of interrupt signals signal i/o signal description p_extint_b i external input interrupt request. provides the external input interrupt request to the core. p_extint_b is masked by msr[ee]. state meaning asserted?an external input interrupt request has been signaled. negated?an external input interrupt request has not been signaled. timing not internally synchronized by the core. it must meet setup and hold time constraints relative to m_clk when the core clock is running. assertion?level-sensitive, must remain asserted to be guaranteed recognition. p_critint_b i critical input interrupt request. critical i nput interrupt request to the core. masked by msr[ce]. state meaning asserted?critical input interrupt is being requested. negated?no critical input interrupt is requested. timing not internally synchronized by the core. must meet setup and hold times relative to m_clk when the core clock is running. see chapter 9.5.6: interru pt interface on page 289 .? assertion?level-sensitive, must remain asserted to be guaranteed to be recognized. p_ipend i interrupt pending. indicates whether a p_extint_b or p_critint_b interrupt request or an enabled timer facility interrupt was recognized internally by the core, is enabled by the appropriate msr bit, and is asserted in response to the interrupt request inputs. p_ipend can signal other bus masters or a bus arbiter that an interrupt is pending. external power management logic can use p_ipend to control operation of the core and other logic or may use p_wakeup similarly. higher priority exceptions may delay handling of the interrupt. state meaning asserted?a p_extint_b or p_critint_b interrupt request or an enabled timer facility interrupt (watchdog, fixed-interval, or decrementer) was recognized internally by the core. assertion of p_ipend does not mean that exception processing for the interrupt has begun. negated?a p_extint_b or p_critint_b interrupt request or an enabled timer facility interrupt has not been recognized. p_avec_b i autovector. determines how a vector is chosen for critical and external interrupt signals. state meaning asserted?asserted with either the p_extint_b or p_critint_b interrupt request to request use of the ivor4 or ivor0 for obtaining an exception vector offset. negated?if negated when a p_extint_b or p_critint_b interrupt is requested, an external vector offset and context selector is taken from p_voffset[0:15] . timing must be driven to a valid state dur ing each clock cycle that either p_extint_b or p_critint_b is asserted. assertion?level-sensitive, must remain asserted to have guaranteed recognition.
UM0434 external core complex interfaces 253/391 table 176 describes the timer facility signals, which ar e associated with the time base, watchdog, fixed- interval, and decre menter facilities. p_voffset[0:15 ] i interrupt vector offset. vector offset and context selector used when processing begins for an incoming interrupt request. ignored if multip le hardware contexts are not implemented. state meaning correspond to ivor n [16?31]. p_voffset[0:11] are used in forming the exception handler address; p_voffset[12:15] are used to select a new operating context when multiple hardware contexts are implemented. timing sampled with the p_extint_b and p_critint_b interrupt request inputs; must be driven to a valid value when either signal is asserted unless p_avec_b is also asserted. if p_avec_b is asserted, these inputs are not used. assertion?level-sensitive; mu st remain asserted to guar antee correct recognition. must be asserted concurrently with p_extint_b and p_critint_b when used. p_iack o interrupt vector acknowledge. interrupt vector acknowledge indicator to allow external interrupt controllers to be informed when a critical input or external input interrupt is being processed. state meaning asserted?an interrupt vector is being acknowledged. negated?an interrupt vector is not being acknowledged. timing assertion?asserted after the cycle in which p_avec_b and p_voffset[0:15] are sampled in preparation for exception processing. see figure 62 and figure 63 for timing diagrams. p_mcp_b i machine check. machine check interrupt req uest to the core. masked by hid0[emcp]. state meaning asserted?a machine check interrupt is being requested. negated?a machine check interrupt is not being requested. timing because this signal is not internally synch ronized by the core, it must meet setup and hold time constraints to m_clk when the core clock is running. p_mcp_b is not sampled while the core is in the hal ted or stopped power management states. assertion? p_mcp_b is sampled on two consecutive m_clk periods to detect a transition from the negated to the asserted st ate. it is internally qualified with this transition, but must remain asserted to be guaranteed to be recognized . table 175. descriptions of interrupt signals (continued) signal i/o signal description table 176. descriptions of timer facility signals signal i/o signal description p_tbdisable i timer disable. used to disable the internal time base and decrementer counters. used to freeze the state of the time base and decrementer during low power or debug operation. state meaning asserted?time base and decrementer updates are frozen. negated?time base and decrem enter updates are unaffected. timing not internally synchronized by the core; must meet setup and hold time constraints relative to m_clk when the core clock is running, as well as to p_tbclk when selected as an alternate time base clock source. p_tbclk i timer external clock. used as an alternate cl ock source for the time base and decrementer counters. selection of this clock is made using hid0[sel_tbclk] (see chapter 4.13.1: hardware implementation dependent register 0 (hid0) on page 84 ?). timing must be synchronous to the m_clk input and cannot exceed 50% of the m_clk frequency. must be driven such that it changes state on the falling edge of m_clk .
external core complex interfaces UM0434 254/391 table 177 describes the processor reservation signals associated with lwarx and stwcx. . table 178 describes miscellaneous processor signals. p_tbint o timer interrupt status. indicates whether an internal timer facility unit is requesting an interrupt (tsr[wis]=1 and tcr[wie]=1, or tsr[dis]=1 and tcr[die]=1, or tsr[fis]=1 and tcr[fie]=1). may be used to ex it low power operation or for other system purposes. state meaning asserted?an internal timer facility unit is generating an interrupt request. negated?an internal timer facility unit is not generating an interrupt request. table 176. descriptions of timer facility signals (continued) signal i/o signal description table 177. descriptions of processor reservation signals signal i/o signal description p_rsrv o cpu reservation status. indicates whether a reservation was established by the execution of an lwarx . state meaning asserted?a reservation was established by successful execution of an lwarx . remains asserted until the reservation is cleared. negated?no reservation is in effect. timing assertion?remains asserted until the reservation is cleared. p_rsrv_clr i cpu reservation clear. used to clear a reservation. external logic may use this signal to implement reservation management polic ies outside the scope of the cpu. p_xfail_b indicates success/failure of an stwcx. as part of bus transfer termination using the xfail p_hresp[2:0] encoding. state meaning asserted?signals that a reservation shoul d be cleared. asserted independently of any bus transfer. timing assertion?asserted independently of any bus transfer. table 178. descriptions of miscellaneous processor signals signal i/o signal description p_cpuid[0:7] i cpu id. reflected in the pir. see chapter 4.4.2: processor id register (pir) on page 45 .? timing intended to remain in a static condition and are not internally synchronized. p_pid0[0:7] o pid0 outputs. reflecte d to pid0[56?63]. see chapter 4.16.5: process id register (pid0) on page 96 .? p_pid0_updt o pid0 update. indicates that pid0 is being updated by an mtspr . state meaning asserted?pid0 is being updated by an mtspr . negated?pid0 is not being updated by an mtspr . timing assertion?asserts during the clock cycle the p_pid0[0:7] outputs are changing . p_sysvers[0:31] i system version. core version number reflected in the svr. see chapter 4.4.4: system version register (svr) on page 46 .? timing intended to remain in a static condition and not internally synchronized.
UM0434 external core complex interfaces 255/391 9.3.1 processor state signals table 179 describes the processor state signals. p_pvrin[16:31] i processor version. provide a portion of the version number for a particular cpu. reflected in the pvr. see chapter 4.4.3: processor versio n register (pvr) on page 45 .? timing intended to remain in a static condition and are not internally synchronized. table 178. descriptions of miscellaneous processor signals (continued) signal i/o signal description table 179. descriptions of processor state signals signal i/o signal description p_pstat[0:6] o processor status. indicate the internal execution unit status. any values not shown are reserved. p_pstat[0:6] internal processor status 00000xx execution stalled 00001xx execute exception 00010xx instruction squashed 01000xx processor in halted state 01001xx processor in stopped state 01010xx processor in debug mode (1) 01011xx processor in checkstop state 10000sm complete instruction (2),(3) 1000100 complete lmw or stmw 1000101 complete e_lmw or e_stmw 1001000 complete isync 1001011 complete se_isync 100110m complete lwarx or stwcx. 3 1100000 complete branch instruction bc , bcl , bca , bcla, b, bl, ba, bla resolved as not taken 1100001 complete branch instruction e_bc , e_bcl , e_b, e_bl resolved as not taken 1100011 complete branch instruction se_bc , se_bcl , se_b, se_bl resolved as not taken 1100100 complete branch instruction bc , bcl , bca , bcla, b, bl, ba, bla resolved as taken 1100101 complete branch instruction e_bc , e_bcl , e_b, e_bl resolved as taken 1100111 complete branch instruction se_bc , se_bcl , se_b, se_bl resolved as taken 1101000 complete bclr , bclrl, bcctr , bcctrl resolved as not taken 1101100 complete bclr , bclrl, bcctr , bcctrl resolved as taken 1101111 complete se_blr , se_blrl, se_bctr , se_bctrl (always taken) 111000m complete isel with condition false 111010m complete isel with condition true 1111100 complete rfi , rfci , or rfdi 1111111 complete se_rfi , se_rfci , or se_rfdi timing synchronous with m_clk , so the indicated status may not apply to a current bus transfer.
external core complex interfaces UM0434 256/391 table 180 describes power management and other external control logic functions. p_brstat[0:1] o branch prediction status. indicates the status of a branch prediction prefetch. such prefetches are performed for branch target buffer (btb) hi ts with predict taken status to accelerate branches. p_s1stat[0:1] s1 prefetch status 0x default (no branch-predicted taken prefetch) 10 branch-predicted taken prefetch resolved as not taken 11 branch-predicted taken prefetch resolved as taken timing synchronous with m_clk , so the indicated status may not apply to a current bus transfer. p_mcp_out o processor machine check. indicates whethe r a machine check condition has caused a syndrome bit to be set in the machine check syndrome register (mcsr). state meaning asserted?a machine check condition caused an mcsr bit to be set. negated?no machine check condition exis ts that would set an mcsr bit. p_chkstop o processor checkstop. asserted by the processo r when a checkstop condition has occurred and the cpu has entered the checkstop state. state meaning asserted?the processor has indicated a checkstop condition. negated?the processor has not indicated a checkstop condition. 1. as reflected on the cpu_dbgack internal state signal 2. except rfi, rfci, rfdi, lmw, stmw, lwarx, stwcx., isyn c, isel, se_rfi, se_rfci, se_rfdi, e_lmw, e_stmw, se_isel, and change of flow instructions 3. s: instruction size, 0 = 32 bit, 1 = 16 bit. m: 0 for book e page, 1 for vle page table 179. descriptions of processor state signals (continued) signal i/o signal description table 180. descriptions of power management control signals signal i/o signal description p_halt i processor halt request. used to request that the processor enter the halted state. state meaning asserted?requests the processor to enter halted state. negated?no request is being made for the processor to enter halted state. p_halted o processor halted. the active-high p_halted output signal indicates that the processor entered the halted state. state meaning asserted?the processor is in halted state. negated?the processor is not in halted state. p_stop i processor stop request. the active-high p_stop input signal requests that the processor enter the stopped state. state meaning asserted?requests the processor to enter stopped state. negated?no request is being made for th e processor to enter stopped state. p_stopped o processor stopped. the active-high p_stopped output signal indicates that the processor entered the stopped state. state meaning asserted?the processor is in stopped state. negated?the processor is not in stopped state.
UM0434 external core complex interfaces 257/391 table 181 describes signal debug events to the core. p_doze p_nap p_sleep o low-power mode. asserted by the processor to reflect the settings of hid0[doze,nap,sleep] when msr[we] is set. the core can be placed in a low-power state by forcing m_clk to a quiescent state and brought out of low-power state by re-enabling m_clk . the time base facilities may be separately enabled or disabled using combinations of the timer facility control signals. external logic can detect the asserted edge or level of these signals to determine which low- power mode has been requested and then place the core and peripherals in a low-power consumption state. p_wakeup can be monitored to determine when to end the low-power condition. state meaning asserted?msr[we] and the respective hid0 bit are both set. negated?msr[we] and the respecti ve hid0 bit are not both set. timing assertion?may assert for 1 or more clock cycles. p_wakeup o wake up. used by external logic to remove the core and system logic from a low-power state. it can also indicate to the syst em clock controller that m_clk should be re-enabled for debug purposes. p_wakeup (or other system state) should be monitored to dete rmine when to release the processor (and system if applicable) from a low-power state. state meaning asserted?asserts whenever one of the following occurs: ? a valid pending interrupt is detected by the core. ? a request to enter debug mode is made by setting the ocr[dr] or via the assertion of jd_de_b or p_ude . ? the processor is in a debug session and jd_debug_b is asserted. ? a request to enable m_clk has been made by setting ocr[wkup]. timing see chapter 9.5.5: power management on page 289 .? this signal is asynchronous to the system clock and should be synchronized to the system clock domain to avoid hazards. table 180. descriptions of power management control signals (continued) signal i/o signal description table 181. descriptions of debug events signals signal i/o signal description p_ude i unconditional debug event. used to request an unconditional debug event. state meaning asserted?an unconditional debug event has been requested. only a transition from negated to asserted state of p_ude causes an event to occur. however, the level on this signal causes assertion of p_wakeup . negated?no unconditional debug event has been requested. timing not internally synchronized by the core, and must meet setup and hold time constraints relative to m_clk when the core clock is running. assertion?level-sensitive and must be held asserted until acknowledged by software, or, when external debug mode is enabled, by assertion of jd_debug_b to be guaranteed recognition. only a transition from negated to asserted state of p_ude causes an event to occur. however, the level on this signal causes assertion of p_wakeup .
external core complex interfaces UM0434 258/391 table 182 lists debug/emulation (nexus 1/ once) support signals. these signals assist in implementing an on-chip emulation ca pability with a contro ller external to the core . table 183 describes debug/emulation (nexus 1/ once) support signals. p_devt1 i external debug event 1. used to request an external debug event. if the core clock is disabled, this signal is not recognized. in addition, only a transition from negated to asserted state of p_devt1 causes an event to occur. it is intended to si gnal core-related events generated while the cpu is active. state meaning asserted?an external debug event is requested. only a transition from negated to asserted state of p_devt1 causes an event to occur. it is intended to signal core-related events generated while the cpu is active. negated?no external debug event is requested. timing not internally synchronized by the core, and must meet setup and hold time constraints relative to m_clk when the core clock is running. p_devt2 i external debug event 2. used to request an external debug event. if the core clock is disabled, this signal is not recognized. in addition, only a transition from negated to asserted state of p_devt2 causes an event to occur. it is intended to si gnal core-related events generated while the cpu is active. state meaning asserted?an external debug event is requested. only a transition from negated to asserted state of p_devt2 causes an event to occur. negated?no external debug event is requested. timing not internally synchronized by the core, and must meet setup and hold time constraints relative to m_clk when the core clock is running. table 181. descriptions of debug events signals (continued) signal i/o signal description table 182. core debug/emulation support signals signal type description jd_en_once i enable full once operation jd_debug_b o debug session indicator jd_de_b i debug request jd_de_en o de_b active high output enable jd_mclk_on i cpu clock is active indicator
UM0434 external core complex interfaces 259/391 table 183. descriptions of debug/emulation (nexus 1/ once) support signals signal i/o signal description jd_en_once i once enable. enables the once controller to allow certain instructions and operations to be executed. other systems should tie this signal a sserted to enable fu ll once operation. j_en_once_regsel and j_key_in are provided to assist external logic performing security checks. state meaning asserted?enables the full once command set, as well as operation of control signals and once control register functions. negated?only the bypass, id, and enabl e_once commands are executed by the once unit; all other commands default to a bypass command. the once status register (osr) is not visible when once operation is disabled. in addition, ocr functions and the operation of jd_de_b are disabled. secure systems may leave this signal negated until a security check is performed. timing must change state only during the test-logic- reset, run-test/idle, or update_dr tap states. a new value takes effect after one additional j_tclk cycle of synchronization. jd_debug_b o debug session. a debug session includes single-step operations (go+noexit once commands). this signal is prov ided to inform system resource s that access is occurring for debug purposes, thus allowing certain resource side effects to be frozen or otherwise controlled. examples may include fifo state c hange control and control of side-effects of register or memory accesses. see chapter 11.5.4: once interface signals on page 309 .? state meaning asserted?asserted when the processor ent ers debug mode. it remains asserted for the duration of a debug session. that is, during once single-step executions. jd_de_b i debug request. normally the input from the top-level de_b open-drain bidirectional i/o cell. see chapter 11.5.4: once interface signals on page 309 .? state meaning asserted?a debug request is pending. negated?no debug request is pending. timing assertion?not internally synchronized by the core and must meet setup and hold time constraints relative to j_tclk . to be recognized, it must be held asserted for a minimum of two j_tclk periods, and jd_en_once must be in the asserted state. jd_de_b is synchronized to m_clk in the debug module before being sent to the processor (two clocks). jd_de_en o de_b active high output enable. enable for the top-level de_b open-drain bidirectional i/o cell. see chapter 11.5.4: once interface signals on page 309 .? state meaning asserted?the top-level de_b open-drain bidirectional i/o cell is enabled. negated?the top-level de_b open-drain bidirectional i/o cell is disabled. timing assertion?asserted for three j_tclk periods upon processor entry into debug mode. jd_mclk_on i processor clock on. driven by system-level clock control logi c to indicate the m_clk input state state meaning asserted?the processor?s m_clk input is active. negated?the processor?s m_clk input is not active. timing assertion?synchronized to j_tclk and provided as an osr status bit. jd_watchpoint [0:7] o watchpoint events. indicate whether a watchpoint occurred. each debug address compare function (iac1?iac4, dac1?dac2), and debug counter event (dcnt1?dcnt2) is capable of triggering a watchpoint output. state meaning asserted?a watchpoint occurred negated?no watchpoint occurred
external core complex interfaces UM0434 260/391 table 184 lists interface signals that assist in implementing a real-time development tool capability with a controller that is external to the core . these signals are described in chapter 12.11: nexus3 pin interface on page 371 .? table 185 lists the primary jtag interface signals. these signals are usually connected directly to device pins (except for j_tdo , which needs tri-state and edge support logic), unless jtag tap controllers are concatenated. table 186 describes jtag interface signals. table 184. core development support (nexus3) signals signal type description nex_mcko o nexus3 clock output nex_rdy_b o nexus3 ready output nex_evto_b o nexus3 event-out output nex_evti_b i nexus3 event-in input nex_mdo[n:0] o nexus3 message data output nex_mseo_b[1:0] o nexus3 message start/end output table 185. jtag primary interface signals signal name type description j_trst_b i jtag test reset j_tclk i jtag test clock j_tms i jtag test mode select j_tdi i jtag test data input j_tdo o test data out to master controller or pad j_tdo_en o enables tdo output buffer. j_tdo_en is asserted when the tap controller is in the shift_dr or shift_ir state. table 186. descriptions of jtag interface signals signal i/o signal description j_tdi i jtag/once serial input. provides data and commands to the once controller. data is latched on the rising edge of j_tclk . data is shifted into the once serial port lsb first. j_tclk i jtag/once serial clock. supplie s the serial clock to the once control block. the serial clock provides pulses required to shift data and commands into and out of the once serial port (data is clocked into the once on the rising edge and is clocked out of the once serial port on the rising edge). the debug seri al clock frequency must not exceed 50% of the processor clock frequency.
UM0434 external core complex interfaces 261/391 j_tdo o jtag/once serial output. serial data is read from the once block through j_tdo . state meaning data is shifted out the on ce serial port lsb first. timing when data is clocked out of the once serial port, j_tdo changes on the rising edge of j_tclk . the j_tdo output is always driven. an external system-level tdo pin may be three-statable and should be actively driven in the shift-ir and shift-dr cont roller states. j_tdo_en indicates when an external tdo pin should be enabled, and is asserted during the sh ift-ir and shift-dr controller states. in addition, for ieee1149 compliance, the system-level pin should change state on the falling edge of tclk. j_tms i jtag/once test mode select. us ed to cycle through states in the once debug controller. toggling j_tms while clocking with j_tclk controls transitions through the tap state controller. j_trst_b i jtag/once test reset. resets the once controller externally by placing it in the test-logic- reset state. the following information details additional signals that can support external jtag data registers using the core tap controller. signal name type description j_tst_log_rst o indicates the tap controller is in the test-l ogic-reset state j_rti o jtag controller run-test/idle state j_capture_ir o indicates the tap controller is in the capture ir state j_shift_ir o indicates the tap controller is in shift ir state j_update_ir o indicates the tap controller is in update ir state j_capture_dr o indicates the tap controller is in the capture dr state j_shift_dr o indicates the tap controller is in shift dr state j_update_gp_reg o updates jtag controller general-purpose data register j_gp_regsel[0:11] o general-purpose external jtag register select j_en_once_regsel o external enable once register select j_key_in i serial data from external key logic j_nexus_regsel o external nexus register select j_lsrl_regsel o external lsrl register select j_serial_data i serial data from external jtag register(s) j_tst_log_rst o test-logic-reset. indicates whether the t ap controller is in te st-logic-reset state. state meaning asserted?the tap controller is in test-logic-reset state. negated?the tap controller is not in test-logic-reset state. j_rti o run-test/idle. indicates whether the tap c ontroller is in the run-test/idle state. state meaning asserted?the tap controller is in run-test/idle state. negated?the tap controller is not in run-test/idle state. j_capture_ir o capture ir. indicates whether the tap co ntroller is in the capture_ir state. state meaning asserted?the tap controller is in capture_ir state. negated?the tap controller is not in capture_ir state. j_shift_ir o shift ir. indicates whether the tap co ntroller is in the shift_ir state. state meaning asserted?the tap controller is in shift_ir state. negated?the tap controller is not in shift_ir state. table 186. descriptions of jtag interface signals (continued) signal i/o signal description
external core complex interfaces UM0434 262/391 j_update_ir o update ir. indicates the tap contro ller is in the update_ir state. state meaning asserted?the tap controller is in update_ir state. negated?the tap controller is not in update_ir state. j_capture_dr o capture dr. indicates whether the tap c ontroller is in the capture_dr state. state meaning asserted?the tap controller is in capture_dr state. negated?the tap controller is not in capture_dr state. j_shift_dr o shift dr. indicates whether the tap c ontroller is in the shift_dr state. state meaning asserted?the tap controller is in shift_dr state. negated?the tap controller is not in shift_dr state. j_update_gp_reg o update dr. indicates whether the tap controller is in the update_dr state. state meaning asserted?the tap controller is in t he update_dr state, and ocmd[r/w] is low (write command). j_gp_regsel[0:11] should be monitored to see which register, if any, needs updating. negated?the tap controller is not in the update_dr state. j_gp_regsel o register select. decoded from the ocmd[rs] . they are used to specify which external general-purpose jtag register to access using the core tap controller. signal name type rs j_gp_regsel[0] o 0x70 j_gp_regsel[1] o 0x71 j_gp_regsel[2] o 0x72 j_gp_regsel[3] o 0x73 j_gp_regsel[4] o 0x74 j_gp_regsel[5] o 0x75 j_gp_regsel[6] o 0x76 j_gp_regsel[7] o 0x77 j_gp_regsel[8] o 0x78 j_gp_regsel[9] o 0x79 j_gp_regsel[10] o 0x7a j_gp_regsel[11] o 0x7b j_en_once_regsel o enable once register select. th is control signal can be used by external security logic to help control jd_enable_once . the external enable_once register should be muxed onto the j_serial_data input. during the shift_dr state, j_serial_data is supplied to j_tdo . state meaning asserted?a decode of ocmd[rs] indicates an external enable_once register is selected (0b1111110 encoding) for access using the core tap controller. j_nexus_regsel o external nexus register select. state meaning asserted?a decode of ocmd[rs] indicates an external nexus register is selected (0b1111100 encoding) for access using the core tap controller. negated?no nexus register is selected. j_lsrl_regsel o lsrl register select. state meaning asserted?a decode of ocmd[rs] indicates an external lsrl register is selected (0b1111101 encoding) for access using the core tap controller. table 186. descriptions of jtag interface signals (continued) signal i/o signal description
UM0434 external core complex interfaces 263/391 figure 32 shows an example for designing an external jtag register set using the inputs and outputs provided along with the jtag primary inputs. the main components are a clock generation unit, a jtag shifter (load, shift, hold, clr), the registers (load, hold, clr), and an input mux to the shifter for the serial output back to the core.the shifter and the registers may be as wide as the application warrants [0:x]. the length determines the number of states the tap controller is held in shift_dr (x+1). figure 32. example external jtag register design 9.3.2 jtag id signals table 187 shows the jtag id register unique to freescale as specified by the ieee 1149.1 jtag specification . note that bit 31 is the msb of this register. j_serial_data i serial data. receives serial data from external jtag registers. all external registers share this serial output back to the core. therefore it must be muxed using j_gp_regsel[0:11] , j_lsrl_regsel , and j_en_once_regsel . the data is internally routed to j_tdo . j_key_in i key data in. receives serial data from logic to indicate a key or other value to be scanned out in the shift_ir state when the current valu e in the ir is the enable_once instruction. this input is provided to assist in implementing security logic outside of the core, which conditionally asserts jd_en_once . during the shift_ir state, when jd_en_once is negated, this input is sampled on the rising edge of j_tclk , and, after a 2-clock delay, the data is internally routed to j_tdo . this allows provision of a key value via the j_tdo output following a transition from capture_ir to shift_ir. j_key_in provides the key value. table 186. descriptions of jtag interface signals (continued) signal i/o signal description shifter d data q reg0 q d reg1 q j_gp_regsel[1:0] s d 0 1 reg0_dat reg1_dat clk_reg0 2 clk_reg1 3 2. clk_reg0 = j_tclk & j_update_gp_reg & j_gp_regsel[0] 3. clk_reg1 = j_tclk & j_update_gp_reg & j_gp_regsel[1] si so j_serial_data j_tdi clk_shfter 1 1. clk_shfter = j_tclk & (j_s hift_dr | j_capture_dr) clk gen j_tclk j_gp_regsel[1:0] j_shift_dr j_update_gp_reg shift load j_capture_dr j_shift_dr j_capture_dr j_trst_b notes:
external core complex interfaces UM0434 264/391 the core shifts out a 1 as the first bit on j_tdo if the shift_dr state is entered directly from the test-logic-reset state, per the jtag specification, and informs any jtag controller that an id register exists on the part. the jtag id register is accessed by writing the ocmr (once command register) with the value 0x02 in ocmd[rs]. the jtag id bit, manufacturer id field, and design center number are fixed by the jtag consortium or freescale. the version numbers and the 2 msbs of the sequence number are variable and brought out to external ports. the 8 lsbs of the sequence number are variable and are strapped internally to track variations in processor deliverables. table 188 shows the inputs to the jtag id register that are input ports on the core. these bits can help a customer track revisions of a device using the core. table 189 describes the jtag id signals. table 187. jtag register id fields bit field type description value [31:28] variable version number variable [27:22] fixed design center number (e200z3) 01_1111 [21:12] variable sequence number variable [11:1] fixed motorola manufacturer id 000_0000_1110 0 fixed jtag id register identification bit 1 table 188. jtag id register inputs signal name type description j_id_sequence[0:1] i jtag id register (2 msbs of sequence field) j_id_version[0:3] i jtag id register version field table 189. descriptions of jtag id signals signal i/o signal description j_id_sequence[0:1] i jtag id sequence. corresponds to the two msbs of the 10-bit sequence number in the jtag id register. these inputs are normally static and are provided for the integr ator for further component variation identification. j_id_sequence[2:9] i jtag id sequence. internally strapped by eps to track variations in processor and module deliverables. each core deliverable has a unique sequence number. additionally, each revision of these modules can be identified by unique sequence numbers. eps ma intains a database of the sequence numbers. j_id_version[0:3] i jtag id version. corresponds to t he 4-bit version number in the jtag id register. these inputs are normally static. they are provided to the customer for strapping to facilitate identification of component variants.
UM0434 external core complex interfaces 265/391 9.4 internal signals table 190 lists internal signals that are mentioned in this manual. these signals are not directly accessible to the user, but are used in this document to help describe the general behavior of the core. 9.5 timing diagrams the following sections discuss various types of timing diagrams. 9.5.1 processor instruction/data transfers transfer of data between the core and peripherals involves the address bus, data buses, and control and attribute signals. the address and data buses are parallel, non-multiplexed buses, supporting byte, half word, 3-byte, word, and double-word transfers. all bus inputs and outputs are sampled and driven with respect to the rising edge of m_clk . the core moves data on the bus by issuing control signals and using a handshake protocol to ensure correct data movement. the memory interface operates in a pipelined fashion to allow additional access time for memory and peripherals. ahb transfers consist of an address phase that lasts only one cycle, followed by the data phase that may la st for one or more cycles, depending on the state of p_[d,i]_hready . table 190. internal signal descriptions signal name description p_addr[0:31] address bus. provides the address for a bus transfer. p_ta_b transfer acknowledge. indicates completion of a requested data transfer operation. an external device asserts p_ta_b to terminate the transfer. for the core to accept the transfer as successful, p_tea_b must remain high while p_ta_b is asserted. p_tea_b transfer error acknowledge. indicates that a transfer error condition has occurred and causes the core to immediately terminate the transfer. an external device asserts p_tea_b to terminate the transfer with error. p_tea_b has higher priority than p_ta_b . p_treq_b transfer request. the core drives this output to indicate that a new access has been requested. p_xfail_b store exclusive failure. an external agent causes assertion of p_xfail_b to indicate a failure of the store portion of an stwcx. for the current transfer. p_xfail_b is ignored if p_tea_b is asserted, because the store terminated with an error. assertion of p_xfail_b with p_ta_b does not cause an exception; it indicates that the store was not perfo rmed due to a loss of reservation (determined by an external agent). the cpu updates the condition code accordingly and clears any outstanding reservation. p_xfail_b may be asserted by reservation logic or as a result of a system bus transfer with a failure response that is passed back to the cpu from the bi u. the amba xfail response is signaled back to the cpu using this signal. see chapter 5.7: memory synchronization and reservation instructions on page 111 .? p_xfail_b is ignored for all transfers other than an stwcx. .
external core complex interfaces UM0434 266/391 read transfers consist of the following: a request cycle, where address and attributes are driven along with a transfer request one or more memory access cycles to perform accesses and return data to the cpu for alignment, sign or zero extension, and forwarding. write transfers consist of a request cycle, in which address and attributes are driven along with a transfer request; and of on e or more data drive cycles, in which write data is driven and external devices accept write data for the access. to support sustained single-cycle transfers, access requests can overlap. up to two access requests may be in progress during any cycle?one access outstanding and a second in the pending request phase. if access retraction is enabled via hid1[ard] = 0, the biu is free to change the current request at any time, even if part of a burst transfer. access requests are assumed to be accepted as long as either no access is in progress or an access is terminated during the same cycle when a new request is active ( p_[d,i]_hready asserted). when an access is accepted, the biu is free to change the current request. the local memory control logic is responsible for proper pipelining and latching of all interface signals to initiate memory accesses. the system hardware can use p_hresp[2:0] to signal, using the error response encoding, that the current bus cycle has an error when a fault is detected. error assertion requires a 2-cycle response. in the fi rst cycle of the response, p_hresp[2:0] are driven to indicate error and p_[d,i]_hready must be negated. during the following cycle, the error response must continue to be driven, and p_[d,i]_hready must be asserted. when the core recognizes a bus error condition for an access at the end of the first cycle of the 2-cycle error response, a subsequent pending access request may be removed by the biu driving p_[d,i]_htrans[2:0] to the idle state in the second cycle of the 2-cycle error response. not all pending requests are removed, however. when a bus cycle is terminated with a bus erro r, the core can enter storage error exception processing immediately following the bus cycle, or it can defer processing the exception. the instruction prefetch mechanism requests instruction words from the instruction memory unit before it is ready to execute them. if a bus error occurs on an instruction fetch, the core does not take the exception until it attempts to use the instruction. should an intervening instruction cause a branch, or should a task switch occur, the storage error exception for the unused access does not occur. a bus error te rmination for any write access or read access that references data specifically requested by the execution unit causes the core to begin exception processing. basic read transfer cycles during a read transfer, the core receives data from a memory or peripheral device. figure 33 shows functional timing for basic read transfers, and clock-by-clock descriptions of activity follow.
UM0434 external core complex interfaces 267/391 figure 33. basic read transfer?single-cycle reads, full pipelining clock 1 (c1)?the first read transfer starts in clock cycle 1. during c1, the core places valid values on the address bus and transfer attributes. the burst type ( p_[d,i]_hburst[2:0] ), protection control ( p_[d,i]_hprot[5:0] ), and transfer type ( p_[d,i]_htrans[1:0] ) attributes identify the specific access type. the transfer size attributes ( p_[d,i]_hsize[1:0] ) indicate the size of the transfer. the byte strobes ( p_[d,i]_hbstrb[7:0] ) are driven to indicate active byte lanes. the write ( p_[d,i]_hwrite ) signal is driven low for a read cycle. the core asserts a transfer request ( p_[d,i]_htrans = nonseq) during c1 to indicate that a transfer is being requested. because the bus is currently idle, (0 transfers outstanding), the first read request to addr x is considered taken at the end of c1. the default slave drives a ready/okay response for the current idle cycle. clock 2 (c2)?during c2, the addr x memory access takes place, using the address and attribute values that were driven during c1 to enable reading of 1 or more bytes of memory. read data from the slave device is provided on the p_[d,i]_hrdata inputs. the slave device responds by asserting p_[d,i]_hready to indicate that the cycle is completing, and it drives an okay response. another read transfer request is made during c2 to addr y ( p_[d,i]_htrans = nonseq), and because the access to addr x is completing, it is considered taken at the end of c2. clock 3 (c3)?during c3, the addr y memory access takes place, using the address and attribute values that were driven during c2 to enable reading of one or more bytes of memory. read data from the slave device for addr y is provided on the p_[d,i]_hrdata inputs. the slave device responds by asserting p_[d,i]_hready to indicate the cycle is completing, and it drives an okay response. another read transfer request is made during c3 to addr z ( p_[d,i]_htrans = nonseq), and because the access to addr y is completing, it is considered taken at the end of c3. clock 4 (c4)?during c4, the addr z memory access takes place, using the address and attribute values that were driven during c3 to enable reading of one or more bytes nonseq nonseq nonseq idle addr x addr y addr z single single single data x data y data z okay okay okay okay 12345 m_clk p_htrans p_addr,p_hprot p_hsize , p_hbstrb , etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
external core complex interfaces UM0434 268/391 of memory. read data from the slave device for addr z is provided on the p_[d,i]_hrdata inputs. the slave device responds by asserting p_[d,i]_hready to indicate the cycle is completing, and it drives an okay response. because the cpu has no additional outstanding requests, p_[d,i]_htrans indicates idle and the address and attribute signals are undefined. read transfer with wait state figure 34 shows an example of wait state operation. because signal p_[d,i]_hready for the first request (addr x ) is not asserted during c2, a wait state is inserted until p_[d,i]_hready is recognized (during c3). meanwhile, a subsequent request was generated by the cpu for addr y which is not taken in c2, because the previous transaction is still out standing. the a ddress and transfer attributes remain driven in cycle c3 and are taken at the end of c3 because the previous access is completing. data for addr x and a ready/okay response are driven back by the slave device. in cycle c4, a request for addr z is made. the request for access to addr z is taken at the end of c4, and during c5, the slave device provides the data and a ready/okay response. in cycle c5, no further accesses are requested. figure 34. read with wait-state, si ngle-cycle reads, full pipelining basic write transfer cycles during a write transfer, the core provides write data to a memory or peripheral device. figure 35 shows functional timing for basic write transfers. clock-by-clock descriptions of activity in figure 35 follow. nonseq nonseq nonseq idle addr x addr y addr z single single single data x data y data z okay okay okay okay okay 123456 m_clk p_htrans p_addr,p_hprot p_hsize , p_hbstrb , etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
UM0434 external core complex interfaces 269/391 figure 35. basic write transfers?single-cycle writes, full pipelining clock 1 (c1)?the first write transfer starts in clock cycle 1. during c1, the core places valid values on the address bus and transfer attributes. the burst type ( p_[d,i]_hburst[2:0] ), protection control ( p_[d,i]_hprot[5:0] ), and transfer type ( p_[d,i]_htrans[1:0] ) attributes identify the specific access type. the transfer size attributes ( p_[d,i]_hsize[1:0] ) indicate the size of the transfer. the byte strobes ( p_[d,i]_hbstrb[7:0] ) are driven to indicate active byte lanes. the write ( p_[d,i]_hwrite ) signal is driven high for a write cycle. the core asserts transfer request ( p_[d,i]_htrans = nonseq) during c1 to indicate that a transfer is being requested. because the bus is idle, (0 transfers outstanding), the first read request to addr x is considered taken at the end of c1. the default slave drives a ready/okay response for the current idle cycle. clock 2 (c2)?during c2, the write data for the access is driven and the addr x memory access occurs using the address and attribute values (driven during c1) to enable writing of one or more bytes of memory. the slave device responds by asserting p_[d,i]_hready to indicate the cycle is completing and drives an okay response. another write transfer request is made during c2 to addr y ( p_[d,i]_htrans = nonseq), and because the access to addr x is completing, it is considered taken at the end of c2. clock 3 (c3)?during c3, write data for addr y is driven, and the addr y memory access takes place using the address and attribute values (driven during c2) to enable writing of one or more bytes of memory. the slave device responds by asserting p_[d,i]_hready to indicate the cycle is completing and drives an okay response. another write transfer request is made during c3 to addr z ( p_[d,i]_htrans = nonseq), and because the access to addr y is completing, it is considered taken at the end of c3. clock 4 (c4)?during c4, write data for addr z is driven, and the addr z memory access takes place using the address and attribute values (driven during c3) to enable reading of one or more bytes of memory. the slave device responds by asserting p_[d,i]_hready to indicate the cycle is completing and drives an okay response. because the cpu has no more outstanding requests, p_[d,i]_htrans indicates idle and the address and attribute signals are undefined. nonseq nonseq nonseq idle addr x addr y addr z single single single data x data y data z okay okay okay okay 12345 m_clk p_htrans p_addr,p_hprot p_hsize , p_hbstrb , etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
external core complex interfaces UM0434 270/391 write transfer with wait states figure 36 shows an example write wait state operation. because p_[d,i]_hready for the first request (addr x ) is not asserted during c2, a wait state is inserted until p_[d,i]_hready is recognized (during c3). figure 36. write with wait-state, single-cycle writes, full pipelining meanwhile, the core generates a subsequent request for addr y which is not taken in c2, because the previous transaction is outstanding. the address, transfer attributes, and write data remain driven in cycle c3 and are taken at the end of c3 because a ready/okay response is driven back by the slave device for the previous access. in cycle c4, a request for addr z is made. the request for access to addr z is taken at the end of c4, and during c5, the slave device provides a ready/okay response. in c5, no further accesses are requested. nonseq nonseq nonseq idle addr x addr y addr z single single single data x data y data z okay okay okay okay okay 123456 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
UM0434 external core complex interfaces 271/391 read and write transfers figure 37 shows a sequence of read and write cycles. figure 37. single-cycle reads, si ngle-cycle write, full pipelining the first read request (addr x ) is taken at the end of cycle c1 because the bus is idle. the second read request (addr y ) is taken at the end of c2 because a ready/okay response is asserted during c2 for the first read access (addr x ). during c3, a request is generated for a write to addr y which is taken at the end of c3 because the second access is terminating. data for the addr z write cycle is driven in c4, the cycle after the access is taken, and a ready/okay response is signaled to complete the write cycle to addr z . nonseq nonseq nonseq idle addr x addr y addr z single single single data x data y data z okay okay okay okay 12345 m_clk p_htrans p_addr,p_hprot p_hsize , p_hbstrb , etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
external core complex interfaces UM0434 272/391 figure 38 shows another sequence of read and write cycles. this example shows an interleaved write access between two reads. figure 38. single-cycle read, write, read?full pipelining the first read request (addr x ) is taken at the end of cycle c1 because the bus is idle. the first write request (addr y ) is taken at the end of c2 because the first access is terminating (addr x ). data for the addr y write cycle is driven in c3, the cycle after the access is taken. also during c3, a request is generated for a read to addr z , which is taken at the end of c3 because the write acce ss is terminating. during c4, the addr y write access is terminated, and no further access is requested. nonseq nonseq nonseq idle addr x addr y addr z single single single data x data z data y okay okay okay okay 12345 m_clk p_htrans p_addr,p_hprot p_hsize , p_hbstrb , etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
UM0434 external core complex interfaces 273/391 figure 39 shows another sequence of read and write cycles. in this example, reads incur a single wait state. figure 39. multiple-cycle reads with wait-state, single-cycle writes, full pipelining the first read request (addr x ) is taken at the end of cycle c1 because the bus is idle. the second read request (addr y ) is not taken at the end of cycle c2 because no ready response is signaled and only one access can be outstanding (addr x ). it is taken at the end of c3 once the first read request has signaled a ready/okay response. the first write request (addr z ) is not taken during c4 because a ready response is not asserted during c4 for the second read access (addr y ). during c5, the request for a write to addr z is taken because the seco nd access is terminating. data for the addr z write cycle is driven in c6, the cycle after the access is taken. during c6, the addr z write access is terminated and the addr w write request is taken. during c7, data for the addr w write access is driven , and a ready/okay response is asserted to complete the write cycle to addr w . nonseq nonseq nonseq nonseq idle addr x addr y addr z addr w single single single single data x data y data z data w okay okay okay okay okay okay okay 12345678 m_clk p_htrans p_addr,p_hprot p_hsize , p_hbstrb , etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
external core complex interfaces UM0434 274/391 figure 40 shows another sequence of read and write cycles. in this example, reads incur a single wait state. figure 40. multi-cycle read with wait-state, single-cycle write, read with wait-state, single-cycle write, full pipelining - the first read request (addr x ) is taken at the end of cycle c1 because the bus is idle. the first write request (addr y ) is not taken at the end of cycle c2 because no ready response is signaled and only one access can be outstanding (addr x ). it is taken at the end of c3 once the first read request has signaled a ready/okay response. data for the addr y write cycle is driven in c4, the cycle after the access is taken. the second read request (addr z ) is taken during c4 because the addr y write is terminating. a second write request (addr w ) is not taken at the end of c5 because the second read access is not terminating, and it continues to drive the address and attributes into cycle c6. during c6, the addr z read access is terminated and the addr w write access is taken. in cycle c7, data for the addr w write access is driven . during c7, a ready/okay response is asserted to complete the write cycle to addr w . no further accesses are requested, so p_[d,i]_htrans signals idle. nonseq nonseq nonseq nonseq idle addr x addr y addr z addr w single single single single data x data z data y data w okay okay okay okay okay okay okay 12345678 m_clk p_htrans p_addr,p_hprot p_hsize , p_hbstrb , etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
UM0434 external core complex interfaces 275/391 misaligned accesses figure 41 shows functional timing for a misaligned read transfer. the read to addr x is misaligned across a 64-bit boundary. note that only half-word and word transfers may be misaligned; double-word transfers are always aligned. figure 41. misaligned read, read, full pipelining the first portion of the misaligned read transfer starts in c1. during c1, the core places valid values on the address bus and transfer attributes. the p_[d,i]_hwrite signal is driven low for a read cycle. the transfer size attributes ( p_[d,i]_hsize ) indicate the size of the transfer. even though the transfer is misaligned, the size value driven corresponds to the size of the entire misaligned data item. p_[d,i]_hunalign is driven high to indicate that the access is misaligned. the p_[d,i]_hbstrb outputs are asserted to indicate the active byte lanes for the read, which may not correspond to size and low-order address outputs. p_[d,i]_htrans is driven to nonseq. during c2, the addr x memory access takes place using the address and attribute values which were driven during c1 to enable reading of one or more bytes of memory. the second portion of the misaligned read transfer request is made during c2 to addr x+ (which is aligned to the next higher 64-bit boundary), and because the first portion of the misaligned access is completing, it is taken at the end of c2. the p_[d,i]_htrans signals indicate nonseq. the size value driven is the size of the remaining bytes of data in the misaligned read, rounded up (for the 3-byte case) to the next higher power of 2. the p_[d,i]_hbstrb signals indicate the active byte lanes. for the second portion of a misaligned transfer, p_[d,i]_hunalign is driven high for the 3-byte case (low for all others). the next read access is requested in c3 and p_[d,i]_htrans indicates nonseq. p_[d,i]_hunalign is negated, because this access is aligned. nonseq nonseq nonseq idle addr x addr x+ addr y single single single ** data x data x+ data y okay okay okay okay 12345 m_clk p_htrans p_addr,p_hprot p_hsize , p_hbstrb , etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
external core complex interfaces UM0434 276/391 figure 42 shows functional timing for a misaligned write transfer. the write to addr x is misaligned across a 64-bit boundary. note that only half-word and word transfers may be misaligned; double-word transfers are always aligned. figure 42. misaligned write, write, full pipelining the first portion of the misaligned write transfer starts in c1. during c1, the core places valid values on the address bus and transfer attributes. the p_[d,i]_hwrite signal is driven high for a write cycle. the transfer size attribute ( p_[d,i]_hsize ) indicates the size of the transfer. even though the transfer is misaligned, the size value driven corresponds to the size of the entire misaligned data item. p_[d,i]_hunalign is driven high to indicate that the access is misaligned. the p_[d,i]_hbstrb outputs are asserted to indicate the active byte lanes for the write, which may not correspond to size and low-order address outputs. p_[d,i]_htrans is driven to nonseq. during c2, data for addr x is driven, and the addr x memory access takes place using the address and attribute values that were driven during c1 to enable writing of one or more bytes of memory. the second portion of the misaligned write transfer request is made during c2 to addr x+ (which is aligned to the next higher 64-bit boundary), and because the first portion of the misaligned access is completing, it is taken at the end of c2. the p_[d,i]_htrans signals indicate nonseq. the size value driven is the size of the remaining bytes of data in the misaligned write, rounded up (for the 3-byte case) to the next higher power-of-2. the p_[d,i]_hbstrb signals indicate the active byte lanes. for the second portion of a misaligned transfer, p_[d,i]_hunalign is driven high for the 3-byte case (low for all others). the next write access is requested in c3 and p_[d,i]_htrans indicates nonseq. p_[d,i]_hunalign is negated, because this access is aligned. nonseq nonseq nonseq idle addr x addr x+ addr y single single single ** data x data x+ data y okay okay okay okay 12345 m_clk p_htrans p_addr,p_hprot p_hsize , p_hbstrb , etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
UM0434 external core complex interfaces 277/391 an example of a misaligned write cycle followed by an aligned read cycle is shown in figure 43 . it is similar to the example in figure 42 . figure 43. misaligned write, single cycle read transfer, full pipelining 9.5.2 burst accesses figure 44 shows functional timing for a burst read transfer. figure 44. burst read transfer nonseq nonseq nonseq idle addr x addr x+ addr y single single single ** data y data x data x+ okay okay okay okay 12345 m_clk p_htrans p_addr,p_hprot p_hsize , p_hbstrb , etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp nonseq seq seq seq ... addr x addr x+8 addr x+16 addr x+24 incr data x data x+8 data x+16 data x+24 okay okay okay okay okay burst read 123456 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
external core complex interfaces UM0434 278/391 the p_[d,i]_hburst signals indicate incr for all burst transfers. the p_[d,i]_hunalign signal is negated. p_[d,i]_hsize indicates 64-bits, and all eight p_[d,i]_hbstrb signals are asserted. the burst address is aligned to a 64-bit boundary and increments by double words. note that in this example four beats are shown, but in operation the burst may be of any length including only a single beat. note: bursts can be interrupted immediately at any time and can be followed by any type of cycle. no idle cycle is required. figure 45 shows functional timing for a burst read with wait-state transfer. figure 45. burst read with wait-state transfer the first cycle of the burst incurs a single wait-state. nonseq seq seq seq ... addr x addr x+8 addr x+16 addr x+24 incr data x data x+8 data x+16 data x+24 okay okay okay okay okay okay burst read with wait-state 1234567 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
UM0434 external core complex interfaces 279/391 figure 46 shows functional timing for a burst write transfer. figure 46. burst write transfer figure 45 shows functional timing for a burst write with wait-state transfer. figure 47. burst write with wait-state transfer nonseq seq seq seq ... addr x addr x+8 addr x+16 addr x+24 incr data x data x+8 data x+16 data x+24 okay okay okay okay okay burst write 123456 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp nonseq seq seq seq ... addr x addr x+8 addr x+16 addr x+24 incr data x data x+8 data x+16 data x+24 okay okay okay okay okay okay burst write with wait-state 1234567 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
external core complex interfaces UM0434 280/391 the first cycle of the burst incurs a single wait-state. data for the second beat of the burst is valid the cycle after the second beat is taken . figure 48 shows functional timing for a pair of burst read transfers. figure 48. burst read transfers note that in this example the first burst is two beats long and is followed immediately by a second burst which is unrelated to the first. note: bursts may be of any length (including a single beat) and may be followed immediately by any type of transfer. no idle cycles are required. nonseq seq nonseq seq ... addr x addr x+8 addr y addr y+8 incr data x data x+8 data y data y+8 okay okay okay okay okay burst read 123456 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
UM0434 external core complex interfaces 281/391 figure 49 shows functional timing for a burst read with wait-state transfer where the second beat to addr x+8 is retracted and replaced with a new burst transfer. figure 49. burst read with wait-state transfer, retraction the 1 st cycle of the burst incurs a si ngle wait state, & the burst is replaced by another burst. figure 50 shows functional timing for a burst write transfer. the 2 nd burst is only 1 beat long. figure 50. burst write transfers, single-beat burst this same scenario can occur for read bursts as well. nonseq seq seq seq idle addr x addr y+8 addr y+16 incr data x data y data y+8 data y+16 okay okay okay okay okay okay burst read with wait-state 1234567 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp addr y addr x+8 nonseq nonseq seq seq nonseq idle addr x addr x+8 addr x+16 addr y incr data x data x+8 data x+16 data y okay okay okay okay okay burst write 123456 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
external core complex interfaces UM0434 282/391 9.5.3 address retraction address retraction is the process of replacing a request with a new unrelated one. although the amba ahb protocol requires an access request to remain driven unchanged once presented on the bus, higher system performance may be obtained if this aspect of the protocol is modified to allow an access request to be changed before being taken. figure 57 shows an example of address retraction during wait state operation. signal p_[d,i]_hready for the first request (addr x ) is not asserted during c2, so a wait state is inserted during c3 until p_[d,i]_hready is recognized. meanwhile, a subsequent request has been generated by the cpu for addr y which is not taken in c2 since the previous transaction is still outstanding. the address and transfer attributes are retracted in cycle c3, and a new access request to addr z is requested and are taken at the end of c3 because the previous access is completing. data for addr x and a ready/okay response is driven back by the slave device. in cycle c4, a request for addr w is made. the request for access to addr w is taken at the end of c4; during c5, the data and a ready/okay response is provided by the slave device. in cycle c5, no further accesses are requested. figure 51. read transfer with wait-state, address retraction figure 52 shows functional timing for a burst read with wait-state transfer where the second beat to addr x+8 is retracted and replaced with a new burst transfer. nonseq nonseq nonseq idle addr x addr y addr w single single single data x data z data w okay okay okay okay okay read with wait-state, address retraction 123456 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp addr z nonseq
UM0434 external core complex interfaces 283/391 figure 52. burst read with wait-state transfer, retraction the first cycle of the burst incurs a single wa it-state, and the burst is replaced by another burst. replacement by a single access is also possible. address retraction does not occur on a reques ted write cycle, only on read cycles. it also may occur any time during a burst cycle. error termination operation the p_[d,i]_hresp[2:0] inputs signal an error termination for an access in progress. the error encoding is used with the assertion of p_[d,i]_hready to terminate a cycle with error. error termination is a two-cycle termination; the first cycle consists of signaling the error response on p_[d,i]_hresp[2:0] while holding p_[d,i]_hready negated, and during the second cycle, asserting p_[d,i]_hready while continuing to drive the error response on p_[d,i]_hresp[2:0] . this 2-cycle termination allows the biu to retract a pending access if it desires to do so. p_[d,i]_htrans may be driven to idle during the second cycle of the two- cycle error response , or may change to any other value, and a new access unrelated to the pending access may be requested. the cycle th at may have been previously pending while waiting for a response that terminates with error may be changed. it is not required to remain unchanged when an error response is received. nonseq seq seq seq idle addr x addr y+8 addr y+16 incr data x data y data y+8 data y+16 okay okay okay okay okay okay burst read with wait-state 1234567 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp addr y addr x+8 nonseq
external core complex interfaces UM0434 284/391 figure 53 shows an example of error termination. figure 53. read and write transfers: instruction read with error, data read, write, full pipelining the first read request (addr x ) is taken at the end of cycle c1 because the bus is idle. it is an instruction prefetch. the second read request (addr y ) is not taken at the end of c2 because the first access is still outstanding (no p_[d,i]_hready assertion). an error response is signaled by the addressed slave for addr x by driving error onto the p_[d,i]_hresp[2:0] inputs. this is the first cycle of the two cycle error response protocol. p_[d,i]_hready is asserted during c3 for the first read access (addr x ) while the error encoding remains driven on p_[d,i]_hresp[2:0] , terminating the access. the read data bus is undefined. in this example of error termination, the cpu continues to request an access to addr y . it is taken at the end of c3. during c4, read data is supplied for the addr y read, and the access is terminated normally during c4. also during c4, a request is generated for a write to addr z , which is taken at the end of c4 because the second access is terminating. data for the addr z write cycle is driven in c5, the cycle after the access is taken . during c5, a ready/okay response is si gnaled to complete the write cycle to addr z . in this example of error termination, a subsequent access remained requested. this does not always occur when certain types of transfers are terminated with error. the following figures outline cases where an error termination for a given cycle causes a pending request to be aborted prior to initiation. figure 54 shows another example of error termination. nonseq nonseq nonseq idle addr x addr y addr z single single single data x data y data z okay error error okay okay 123456 m_clk p_htrans p_addr,p_hprot p_hsize , p_hbstrb , etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
UM0434 external core complex interfaces 285/391 figure 54. data read with error, data write retracted, instruction read, full pipelining the first read request (addr x ) is taken at the end of cycle c1 because the bus is idle. it is a data read. the second request (write to addr y ) is not taken at the end of c2 because the first access is still outstanding (no p_[d,i]_hready assertion). an error response is signaled by the addressed slave for addr x by driving error onto the p_[d,i]_hresp[2:0] inputs. this is the first cycle of the two cycle error response protocol. p_[d,i]_hready is asserted during c3 for the first read access (addr x ) while the error encoding remains driven on p_[d,i]_hresp[2:0] , terminating the access. the read data bus is undefined. in this example of error termination, the cpu retracts the requested access to addr y by driving p_[d,i]_htrans signals to the idle state during the second cycle of the two-cycle error response. a different access to addr z is requested during c4 and is taken at the end of c4. during c5, read data is supplied for the addr z read, and the access is terminated normally. in this example of error termination, a subsequent access was aborted. nonseq nonseq idle nonseq idle addr x addr y addr z single single single data x data z okay error error okay okay 123456 m_clk p_htrans p_addr,p_hprot p_hsize , p_hbstrb , etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
external core complex interfaces UM0434 286/391 figure 55 shows another example of error termination, this time on the initial portion of a misaligned write. figure 55. misaligned write with error, data write retracted, burst read substituted, full pipelining the first portion of the misaligned write request is terminated with error. the second portion is aborted by the cpu during the second cyc le of the two cycle error response, and a subsequent burst read access to addr w becomes pending instead. nonseq nonseq idle nonseq seq seq seq idle addr x addr x+ addr w addr w+8 addr w+16 addr w+24 single single wrap 4 ** data w w+8 w+16 w +24 data x okay error error okay okay okay okay okay 12345678 m_clk p_htrans p_ addr,p_hprot p_hsize , p_hbstrb , etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
UM0434 external core complex interfaces 287/391 figure 56 shows another example of error termination, this time on the initial portion of a burst read. the aborted burst is followed by a burst write. figure 56. burst read with error termination, burst write the first portion of the burst read request is terminated with error. the second portion is aborted by the cpu during the second cycle of the two cycle error response, and a subsequent burst write access to addr y becomes pending instead. 9.5.4 address retraction address retraction is the process of replacing a request with a new unrelated one. although the amba ahb protocol requires an access request to remain driven unchanged once presented on the bus, higher system performance may be obtained if this aspect of the protocol is modified to allow an access request to be changed before being taken. figure 57 shows an example of address retraction during wait state operation. signal p_hready for the first request (addr x ) is not asserted during c2, so a wait state is inserted during c3 until p_hready is recognized. meanwhile, a subsequent request has been generated by the cpu for addr y which is not taken in c2 since the previous transaction is still outstanding. the address and transfer attributes are retracted in cycle c3, and a new access to addr z is requested and made at the end of c3 because the previous access is completing. data for addr x and a ready/okay response are driven back by the slave device. in cycle c4, a request for addr w is made. the request for access to addr w is taken at the end of c4; during c5, the data and a ready/okay response are provided by the slave device. in cycle c5, no further accesses are requested. nonseq seq idle nonseq seq seq seq idle addr x addr x+8 addr y addr y+8 addr y+16 addr y+24 wrap4 wrap4 data x data y y+8 y+16 y+24 okay error error okay okay okay okay okay 12345678 m_clk p_htrans p_addr,p_hprot p_hsize , p_hbstrb , etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp
external core complex interfaces UM0434 288/391 figure 57. read transfer with wait-state, address retraction figure 58 shows functional timing for a burst read with wait-state transfer where the second beat to addr x+8 is retracted and replaced with a new burst transfer. figure 58. burst read with wait-state transfer, retraction the first cycle of the burst incurs a single wa it-state, and the burst is replaced by another burst. replacement by a single access is also possible. nonseq nonseq nonseq idle addr x addr y addr w single single single data x data z data w okay okay okay okay okay read with wait-state, address retraction 123456 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp addr z nonseq nonseq seq seq seq idle addr x addr y+8 addr y+16 incr data x data y data y+8 data y+16 okay okay okay okay okay okay burst read with wait-state 1234567 m_clk p_htrans p_addr,p_hprot p_hsize, p_hbstrb, etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp addr y addr x+8 nonseq
UM0434 external core complex interfaces 289/391 address retraction does not occur on a reques ted write cycle, only on read cycles. it also may occur any time during a burst cycle. 9.5.5 power management figure 59 shows the relationship of the wake-up control signal p_wakeup to the relevant input signals. figure 59. wakeup control signal (p_wakeup) 9.5.6 interrupt interface figure 60 shows the relationship of the interrupt input signals to the cpu clock. the p_avec_b , p_extint_b , p_critint_b , and p_voffset[0:15] inputs must meet setup and hold timing relative to the rising edge of m_clk . in addition, during each clock cycle in which either p_extint_b or p_critint_b is asserted, p_avec_b and p_voffset[0:15] are required to be in a valid state for the highest priority interrupt requested. figure 60. interrupt interface input signals m_clk p_extint_b p_wakeup p_critint_b jd_de_b , p_ude , ocr[wkup] p_extint_b p_voffset[0:15] p_critint_b p_avec_b m_clk
external core complex interfaces UM0434 290/391 figure 61 shows the relationship between p_ipend and the interrupt request inputs. note that p_ipend is asserted combinationally from the p_extint_b and p_critint_b inputs. figure 61. interrupt pending operation figure 62 shows the relationships among p_iack, the interrupt request inputs, and exception vector fetching. figure 62. interrupt acknowledge operation case 1 m_clk p_extint_b p_ipend p_critint_b exception vector fetch pair vec a vec b a handler a +8 a +16 idle 1 outst. 2 outst. 1st inst pair int a handlr a hand + 8 int a hand addr int a hand + 8 12345 m_clk p_critint_b p_extint_b p_voffset[0:15] sample point p_iack p_avec_b p_treq_b p_addr attributes p_r / w p_tbusy_b p_data_in p_ta_b mmu access cache access cache miss
UM0434 external core complex interfaces 291/391 in this example, an external input interrupt is requested in cycle 1. the p_voffset[0:15] inputs are driven with the vector offset for ?a?, and p_avec_b is negated, indicating vectoring is desired. for this example, the bus is idle at the time of assertion. the cpu may sample a requested interrupt as early as the cycle in which it is initially request ed, and it does so in this example. the interrupt request,the vector offset, and the autovector input are sampled at the end of cycle 1. in cycle 3, the interr upt is acknowledged by the assertion of the p_iack output, indicating that the values present on interrupt inputs at the beginning of cycle 2 have been internally latched and committed for servicing. note that the interrupt vector lines have changed to a value of ?b? during cycle 2, and the p_critint_b input has been asserted by the interrupt controller. the vector number and autovector signals must be consistent with the higher priority critical input request, and thus must change when the state of the interrupt request inputs change. the p_iack output assertion in cycle 3 indicates that the values present at the rise of cycle 2 (vector ?a?) ha ve been committed to. during cycle 3, the cpu begins instruction fetching of the handler for vector ?a?. the new request for a subsequent critical interrupt ?b? was not received in time to be acted on first. it is acknowledged after the fetch for the external input interrupt handler is completed and has entered decode. note that the time between assertion of an interrupt request input and the acknowledgment of an interrupt may be multiple cycles, and the interrupt inputs may change during that interval. the cpu asserts the p_iack output to indicate the cycle at which an interrupt is committed to. in the following example, because the cpu was unable to acknowledge the external input interrupt during cycle 2 due to internal or external execution conditions, the critical input request was samp led. this case is shown in figure 63 . figure 63. interrupt acknowledge operation case 2 vec a vec b b handler b +8 idle 1 outst. 2 outst. int b handlr b hand + 8 int b hand addr int b hand + 8 12345 m_clk p_critint_b p_extint_b p_voffset[0:15] sample point p_iack p_avec_b p_treq_b p_addr attributes p_r/w p_tbusy_b p_data_in p_ta_b mmu access cache access cache miss
power management UM0434 292/391 10 power management this chapter describes the po wer management facilities as they are defined by book e and implemented in devices that contain the core. the scope of this chapter is limited to core complex features. additional power management capabilities as sociated with a device that integrates this core (referred to as an integrated device) are documented separately. 10.1 overview power management minimizes overall system power consumption. the core provides the ability to initiate power manage ment from external sources as well as through software techniques. table 191 describes core power states. table 191. power states state description active (default) all internal units on the core operate at fu ll processor clock speed. the core provides dynamic power management in which idle in ternal units may stop clocking automatically. halted instruction execution and bus activity are suspended, and most internal clocks are gated off. the core asserts p_halted to indicate it is in the halted state. before entering halted state, all outstanding bus transactions comp lete, and the cache?s store and push buffers are flushed. the m_clk input should remain running to allow further transitions into the power-down state if requested and to keep the time base operational if it is using m_clk as the clock source. power down (stopped) all core functional units except the time ba se unit and clock control state machine logic are stopped. m_clk may be kept running to keep the time base active and to allow quick recovery to full-on state. clocks are not running to functional units except to the time base. the core reaches power-down state a fter transitioning through halted state with p_stop asserted; at this point p_stopped output is asserted. additional power may be saved by disabling the time base by asserting p_tbdisable or by integrated logic stopping m_clk after the core is in power-down state and has asserted p_stopped . to exit power-down state, integrated logic must first restart m_clk . because the time base is off during power-down state, if m_clk is the clock source and is stopped, or if time base clocking is disabled by the assertion of p_tbdisable , system software must usually have to access an exter nal time base source af ter returning to the full-on state to reinitialize the time base unit . a time-base related interrupt source (such as the decrementer) cannot be used to exit low-power states. the core also provides the ability to clock the time base from an independent (but externally synchronized) clock source, which allows the time base to be maintained during the power-down state, and allows a time-base related interrupt to be generated to indicate an exit condition from the power-down state.
UM0434 power management 293/391 figure 64 is a power management state diagram. figure 64. power management state diagram 10.1.1 power management signals table 191 summarizes power management signals. more detailed informat ion is provided in chapter 9.5.5: power management on page 289 .? halted power-down ~ p_stop & p_halt p_stop ~ p_halt & ~ p_stop p_halt | p_stop ~ p_stop p_stop active ~ p_halt & ~ p_stop ( p_stopped asserted) ( p_halted asserted) table 192. descriptions of timer facility and power management signals signal i/o signal description p_halt i processor halt request. the active-high p_halt input requests that the core enter the halted state. p_halted o processor halted. the active-high p_halted output indicates that the core entered the halted state. p_stop i processor stop request. the active-high p_stop input requests that the core enter the stopped state. p_stopped o processor stopped. the active-high p_stopped output indicates that the core entered stopped state. p_doze p_nap p_sleep o low-power mode. these signals are asserted by the core to reflect the settings of the hid0[doze], hid0[nap], and hid0[sl eep] control bits when msr[we] is set. the core can be placed in a low-power state by forcing m_clk to a quiescent state, and brought out of lo w-power state by re-enabling m_clk . the time base facilities may be separately enabled or disabled using combinations of the timer facility control signals. p_wakeup o wakeup. used by external logic to remove the core and system logic from a low- power state. it can also indicate to the system clock controller that m_clk should be re-enabled for debug purposes. p_wakeup (or other system state) should be monitored to determine when to release the core (and system if applicable) from a low-power state. p_tbdisable i timer disable. used to disable the internal time base and decrementer counters. this signal can be used to freeze the state of the time base and decrementer during low power or debug operation.
power management UM0434 294/391 10.1.2 power management control bits software uses the register fields listed in table 193 to generate a request to enter a power- saving state and to choose the state to be entered. 10.1.3 software considerations for power management setting msr[we] generates a request to enter a power-saving state (doze, nap, or sleep). this state must be previously determined by setting the appropriate hid0 bit. setting msr[we] does not directly affect execution, but is reflected on p_doze , p_nap , and p_sleep , depending on the se tting of the hid0 doze, nap, and sl eep bits. note that the core is not affected by assertion of these signals directly. external system hardware may interpret the state of these signals and activate the p_halt and/or p_stop inputs to cause the core to enter a quiescent state, in which clocks may be disabled for low-power operation. to ensure a clean transition into and out of a power-saving mode, the following program sequence is recommended: sync mtmsr (we) isync loop:br loop an interrupt is typically used to exit a power-saving state. the p_wakeup output is used to indicate to the system logic that an interrupt (or a debug request) has become pending. system logic uses this output to re-enable the clocks and exit a low-power state. the interrupt handler is responsible for determining how to exit the low-power loop if one is used. p_tbclk i timer external clock. used as an alternate clock source for the time base and decrementer counters. selection of this clock is made using hid0[sel_tbclk] (see chapter 4.13.1: hardware implementat ion dependent register 0 (hid0) on page 84 ? ). p_tbint o timer interrupt status. indicates whether an internal timer facility unit is requesting an interrupt (tsr[wis] = 1 and t cr[wie] = 1, or tsr[dis] = 1 and tcr[die] = 1, or tsr[fis] = 1 and tcr[fie] = 1 ). may be used to exit low-power operation or for other system purposes. table 193. power management control bits bit description msr[we] used to qualify assertion of the p_doze , p_nap , and p_sleep outputs to the integrated logic. when msr[we] is negated, these si gnals are negated. if msr[we] is set, these pins reflect the state of t heir respective hid0 control bits. hid0[doze] the interpretation of the doze mode bit is done by the external integrated logic. doze mode on the core is intended to be the halted state with the clocks running. hid0[nap] the interpretation of the nap mode bit is done by the external integrated logic. nap mode on the core may be used for a power-down state with the time base enabled. hid0[sleep] the interpretation of the sleep mode bit is done by the external integrated logic. sleep mode on the core may be used for a power-down state with the time base disabled. table 192. descriptions of timer facility and power management signals (continued) signal i/o signal description
UM0434 power management 295/391 the vectored interrupt capab ility provided by the core ma y help determine whether an external hardware interrupt is used to perform the wake-up. 10.1.4 debug considerati ons for power management when a debug request is presented to the core when it is in either the halted or stopped state, p_wakeup is asserted, and when m_clk is provided to the cpu, it temporarily exits the halted or stopped state and enters debug mode, regardless of the assertion of p_halt or p_stop . the p_halted and p_stopped outputs are negated as long as the cpu remains in a debug session ( jd_debug_b asserted). when the debug session is exited, the cpu resamples the p_halt and p_stop inputs and re-enters halted or stopped state as appropriate.
debug support UM0434 296/391 11 debug support 11.1 introduction this chapter describes the debug features of the e200z3 core, including the software and hardware debug facilities, events , and registers. it also deta ils the external debug support features available and introduces the reader to the on-chip emulation circuitry (once) and its key attributes, that is, the interface signals, debug inputs, and outputs. this chapter also covers watchpoint support, mmu and cache op erations during debug, cache array access, and the basic steps for enabling, using, and exiting external debug mode. 11.2 overview internal debug support in the core allows for software and hardware debugging by providing debug functions such as instruction and data breakpoints and program trace modes. for software-based debugging, debug facilities consisting of a set of software-accessible debug registers and interrupt mechanis ms are provided. these facilit ies are also available to a hardware-based debugger that communicates using a modified ieee 1149.1 test access port (tap) controller and pin interface. when hardware debugging is enabled, the debug facilities are protected fr om software modification. software debug facilities are defi ned as part of book e. the co re supports a subset of these defined facilities. in addition to the book e?de fined facilities, the core provides additional flexibility and functionality in the form of de bug event counters, linked instruction and data breakpoints, and sequential debug event detecti on. these features are also available to a hardware-based debugger. the core also supports an external nexus real-time debug module. real-time system-level debugging is supported by an external nexus class 2, 3, or 4 module. definitions and features of this module are part of the system/platform specification and are not further defined in this chapter. additional information can be found in chapter 12: nexus3 module on page 329 .? 11.2.1 software debug facilities the debug facilities enab le hardware and software debug functions, such as instruction and data breakpoints and program si ngle-stepping. the debug facilit ies consist of a set of debug control registers (dbcr0?dbcr3), a set of address compare registers (iac1?iac4, dac1, and dac2), a configurable debug counter register (dbcnt), a debug status register (dbsr) for enabling and recording various kinds of debug events, and a special debug interrupt type built into the interrupt mechanism (see chapter 6.6.16: debug interrupt (ivor15) on page 180 ,? for more information). the debug facilities also provide mechanisms for software-controlled processor re set and for controlling the operation of the timers in a debug environment. software debug facilities are enabled by settin g the internal debug mo de bit, dbcr0[idm]. if dbcr0[idm] is set, debug events can occur and can be enabled to record exceptions in the dbsr. if enabled by msr[de], these exceptions cause debug interrupts. if dbcr0[idm] and dbcr0[edm] (edm represents the external debug mode bit) are cleared, no debug events occur and no status flags are set in dbsr unless already set. in addition, if dbcr0[idm] is cleared (or is overridden by dbcr0[edm] being set), no debug interrupts can occur, regardless of the contents of dbsr. a software debug interrupt handler can
UM0434 debug support 297/391 access all system resources and perform the necessary functions appropriate for system debugging. powerpc book e compatibility the core implements a subset of the powerpc book e internal debug features. the following restrictions on functionality are present: instruction address compares do not support compare on physical (real) addresses. data address compares do not support compare on physical (real) addresses. data value compares are not supported. 11.2.2 additional debug facilities in addition to the debug functi onality defined in book e, the core provides the capability to link instruction and data breakpoints. the core also provides a configurable debug event counter to allow debug exception generation and a sequential breakpoint control mechanism. the core also defines two new debug events (critical interrupt taken and critical return) for debugging around critical interrupts. in addition, the core implements the debug auxiliary processing unit (apu) which, when enabled, allows debug interrupts to use a dedicated set of save/restore registers (dsrr0 and dsrr1) to save state information when a debug interrupt occurs and restore this state information at the end of a debug interrupt handler with the rfdi instruction. 11.2.3 hardware debug facilities the core contains facilities that allow for external test and de bugging. a modified ieee 1149.1 control interface is used to communi cate with core resource s. this interface is implemented through a standard 1149.1 tap (test access port) controller. by using public instructions, the external debugger can freeze or halt the core, read and write internal state and debug facilities, single-step instructions , and resume normal execution. hardware debug is enabled by setting the external debug mode enable bit (dbcr0[edm]). setting dbcr0[edm] overrides the internal debug mode enable bit dbcr0[idm]. if the hardware debug facility is enabled, software is blocked from modifying t he debug facilities. in addition, because resources are owned by the hardware debugger, inconsistent values may be present if software attempts to read debug-related resources. when hardware debug is enabled (dbcr0[edm] = 1), the registers and resources described in chapter 11.3: debug registers ,? are reserved for use by the external debugger. the events described in chapter 11.3: debug registers ,? are also used for external debugging, but exceptions are not generated to running software. debug events enabled in the respective dbcr0?dbcr3 registers are recorded in the dbsr regardless of msr[de], and no debug interrupts are generated. instead, the cpu enters debug mode when an enabled event causes a dbsr bit to become se t. dbcr0[edm] may only be written through the once port. a program trace program counter fifo (pc fifo) is also provided to support program change-of-flow capture. to perform write accesses from the external hardware debugger, most debug resources (registers) require the cpu clock ( m_clk ) to be running.
debug support UM0434 298/391 figure 65 shows the core debug resources. figure 65. core debug resources 11.3 debug registers the debug facility regi sters are listed in table 194 and described in chapter 4.12: debug registers on page 69 .? pstat# attr# addr# j_tdo, j_tdo_en j_tdi j_tclk breakpoint and trace logic pipeline information j_tms dbg_dbgrq cpu_dbgack jd_watchpt[0:n] #internal signals to/from cpu only p_devt[1,2 ] j_trst_b jd_de_en jd_debug_b data# jd_en_once jd_de_b jd_mclk_on p_ude pc fifo debug registers and comparators once controller and serial interface table 194. debug registers mnemonic name spr number access privileged core specific dbcr0 debug control register 0 308 r/w yes no dbcr1 debug control register 1 309 r/w yes no dbc.r2 debug control register 2 310 r/w yes no dbcr3 debug control register 3 561 r/w yes yes dbsr debug status register 304 read/clear (1) ye s n o dbcnt debug counter register 562 r/w yes yes iac1 instruction address compare 1 312 r/w yes no
UM0434 debug support 299/391 11.4 software debug events and exceptions software debug events and exceptions are available if internal debug mode is enabled (dbcr0[idm] = 1) and not overridden by external debug mode (dbcr0[edm] = 0). when enabled, debug events cause debug exceptions to be recorded in the debug status register. specific event types are enabled by dbcr0?dbcr3. the unconditional debug event (ude) is an exception to this rule; it is always enabled. once a dbsr bit other than mrr and cnt1trg is set, if debug interrupts are enabled by msr[de], a debug interrupt is generated. the debug interrupt handler is responsible for ensuring that multiple repeated debug interrupts do not occur by clearing the dbsr as appropriate. certain debug events are not allowed to occur when msr[de] = 0 and dbcr0[edm] = 0. under these conditions, no debug exception oc curs and thus no dbsr bit is set. other debug events may cause debug exceptions and set dbsr bits regardless of the state of msr[de]. a debug interrupt is delayed until msr[de] is set. when a dbsr bit is set while msr[de] = 0 and dbcr0[edm] = 0, an imprecise debug event flag (dbsr[ide]) is also set to indicate that an exception bit in the dbsr was set while debug interrupts were disabled. the debug interrupt handler software can use this bit to determine whether dsrr0 holds the address associated with the instruction causing the debug exception or the address of the instruction that enabled a delayed debug interrupt by setting msr[de]. an mtmsr or mtdbcr0 , which causes both msr[de] and dbcr0[idm] to be set, enabling precise debug mode, may caus e an imprecise (delayed) debug exception to be generated due to an earlier recorded event in the dbsr. the following types of debug events are defined by book e: instruction address compare debug events data address compare debug events trap debug events branch taken debug events instruction complete debug events interrupt taken debug events return debug events unconditional debug events these events are described in further detail in the eref . iac2 instruction address compare 2 313 r/w yes no iac3 instruction address compare 3 314 r/w yes no iac4 instruction address compare 4 315 r/w yes no dac1 data address compare 1 316 r/w yes no dac2 data address compare 2 317 r/w yes no 1. the dbsr can be read using mfspr rd,dbsr . it cannot be directly written to. instead, dbsr bits corresponding to 1 bits in gpr( r s) can be cleared using mtspr dbsr,r s. table 194. debug registers (continued) mnemonic name spr number access privileged core specific
debug support UM0434 300/391 the core defines the following debug events, which are described in table 195 : the debug counter debug events dcnt1 and dcnt2 the external debug events devt1 and devt2 the critical interrupt taken debug event (cirpt) the critical return debug event (cret) the core debug framework supports most of these event types. the following book e? defined functionality is not supported: instruction address compare and data address compare real address mode data value compare mode a brief description of each of the debug event types is shown in table 195 . in these descriptions, dsrr0 and dsrr1 are used to store the address of the instruction following a load or store, assuming that the debug apu is enabled. if it is disabled, csrr0 is used.
UM0434 debug support 301/391 table 195. debug event descriptions event name type description instruction address compare event iac occurs when enabled and upon attempt ed execution of an instruction at an address that meets the criteria s pecified in the dbcr0, dbcr1,and iac n registers. instruction address compares may specif y user/supervisor mode and instruction space (msr[is]), along with an effective address, masked effective address, or range of effective addresses for comparison. this event can occur and be recorded in dbsr regardless of the setting of ms r[de]. iac events do not occur when an instruction would not have normally begun execution due to a higher priority exception at an instruction boundary. iac compares perform a 31-bit compar e for vle instruction pages, and 30-bit compares for booke instruction pages. each half-word fetched by the instruction fetch unit will be marked with a set of bits indicating whether an instruction address compare occurred on that half-word. debug exceptions will occur if enabled and a 16-bit instruction, or the first half-word of a 32-bit instruction, is tagged with an iac hit. for instruction fetches that miss in the tlb, book e pages are assumed, and a 30-bit compare is performed. data address compare event dac data address compare debug events occur if data address compare debug events are enabled and execution of a load or store class instruction or a cache maintenance instruction results in a data access with an address that meets the criteria specified in dbcr0, dbcr2, dac1, and dac2. data address compares may specify user/supervisor mode and data space (msr[ds]), along with an effective address, masked effective address, or range of effective addresses for comparison. this event can occur and be recorded in dbsr regardless of the setting of msr[de]. two address compare values (dac1 and dac2) are provided. in contrast to the book e definition, data address compare events on the core do not prevent the load or store instruction fr om completing. if a load or store class instruction completes success fully without a data tlb or data storage interrupt, data address compare exceptions are report ed at the completion of the instruction. if the exception results in a precise debug interrupt, the address value saved in dsrr0 (or csrr0 if the debug apu is disa bled) is the address of the instruction following the load or st ore class instruction. if a load or store class instruction does not complete successfully due to a data tlb or data storage exception, and a data address compare debug exception also occurs, the result is an imprecise debug interrupt, the address value saved in dsrr0 (or csrr0 if the debug apu is disabled) is the address of the load or store class instruction, and dbsr[ide] is set. in addition to occurring when dbcr0[idm] = 1, this can also occur when dbcr0[edm] = 1. dac events are not recorded or counted if an lmw or stmw instruction is interrupted before completion by a critical input or external input interrupt. ? dac events are not signaled on the following: ?the second portion of a misaligned load or store that is broken up into two separate accesses ?the tlbre , tlbwe , tlbsx , or tlbivax instructions
debug support UM0434 302/391 linked instruction address and data address compare event dac1lnk , dac2lnk data address compare debug events may be linked with an instruction address compare event by setting the dac1lnk and/ or dac2lnk control bits in dbcr2 to further refine when a data address compare debug event is generated. dac1 may be linked with iac1, and dac2 (when not used as a mask or range bounds register) may be linked with iac3. when linked, a dac1 (or dac2) debug event occurs when the same instru ction that generates the dac1 (or dac2) hit also generates an iac1 (or iac3) hit. when linked, the iac1 (or iac3) event is not recorded in the dbsr, regardless of whether a corresponding dac1 (or dac2) event occurs, or whether the iac1 (or iac3) event enable is set. when enabled and execution of a load or store class instruction results in a data access with an address, and that addre ss meets the criteria specified in dbcr0, dbcr2, dac1, and dac2, and the instruction also meets the criteria for generating an instruction address compare event, a linked data address compare debug event occurs. this event can occur and be recorded in dbsr regardless of the setting of msr[de]. the normal dac1 and dac2 status bits in the dbsr are used for recording these events. the iac1 and iac3 status bits are not set if the corresponding instruction address compare register is linked. linking is enabled using dbcr2 control bits. if data address compare debug events are used to control or modify operation of the debug counter, linking is also available, even though dbcr0 may not have enabled iac or dac events. also, instruction address compare events that are linked may still affect the debug counter (if enabled to) and may be used to ei ther trigger a counter or be counted, in contrast to being blocked from affecting the dbsr. linked dac events are not re corded or counted if an lmw or stmw instruction is interrupted before completion by a critical input or external input interrupt. trap debug event trap a trap debug event occurs if trap debug events are enabled (dbcr0[trap] = 1), a trap instruction ( tw, twi ) is executed, and the conditions specified by the instruction for the trap are met. this event can occur and be recorded in dbsr regardless of the setting of msr[de]. when a trap debug event occurs, dbsr[trap] is set. branch taken debug event brt a branch taken debug event occurs if branch taken debug events are enabled (dbcr0[brt] = 1) and execution is attempt ed of a branch instruction that will be taken (either an unconditional branch or a conditional branch whose branch condition is true), and msr[de] = 1 or dbcr0[edm] = 1. branch taken debug events are not recognized if msr[de] = 0 and dbcr0[edm] = 0 at the time of execution of the branch instruction and thus dbsr[ide] can not be set by a branch taken debug event. when a branch taken debug event is recognized, dbsr[brt] is set to record the debug exception, and the address of the branch instruction is recorded in dsrr0 (only when the interrupt is taken). table 195. debug event descriptions (continued) event name type description
UM0434 debug support 303/391 instruction complete debug event iac an instruction-complete debug event occurs if instruction-complete debug events are enabled (dbcr0[icmp] = 1), execution of any instruction is completed, and msr[de] = 1 or dbcr0[edm] = 1. if executio n of an instruction is suppressed due to the instruction causing some other e xception that is enabled to generate an interrupt, then the attempted execution of that instruction does not cause an instruction complete debug event. the sc instruction does not fall into the category of an instruction whose execution is s uppressed, since the instruction actually executes and then generates a system call in terrupt. in this case, the instruction complete debug exception is also set. when an instruction complete debug event is recognized, dbsr[icmp] is set to record the debug exception, and the address of the next instruction to be executed is recorded in dsrr0. instruction complete debug events ar e not recognized if msr[de] = 0 and dbcr0[edm] = 0 at the time of execution of the instruction; thus, dbsr[ide] is not generally set by an icmp debug event. one circumstance may cause dbsr[icmp] and dbsr[ide] to be set. this occurs when an embedded fpu round exception occurs. because the instruction is by definition completed (srr0 points to the following instruction), this interrupt takes higher priority than the debug interrupt so as not to be lost, and dbsr[ide] = 1 to indicate imprecise recognition of a debug inte rrupt. in this case, the debug interrupt is taken with srr0 pointing to the instruction following the instruction that generated the spefpu round e xception, and dsrr0 points to the round exception handler. in addition to occurring when dbcr0[idm] = 1, this circumstance can also occur when dbcr0[edm] = 1. instruction complete debug events are not generated by the execution of an instruction that sets msr[de] while db cr0[icmp] = 1, nor by the execution of an instruction that sets dbcr0[icmp] while msr[de] = 1 or dbcr0[edm] = 1. interrupt taken debug event irpt an interrupt-taken debug event occurs if interrupt-taken debug events are enabled (dbcr0[irpt] = 1) and a non-critical interrupt occurs. only non-critical class interrupts cause an interrupt-taken debug event. this event can occur and be recorded in dbsr re gardless of the setting of msr[de]. when an interrupt-taken debug event occurs, dbsr[irpt] is set to record the debug exception. dsrr0 holds the address of the non-critical interrupt handler. critical interrupt taken debug event cirpt a critical interrupt taken debug event occurs if critical interrupt taken debug events are enabled (dbcr0[cirpt] = 1) and a critical interrupt (other than a debug interrupt when the debug apu is disabled ) occurs. only critic al class interrupts cause a critical-interrupt-taken debug event. this event can occur and be recorded in dbsr regardless of the setting of ms r[de]. when a critical-interrupt-taken debug event occurs, dbsr[cirpt] bit is se t, ensuring that debug exceptions are recorded. dsrr0 holds the address of the critical interrupt handler. to avoid corruption of csrr0 or csrr1, this debug event should not normally be enabled unless the debug apu is also enabled. table 195. debug event descriptions (continued) event name type description
debug support UM0434 304/391 11.5 external debug support external debug support is supplied through the core?s once controller serial interface, which allows access to internal cpu register s and other system state while in external debug mode (dbcr0[edm] is set). all debug resources, including dbcr0?dbcr3, dbsr, iac1?iac4, dac1, dac2 and dbcnt are accessible through the serial on-chip emulation (once) interface in external debug mode. setting the dbcr0[edm] bit through the once interface enables external debug mode and disables software updates to the debug registers. when dbcr0[edm] is set, debug even ts enabled to set respective dbsr status return debug event ret a return debug event occurs if return debug events are enabled (dbcr0[ret] = 1) and an attempt is made to execute an rfi instruction. this event can occur and be recorded in dbsr regardle ss of the setting of msr[de]. when a return debug event occurs, the dbsr[ret] bit is set so the debug exceptions are recorded. if msr[de] = 0 and dbcr0[edm] = 0 when rfi executes (that is , before the msr is updated by the rfi ), dbsr[ide] is also set to record the imprecise debug event. if msr[de] = 1 when rfi executes, a debug interrupt occurs provided no higher priority exception is enabled to cause an interrupt. dsrr0 holds the address of the rfi instruction. critical return debug event cret a critical return debug event occurs if critical return debug events are enabled (dbcr0[cret] = 1) and an attempt is made to execute an rfci instruction. this event can occur and be recorded in dbsr regardless of the setting of msr[de]. when a critical return debug event occurs, the dbsr[cret] bit is set to record the debug exception. if msr[de] = 0 and dbcr0[edm] = 0 at th e time of the execution of the rfci (that is before the msr is updated by the rfci ), dbsr[ide] is also set to record the imprecise debug event. if msr[de] = 1 at the time of the execution of the rfci , a debug interrupt occurs provided no higher priority exception is enabled to cause an interrupt. debug save/restore register 0 is set to the address of the rfci instruction. note that this debug event should not normally be enabled unless the debug apu is also enabled to avoid corruption of csrr0 or csrr1. debug counter debug event dcnt1, dcnt2 a debug counter debug event occurs if debug counter debug events are enabled (dbcr0[dcnt1] = 1 or dbcr0[dcnt2] = 1), a debug counter is enabled, and a counter decrements to zero. this event can occur and be recorded in dbsr regardless of the setting of msr[de]. when a debug counter debug event occurs, dbsr[dcnt1] or dbsr[dcnt2] is set to record the debug exception. external debug event devt1, devt2 an external debug event occurs if external debug events are enabled (dbcr0[devt1] = 1 or dbcr0[devt2] = 1), and the respective p_devt1 or p_devt2 input signal transitions to the set state. this event can occur and be recorded in dbsr re gardless of the setting of msr[de]. when an external debug event occurs, dbsr[devt1] or dbsr[d evt2] is set to record the debug exception. unconditional debug event ude an unconditional debug event occurs when the unconditional debug event ( p_ude ) input transitions to the set state, and either dbcr0[idm] = 1 or dbcr0[edm] = 1. the unconditional debug event is the only debug event that does not have a corresponding enable bit for the event in dbcr0. this event can occur and be recorded in dbsr re gardless of the setting of msr[de]. when an unconditional debug event occurs, dbsr[ude] is set, so debug exceptions are recorded. table 195. debug event descriptions (continued) event name type description
UM0434 debug support 305/391 bits also cause the cpu to enter debug mode, as opposed to generating debug interrupts. in debug mode, the cpu is halted at a recoverable boundary, and an external debug control module may control cpu operation through the once logic. no debug interrupts can occur while dbcr0[edm] remains set. note: on the initial setting of dbcr0[edm], other bits in dbcr0 are unchanged. after dbcr0[edm] is set, all debug register resources may be subsequently controlled through the once interface. dbsr should be cleared as part of the process of enabling external debug activity. the cpu should be placed into debug mode through the ocr[dr] control bit before setting edm. this allows the debugger to cleanly write to the dbcrn registers and the dbsr to clear out any residual state/co ntrol information that could cause unintended operation. note: it is intended for the cpu to remain in external debug mode (dbcr0[edm] = 1) in order to single-step or perform other debug mode entr y/reentry through the ocr[dr], by performing once go+noexit commands, or by assertion of jd_de_b. note: dbcr0[edm] operation is blocked if the once operation is disabled (jd_en_once negated) regardless of whether it is set or cleared. th is means that if dbcr0[edm] was previously set and then jd_en_once is negated (this should not occur), entry into debug mode is blocked, all events are blocked, and watchpoints are blocked. due to clock domain design, the cpu clock ( m_clk ) must be active for writes to be performed to debug registers other than the once command register (ocmd), the once control register (ocr), or dbcr0[edm]. register read data is synchronized back to the j_tclk clock domain. the once c ontrol register provides th e capability of signaling the system level clock controller that the cpu clock should be activated if not already active. updates to dbcr n , dbsr, and dbcnt through the once interface should be performed with the cpu in debug mode to guarantee proper operation. due to the various points in the cpu pipeline where control is sa mpled and event handshaking is performed, it is possible that modifications to these registers while the cpu is running may result in early or late entry into debug mode and incorrect status information posted in dbsr. 11.5.1 once introduction the on-chip emulation circuitry (once/nexus class 1 interface) provides a means of interacting with the core and integrated system so that a user may examine registers, memory, or on-chip peripherals. once operation is controlled through an industry-standard ieee 1149.1 tap controller. by using jtag instructions, the external hardware debugger can freeze or halt the cpu, read and write internal state, and resume normal execution. the core does not contain ieee 1149.1 standard boundary cells on its interface, as it is a building block for further integration. it does not support the jtag-related boundary scan instruction functionality, although jtag public instructions may be decoded and signaled to external logic. the once logic provides for nexus class 1 stat ic debug capability (using the same set of resources available to software while the core is in internal debug mode), and is present in all e200z3-based designs. the once module also provides support for directly integrating a nexus class 2 or class 3 real-time debug unit with the core for development of real-time systems where traditional static debug is insufficient. the partitioning between a once module and a connected nexus module to provide real-time de bugging allows for capability and cost tradeoffs to be made. the core is designed to be a fully integratable module. the once tap controller and associated enabling logic are designed to allow concatenation with an existing jtag
debug support UM0434 306/391 controller if one is present in the system. thus, the core module can be easily integrated with existing jtag designs or as a stand-alone controller. to enable full once operation, the jd_enable_once input signal must be asserted. in some system integrations, this is automatic since th e input will be tied asserted. other integrations may require the execution of the enable once command through the tap and appropriate entry of serial data. refer to the documentation for the integrating device. the jd_enable_once input should not change state during a debug session, or undefined activity may occur. figure 67 shows the tap controller and tap registers implemented by the once logic. figure 66. core debug resources figure 67. once tap controller and registers the once controller is implemented as a 16-state finite state machine (fsm), shown in figure 68 , with a one-to-one correspondence to the states defined for the jtag tap controller. once mapped debug registers auxiliary data registers external data registers bypass register tap instruction register ta p controller j_trst_b j_tclk j_tms tdo mux logic j_tdi j_tdo j_tdo_en (once ocmd)
UM0434 debug support 307/391 figure 68. once controller as an fsm access to core processor registers and the contents of memory locations is performed by enabling external debug mode (setting dbcr0[edm]), placing the processor into debug mode, and scanning instructions and data into and out of the core cpu scan chain (cpuscr); execution of scanned instructions by the core is used as the method for accessing required data. memory locations may be read by scanning a load instruction into the core that references the desired memory location, executing the load instruction, and then scanning out the result of the load. other resources are accessed in a similar manner. the initial entry by the cpu into the debug state (or mode) from normal, stopped, halted, or checkstop states (all indicated by the once status register (osr) described in chapter : once status register (osr) on page 311 ? ) by assertion of one or more debug requests begins a debug session. the jd_debug_b output signal indicates that a debug session is in progress, and the osr indicates that the cpu is in the debug state. instructions may be single-stepped by scanning new values into the cpuscr and performing a once go+noexit command (see chapter : once command register (ocmd) on page 312 ? ). the cpu then temporarily exits the debug state (but not the debug session) to execute the capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select dr-scan run-test/idle test-logic-reset 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 0 0 00 0 0 0 0 0 0 0 0 0 select ir-scan
debug support UM0434 308/391 instruction and returns to the debug state (again indicated by the osr). the debug session remains in force until the final go+exit command is executed, at which time the cpu returns to its previous state (unless a new debug request is pending). a scan into the cpuscr is required before executing each go+exit or go+noexit command. 11.5.2 jtag/once signals the jtag/once interface is used to transfer once instructions and data to the once control block. depending on the resource being accessed, the cpu may need to be placed in debug mode. for resources outside the cpu block and contained in the once block, the processor is not disturbed and may continue execution. if a processor resource is required, an internal debug request ( dbg_dbgrq ) may be asserted to the cpu by the once controller, and causes the cpu to finish the instruction being executed, save the instruction pipeline information, enter debug mode, and wait for further commands. asserting dbg_dbgrq causes the chip to exit the low-powe r mode enabled by setting msr[we]. table 196 details the primary jtag/once interface signals. a full description of jtag signals is provided in chapter 9.3.2: jtag id signals .? 11.5.3 once internal interface signals the following sections describe the once interface signals to other internal blocks associated with the once controller. table 197 shows the once internal interface signals. table 196. jtag/once primary interface signals signal name i/o description j_trst_b i jtag test reset j_tclk i jtag test clock j_tms i jtag test mode select j_tdi i jtag test data input j_tdo o test data out to master controller or pad j_tdo_en o enables tdo output buffer. set when the tap controller is in the shift-dr or shift-ir state. table 197. once internal interface signals signal name i/o description cpu debug request ( dbg_dbgrq ) o the db g_dbgrq signal is set by the once control logic to request the cpu to enter the debug state. it may be set for a number of different conditions, and causes the cpu to fi nish the current instruction being executed, save the instruction pipeline information, enter debug mode, and wait for further commands. cpu debug acknowledge ( cpu_dbgack ) i the cpu_dbgack signal is set by the cpu upon entering the debug state. this signal is used as part of the handshake mechanism between the once control logic and the rest of the cpu. the cpu core may enter debug mode through either a software or hardware event.
UM0434 debug support 309/391 cpu address and attributes the cpu address and attribute information are used by an external nexus class 2?4 debug unit with information for real-time address trace information. cpu data the cpu data bus is used to supply an external nexus class 2?4 debug unit with information for real-tim e data trace capability. 11.5.4 once interface signals the following sections describe additional once interface signals to other external blocks such as a nexus controller and external blocks that may need information pertaining to debug operation. table 198 describes the once interface signals. table 198. once interface signals signal name i/o description once enable ( jd_en_once) i the once enable signal, jd_en_once, is used to enable the once controller to allow certain instructions and operations to be exec uted. assertion of th is signal enables the full once command set, as well as oper ation of control signals and once control register functions. when this signal is disabled, only the bypass, id and enable_once commands are executed by the once unit, and all other commands default to the bypass command. the osr is not visible when once operation is disabled. also ocr functions are also disabled, as is the operation of the jd_de_b input. secure systems may choose to leave jd_en_once negated until a security check has been performed. other systems should tie this signal asserted to enable full once operation. the j_en_once_regsel output signal is provided to assist external logic performing security checks. refer to chapter : once control register (ocr) on page 315 ,? for a description of the j_en_once_regsel output. the jd_en_once input must change state only du ring the test-logic-reset, run- test/idle, or update-dr tap states. a ne w value takes effect after one additional j_tclk cycle of synchronization. in addition, jd_enable_once must not change state during a debug session, or undefined activity may occur. once debug request ( jd_de_b) /event (jd_de_en ) i/o the system-level bidirectiona l open drain debug event pin, de_b , (not part of the interface described in chapter 9: external core complex interfaces on page 235 ? ) provides a fast means of entering the debug mode of operation from an external command controller (when input) as well as a fast means of acknowledging entry into debug mode of operation to an external command controller (when output). the assertion of this pin by a command controller causes the cpu core to finish the current instruction being executed, save the instruction pipeline information, enter debug mode, and wait for commands to be entered. if de_b was used to enter debug mode, de_b must be negated after the once controller responds with an acknowledge and before sending the first once command. the assertion of this pin by the cpu core acknowledges that it has entered the debug mode and is waiting for commands to be entered. to support operation of this system pin, the once logic supplies the jd_de_en output and samples the jd_de_b input when once is enabled ( jd_en_once set). assertion of jd_de_b causes the once logic to place the cpu into debug mode. once debug mode has been entered, the jd_de_en output is asserted for three j_tclk periods to signal an acknowledge; jd_de_en can be used to enable the open-drain pulldown of the system level de_b pin.
debug support UM0434 310/391 11.5.5 once controller and serial interface the once controller contains the once command register, the once decoder, and the status/control register. figure 69 is a block diagram of the once controller. in operation, the once command register acts as the instruction register (ir) for the tap controller, and all other once resources are treated as data registers (dr) by the tap controller. the command register is loaded by serially shifting in commands during the tap controller shift- ir state, and is loaded during the update-ir state. the command register selects a resource to be accessed as a data register (dr) during the tap controller capture-dr, shift-dr, and update-dr states. once debug output (jd_debug_b) o the once debug output jd_debug_b is used to indicate to on-chip resources that a debug session is in progress. peripherals and other units may use this signal to modify normal operation for the duration of a debug session, which may involve the cpu executing a sequence of inst ructions solely for the purpos e of visibility/system control that are not part of the normal instruction stream the cpu would have executed had it not been placed in debug mode. this signal is set the first time the cpu enters the debug state, and remains set until the cpu is released by a write to the core once command register (ocmd) wit h the go and ex bits set, a nd a register specified as either no register selected or the cpuscr. this signal remains set even though the cpu may enter and exit the deb ug state for each instruction executed under control of the once controller. see chapter : once command register (ocmd) on page 312 ,? for more information on the function of the go and ex bits. this signal is not normally used by the cpu. cpu clock on input (jd_mclk_on) i the cpu clock on input ( jd_mclk_on) is used to indicate that the cpu?s m_clk input is active. this input signal is expected to be driven by system logic external to the core, is synchronized to the j_tclk (scan clock) clock domain and presented as a status flag on the j_tdo output during the shift-ir state. external firmware may use this signal to ensure proper scan sequences occur to access debug resources in the m_clk clock domain. watchpoint events ( jd_watchpt[0:7] ) o the jd_watchpt[0:7] signals may be set by the once control logic to signal that a watchpoint condition has occurred. watchpoin ts do not cause the cpu to be affected. they are provided to allow external visibility only. watchpoint events are conditioned by the settings in dbcr0, dbcr1, and dbcr2. table 198. once interface signals (continued) signal name i/o description
UM0434 debug support 311/391 figure 69. once controller and serial interface once status register (osr) status information regarding the state of the cpu is latched into the osr when the once controller state machine enters the capture-ir state. when once operation is enabled, this information is provided on the j_tdo output in serial fashion when the shift-ir state is entered following a capture-ir. information is shifted out least-significant bit first. table 199. once status register (osr) table 200 describes once status register bits. . 01 2 3456789 field mclk err chkstop reset halt stop debug 0 1 table 200. osr field descriptions bits name description 0mclk m_clk status bit. reflects the logic level on the jd_mclk_on input signal after capture by j_tclk . 0 inactive state 1 active state 1err error. used to indicate that an error condition occurred during attempted execution of the last single-stepped instruction (go+noexit with cpuscr or no register selected in ocmd), and that the instruct ion may not have executed properly. this can occur if an interrupt (all classes including external , critical, machine check, storage, alignment, program, tlb, and so on) occurs while attempting to perform the instruction single-step. in this case , cpuscr contains information related to the first instruction of the interrupt handl er, and no portion of the handler will have executed. 2 chkstop checkstop mode. reflects the logic level on the cpu p_chkstop output after capture by j_tclk . once command register tdi tclk status and control registers tdo mode select once decoder register register cpu update read write control/ status
debug support UM0434 312/391 once command register (ocmd) the once command register (ocmd) is a 10-bit shift register that receives its serial data from the tdi pin and serves as the instruction register (ir). it holds the 10-bit commands to be used as input for the once decoder. ocmd is shown in table 202 . it is updated when the tap controller enters the update-ir state. it contains fields for controlling access to a resource, as well as contro lling single-step op eration and exit from once mode. although ocmd is updated during the update-ir tap controller state, the corresponding resource is accessed in the dr scan sequence of the tap controller, and as such, the update-dr state must be transitioned through for an access to occur. in addition, the update-dr state must also be transitioned through in order for the single-step and/or exit functionality to be performed, even though the command appears to have no data resource requirement associated with it. table 202 describes ocmd fields. . 3 reset reset mode. reflects the inverted logic level on the cpu p_reset_b input after capture by j_tclk . 4halt halt mode. reflects the logic level on the cpu p_halted output after capture by j_tclk . 5stop stop mode. reflects the logic level on the cpu p_stopped output after capture by j_tclk . 6debug debug mode. set once the cpu is in debug mode. it is negated once the cpu exits debug mode (even during a debug session). 7 ? reserved, set to 0 8 ? reserved, set to 0 for 1149.1 compliance 9 ? reserved, set to 1 for 1149.1 compliance table 201. ocmd fields 0123 9 field r/w go ex rs reset 0b10_0000_0010 on assertion of j_trst_b or m_por or while in test-logic-reset state table 200. osr field descriptions (continued) bits name description
UM0434 debug support 313/391 table 202. ocmd field descriptions bits name description 0r/w read/write. specifies the direction of data transfer. 0 write the data associated with the comm and into the register specified by rs 1 read the data contained in the register specified by rs note: r/w is generally ignored for read-only or write- only registers, although the pc fifo pointer is only guaranteed to be updated when r/w = 1. in addition, it is ignored for all bypass operations. when performing writes, most registers are samp led in the capture-dr state into a 32-bit shift register and subsequently shifted out on j_tdo during the first 32 clocks of shift-dr. 1go go. if the go bit is set, the chip executes the in struction which resides in the ir register in the cpuscr. to execute the instructio n, the processor leaves debug m ode, executes the instruction, and, if the ex bit is cleared, returns to debug mode immediately after execut ing the instruction. the processor goes on to normal operation if the ex bit is set, and no other debug request source is set. the go command is executed only if the operation is a read/write to cpuscr or a read/write to no register selecte. otherwise the go bit is ignored. the processor leaves debug mode after the tap controller update-dr state is entered. on a go+noexit operation, returning to debug mode is treated as a debug event; thus, exceptions such as machine checks and interrupts may take priority and prevent execution of the intended instruction. debug firmware should mask these exceptions as appropriate. osr[err] indicates such an occurrence. 0 inactive (no action taken) 1 execute instruction in ir
debug support UM0434 314/391 2ex exit. the exit command is executed only if t he go command is issued and the operation is a read/write to cpuscr or a read/wr ite to no register selected. otherwise, the ex bit is ignored. the processor leaves debug mode after the tap contro ller update-dr state is entered. note that if the dr bit in the once control register is set or remains set, or if a bit in the dbsr is set, or if a bit in the dbsr is set and dbcr0[edm] = 1 (external debug mode is enabled), then the processor may return to the debug mode without execution of an instruction, even though the ex bit was set. 0 remain in debug mode 1 leave debug mode. the processor leaves debug mode and resumes normal operation until another debug request is generated. 3?9 rs register select. defines which register is the sour ce for the read or the destination for the write operation. table 205 indicates the once register addresses. attempted writes to read-only registers are ignored. 000 0000?000 0001 reserved 000 0010 jtag id read?only 000 0011?000 1111 reserved 001 0000 cpu scan register cpuscr 001 0001 no register selected bypass 001 0010 once control register ocr 001 0011?001 1111 reserved 010 0000 instruction address compare 1 iac1 010 0001 instruction address compare 2 iac2 010 0010 instruction address compare 3 iac3 010 0011 instruction address compare 4 iac4 010 0100 data address compare 1 dac1 010 0101 data address compare 2 dac2 010 0110 reserved dvc1 future use 010 0111 reserved dvc2 future use 010 1000?010 1011 reserved 010 1100 debug counter register dbcnt 010 1101 debug pcfifo (pcfifo) read?only 010 1110?010 1111 reserved 011 0000 debug status register dbsr 011 0001 debug control register 0 dbcr0 011 0010 debug control register 1 dbcr1 011 0011 debug control register 2 dbcr2 011 0100 debug control register 3 dbcr3 011 0101?101 1111 reserved (do not access) 111 0000?111 1001 general purpose register selects [0?9] 111 1010?111 1011 reserved 111 1100 nexus3?access?see chapter 12: nexus3 module on page 329 .? 111 1101 reserved 111 1110 enable_once (1) 1. causes assertion of the j_en_once _regsel output. refer to chapter : once control register (ocr) on page 315 .? table 202. ocmd field descriptions (continued) bits name description
UM0434 debug support 315/391 the once decoder receives as input the 10-bit command from the ocmd and the status signals from the processor, and generates all the strobes required for reading and writing the selected once registers. single-stepping of instructions is performed by placing the cpu in debug mode, scanning appropriate information into the cpuscr, and setting the go bit (with the ex bit cleared) with the rs field indicating either the cpuscr or no register selected. after executing a single instruction, the cpu re-enters debug mode and awaits further commands. during single-stepping, exception conditions may occur if not properly masked by debug firmware (interrupts, machine checks, bus error conditions, and so on) and may prevent the desired instruction from being successfully executed. the osr[err] bit is set to indicate this condition. in these cases, values in the cpuscr correspond to the first instruction of the exception handler. additionally, while single-stepping, to prevent debug events from generating debug interrupts, dbcr0[edm] is internally forced to 1. also, during a debug session, dbsr and dbcnt are frozen from updates due to debug events regardless of dbcr0[edm]. they may still be modified during a debug session through a single-stepped mtspr instruction if dbcr0[edm] is cleared, or through once access if dbcr0[edm] is set. once control register (ocr) the ocr, shown in table 203 , forces the core into debug mode and enables/disables sections of the once control logic. it also provides control over the mmu during a debug session. (see chapter 11.7: mmu and cache operation during debug on page 327 .? ) the control bits are read/write. these bits are effective only while once is enabled ( jd_en_once set). table 204 describes once control register fields. table 203. once control register fields 0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 28 29 30 31 field ? i_dmdis ? i_dvle i_di i_dm i_de dmdis ? dw di dm dg de ? wkup fdb dr reset 0x0000_0000 on m_por , j_trst_b, or entering test-logic-reset state table 204. once control register bit definitions bits name description 0?7 ? reserved, should be cleared. 8i_dmdis instruction side debug mmu disable control bit. may be used to control whether the mmu is enabled or disabled during a debug session for instruction accesses. 0mmu not disabled for debug sessions. the mmu functions normally. 1mmu disabled for debug sessions. for inst ruction accesses, no address translation is performed (1:1 address mapping) and the tlb ime bits are taken from the ocr bits i_di, i_dm, and i_de. the sx and ux access permission control bits are set, allowing full access. when disabled, no tlb miss or tlb exceptions are generated for instruction accesses. external access errors can still occur. 9?10 ? reserved, should be cleared. 11 i_dvle instruction side debug tlb vle attribute bit. provides the vle attribute bit for when the mmu is disabled during a debug session.
debug support UM0434 316/391 12 i_di instruction side debug tlb i attribute bit. provid es the i attribute bit for instruction accesses when the mmu is disabled for instru ction accesses during a debug session. 13 i_dm instruction side debug tlb m attribute bit. provi des the m attribute bit to be used for instruction accesses when the mmu is disabled for in struction accesses during a debug session. 14 ? reserved, should be cleared. 15 i_de instruction side debug tlb e attribute bit. provides the e attribute bit for instruction accesses when the mmu is disabled for instru ction accesses during a debug session. 16 d_dmdis data side debug mmu disable control bit. controls whether the mmu is enabled normally or is disabled during a debug session for data accesses. 0 mmu not disabled for debug sessions. the mmu functions normally 1 mmu disabled for debug sessions. for data accesses, no address translation is performed (1:1 address mapping) and the tlb wimge bits are taken from the ocr bits d_dw, d_di, d_dm, d_dg, and d_de bits. the sr, sw, ur, and uw access permission control bits are set to allow full access. when disabled, no tlb miss or tlb exceptions are generated for data accesses. external access errors can still occur. 17?18 ? reserved, should be cleared. 19 d_dw data side debug tlb w attribute bit. provides the w attribute bit for data accesses when the mmu is disabled for data accesses during a debug session. 20 d_di data side debug tlb i attribute bit. provides the i attribute bit for data accesses when the mmu is disabled for data accesses during a debug session. 21 d_dm data side debug tlb m attribute bit. provides the m attribute bit for data accesses when the mmu is disabled for data accesses during a debug session. 22 d_dg data side debug tlb g attribute bit. provides the g attribute bit for data accesses when the mmu is disabled for data accesses during a debug session. 23 d_de data side debug tlb e attribute bit. provides the e attribute bit for data accesses when the mmu is disabled for data accesses during a debug session. 24?28 ? reserved, should be cleared. 29 wkup wakeup request bit. used to force the p_wakeup output to be asserted. to ensure that debug resources may be properly accessed by external hardware through scan sequences, debug firmware can use this control function to request that the chip-level clock controller restore the m_clk input to normal operation regardless of whether the core is in a low-power state. 30 fdb force breakpoint debug mode. determines whether the processor is operating in breakpoint debug enable mode. the processor may be placed in breakpoint debug enable mode by setting this bit. in breakpoint debug enable mode, execution of the bkpt pseudo-instruction causes the processor to ent er debug mode, as if the jd_de_b input had been asserted. fdb is qualified with dbcr0[edm], which must be set for fdb to take effect. 31 dr cpu debug request control. used to uncondition ally request the cpu to enter debug mode. the cpu indicates that debug mode has been entered via the data scanned out in the shift-ir state. 0 no debug mode request 1 unconditional debug mode request. the processo r enters debug mode at the next instruction boundary. table 204. once control register bit definitions (continued) bits name description
UM0434 debug support 317/391 11.5.6 access to debug resources resources contained in the once module that do not require the core to be halted for access may be accessed without interfering with processor execution. accesses to other resources such as the cpuscr require the core to be placed in debug mode to avoid synchronization hazards. debug firmware may ensure that it is safe to access these resources by determining the state of the core before access. note: a scan operation to update the cpuscr is required before exiting debug mode. some cases of write accesses other than accesses to the once command and control registers or dbcr0 [edm] require the m_clk to be running for proper operation. the once control register provides a means of signali ng this need to a system level clock control module. in addition, because the cpu may cause multiple bits of certain registers to change state, reads of certain registers while the cpu is running (for example, dbsr and dbcnt) may not have consistent bit settings unless read twice with the same value indicated. to guarantee that the contents are consistent, the cpu should be placed into debug mode, or multiple reads should be performed until consistent values have been obtained on consecutive reads. table 205 lists access requiremen ts for once registers. table 205. once register access requirements register name access requirements notes jd_en_once to be set dbcr0 [edm] = 1 m_clk active for write access cpu to be halted for read access cpu to be halted for write access enable_once n n n n ? bypass n n n n n cpuscr y y y y y dac1 y y y n * (1) dac2 y y y n * (1) dbcnt y y y n * (1) date read from dbcnt while the cpu is running may not be self-consistent due to synchronizati on across clock domains. dbcr0 y y y n * (1) *dbcr0[edm] access only requires jd_en_once set dbcr1 y y y n * (1) dbcr2 y y y n * (1) dbcr3 y y y n * (1)
debug support UM0434 318/391 11.5.7 methods for entering debug mode the osr indicates that the cpu has entered the debug mode through the debug status bit. the following sections describe how debug mode is entered assuming the once circuitry has been enabled. once operation is enabled by the assertion of the jd_en_once input (see table 195 ). dbsr y y y n * (1) reads of dbsr while the cpu is running may not give data that is self- consistent due to synchronization across clock domains. iac1 y y y n * (1) iac2 y y y n * (1) iac3 y y y n * (1) iac4 y y y n * (1) jtag id n n ? n ? read only ocr y n n n n osr y n ? n ? read only, accessed by scanning out ir while jd_en_once is set pc fifo y n ? n ? read only, updates frozen while ocmd holds pcfifo register encoding note: pcfifo cannot be updated while the once state machine is in test_logic_reset state cache debug access control (cdacntl) ynyyy cpu must be in debug mode with clocks running cache debug access data (cdadata) ynyyy cpu must be in debug mode with clocks running nexus3-access y n n n n external gprs y n n n n lsrl select y n ? ? ? system test logic implementation determines lsrl functionality 1. writes to these registers while the cpu is running may have unpredictable resu lts due to the pipelined nature of the operation and the fact that updates are not synchronized to a par ticular clock, instruction, or bus cycle boundary; therefore, it is strongly recommended to ensure the processor is first placed into debug mode before updates to these registers are performed. table 205. once register access requirements (continued) register name access requirements notes jd_en_once to be set dbcr0 [edm] = 1 m_clk active for write access cpu to be halted for read access cpu to be halted for write access
UM0434 debug support 319/391 table 206 describes the methods for entering debug mode. 11.5.8 cpu status and control scan chain register (cpuscr) a number of on-chip registers store the cpu pipeline status and are configured in a single scan chain for access by the once controller. cpuscr contains these processor resources, which are used to restore the pipeline and resume normal chip activity upon return from debug mode, as well as a mechanism for the emulator software to access table 206. methods for entering debug mode method name description external debug request during reset holding jd_de_b asserted while p_reset_b is asserted and holding it asserted following the negation of p_reset_b causes the core to enter debug mode. after receiving an acknowledge through the once status register debug bit, the external command controller should negate jd_de_b before sending the first command. note that in this case the core does not execute an instruction before entering debug mode, although the first instruction to be executed may be fetched before entering debug mode. in this case, all values in the debug scan chain are undefined and the external debug control module is responsible for proper initialization of th e chain before debug mode is exited. in particular, the exception processing associated with reset ma y not be performed when debug mode is exited; thus, the debug controller must initialize pc, msr, and ir to the image that the processor would have obtained in performing reset exception processing, or it must cause the appropriate bit reset to be re-asserted. debug request during reset setting ocr[dr] while p_reset_b is asserted causes the device to enter debug mode; the chip may fetch the first instruction of the reset interrupt handler but does not execute an instruction before entering debug mode. in this case, all values in the debug scan chain are undefined and the external debug control module is responsible for pr operly initializing the chain before debug mode is exited. in particular, interrupt processing as sociated with reset may not be performed when debug mode is exited; thus, the debug cont roller must initialize pc, msr, and ir to the image that the processor would have obtained in performing reset exception processing, or it must cause the appropriate reset to be re-asserted. debug request during normal activity setting ocr[dr] during normal chip activity causes the chip to finish execution of the current instruction and then enter debug mode. note that in this case the chip completes execution of the current instruction and stops after the newly fetched instruction enters the cpu instruction register. this process is the same for any newly fetched in struction, including instructions fetched by the interrupt processing or those aborted by the interrupt processing. debug request during halted or stopped state setting ocr[dr] when the device is in the halted or stopped state ( p_halted or p_stopped set) causes the cpu to exit the state and enter debug mode once the cpu clock m_clk has been restored. note that in this case, the cpu negates both the p_halted and p_stopped outputs. once the debug session has ended, the cpu returns to the state it was in before entering debug mode. to signal the chip-level clock generator to re-enable m_clk , the p_wakeup output is set whenever the debug block is asserting a debug request to the cpu due to ocr[dr] being set, or jd_de_b assertion, and remains set from then until the debug session ends ( jd_debug_b goes from set to negated). in addition, the status of the jd_mclk_on input (after synchronization to the j_tclk clock domain) may be sampled along with other status bits from the j_tdo output during the shift-ir tap controller state. this status may be used if necessary by external debug firmware to ensure that proper scan sequences occur to registers in the m_clk clock domain. software request during normal activity upon executing a ?bkpt? pseudo - instruction (for the core, defined to be an all zeros instruction opcode), when ocr [fdb] is set (debug mode ena ble control bit is true) and dbcr0[edm] = 1, the cpu enters debug mode after the instruction following the ?bkpt? pseudo - instruction has entered the instruction register.
debug support UM0434 320/391 processor and memory contents. figure 70 shows the block diagram of the pipeline information registers contained in the cpuscr. once debug mode has been entered, it is required to scan in and update this register before exiting debug mode. figure 70. cpu scan chain register (cpuscr) instruction register (ir) the instruction register provides a way to control the debug session by serving as a means of forcing in selected instructions and causing them to be executed in a controlled manner by the debug control block. the opcode of the next instruction to be executed when entering debug mode is contained in this register when the scan-out of this chain begins. this value should be saved for later restoration if continuation of the normal instruction stream is desired. on scan-in, in preparation for exiting debug mode, this regist er is filled with an instruction opcode selected by debug control software. by selecting appropriate instructions and controlling the execution of thos e instructions, the results of execution may be used to examine or change memory locations and processor registers. the debug control module external to the processor core controls execution by providing a single-step ca pability. once the debug session is complete and normal processing is to be resumed, this register may be loaded with the value or iginally scanned out. tdo tdi tck msr wbbrupper 32 32 031 031 pc 32 031 ir 32 031 ctl 32 031 wbbrlower 32 031
UM0434 debug support 321/391 control state register (ctl) the control state register (ctl), shown in table 207 , stores the value of certain internal cpu state variables before debug mode is entered. this register is affected by the operations performed during the debug session and should normally be restored by the external command controller when returning to normal mode. in addition to saved internal state variables, two of the bits are used by emulation firmware to control the debug process. in certain circumstances, emulation firmware must modify the content of this register as well as the pc and ir values in the cpuscr before exiting debug mode. these cases are described more specifically in the text after the table. table 207. control state register (ctl) 0 15 field internal state bits 16 19 20 21 22 23 24 25 26 27 28 29 30 31 field pcofstpcinv ffra irstat 0 irstat 1 irstat 2 irstat 3 irstat 4 irstat 5 irstat 6 irstat 7 irstat 8 irstat 9 table 208. ctl field definitions bits name description 0?15 internal state bits internal state bits.these control bits represen t the internal processor state and should be restored to their original value after a debug session is completed, that is, when a once command is issued with the go and ex bits set and not ignored. when performing instruction execution during a debug session (see chapter 11.2.1: software debug facilities on page 296 ? ), these bits should be cleared. 16?19 pcofst pc offset field. indicates whether the value in the pc portion of the cpuscr must be adjusted before exiting debug mode. due to the pipelin ed nature of the cpu, the pc value must be backed up by emulation software in certain ci rcumstances. the pcofst field specifies the value to be subtracted from the original val ue of the pc. this adjusted pc value should be restored into the pc portion of the cpuscr just before exiting debug mode with a go+exit. in the event the pcofst is non-zero, the ir should be loaded with a nop instruction instead of the original ir value; otherwise, the original va lue of ir should be restored (but see pcinv which overrides this field). 0000 no correction required 0001 subtract 0x04 from pc. 0010 subtract 0x08 from pc. 0011 subtract 0x0c from pc. 0100 subtract 0x10 from pc. 0101 subtract 0x14 from pc. all other encodings are reserved. 20 pcinv pc and ir invalid status bit. this status bit indicates that the values in the ir and pc portions of the cpuscr are invalid. exiting debug mode with the saved values in the pc and ir will have unpredictable results. debug firmware should initialize the pc and ir values in the cpuscr with desired values before exiting debug mode if this bit was set when debug mode was initially entered. 0 no error condition exists. 1 error condition exists. pc and ir are corrupted.
debug support UM0434 322/391 emulation firmware should modify the ctl, pc, and ir values in the cpuscr during execution of debug-related instructions as well as just before exiting debug with a go+exit 21 ffra feed forward ra operand bit. this control bit causes the content of the wbbr lower to be used as the r a ( r s for logical and shift operations) operand valu e of the first instru ction to be executed following an update of the cpuscr. this allo ws the debug firmware to update processor registers, initialize the wbbr lower with the desired value, set the ffra bit, and execute an ori rx,rx,0 instruction to the desired register. 0 no action 1 content of wbbr used as r a ( r s for logical and shift operations) operand value 22 irstat0 ir status bit 0.this control bit indicate s an error termination status for the ir. 0 no tea occurred on the fetch of this instruction. 1 a tea occurred on the fetch of this instruction 23 irstat1 ir status bit 1. indicates a tlb miss status for the ir. 0 no tlb miss occurred on the fetch of this instruction. 1 tlb miss occurred on the fetch of this instruction. 24 irstat2 ir status bit 2. indicates an instruction address compar e 1 event status for the ir. 0 no instruction address compare 1 event occurred on the fetch of this instruction. 1 an instruction address compare 1 event occurred on the fetch of this instruction. 25 irstat3 ir status bit 3. indicates an instruction address compar e 2 event status for the ir. 0 no instruction address compare 2 event occurred on the fetch of this instruction. 1 an instruction address compare 2 event occurred on the fetch of this instruction. 26 irstat4 ir status bit 4. indicates an instruction address compar e 3 event status for the ir. 0 no instruction address compare 3 event occurred on the fetch of this instruction. 1 an instruction address compare 3 event occurred on the fetch of this instruction. 27 irstat5 ir status bit 5. indicates an instruction address compar e 4 event status for the ir. 0 no instruction address compare 4 event occurred on the fetch of this instruction. 1 an instruction address compare 4 event occurred on the fetch of this instruction. 28 irstat6 ir status bit 6. this control bit indi cates a parity error status for the ir. 0 no parity error occurred on the fetch of this instruction. 1 a parity error occurred on the fetch of this instruction. 29 irstat7 ir status bit 7. indicates a precise exte rnal termination error status for the ir. 0 no precise external termination error occurred on the fetch of this instruction. 1 precise external termination error occu rred on the fetch of this instruction. 30 irstat8 ir status bit 8. indicates the vle status for the ir. irstat8 affects the behavior of irstat9. 0 ir contains a booke instruction. 1 ir contains a vle instruction, aligned in th e most significant portion of ir if 16-bit. 31 irstat9 ir status bit 9. indicates the vle byte-ordering error status for the ir or a book e misaligned instruction fetch, depending on the state of irstat8. 0 ir contains an instruction without a byte-ordering error and no misaligned instruction fetch exception has occurred (no mif). 1 if irstat8 = 0, a book e misaligned instruction fetch exception occurred while filling the ir. if irstat8 = 1, ir contains an instruction wit h a byte-ordering error due to mismatched vle page attributes, or due to e indicating little-endian for a vle page. table 208. ctl field definitions (continued) bits name description
UM0434 debug support 323/391 command. during the debug session, the ctl register should be written with the ffra bit set as appropriate and all other bits cleared, and with ir set to the value of the desired instruction to be executed. the pcinv status bit which was originally present when debug mode was first entered should be tested before exiting debug mode with a go+exit and, if set, the pc and ir initialized for performing whatever recovery sequence is appropriate for a faulted exception vector fetch. if the pcinv bit is cleared, the pcofst bits should be examined to determine whether the pc value must be adjusted. due to the pipelined nature of the cpu, the pc value must be backed up by emulation software in certain circumstances. the pcofst field specifies the value to be subtracted from the original value of the pc. this adjusted pc value should be restored into the pc portion of the cpuscr just before exiting debug mode with a go+exit. in the event that pcofst is non-zero, the ir should be loaded with a nop instruction (such as ori r0,r0,0 ) instead of the original ir valu e; otherwise, the original value of ir should be restored. note that when a correction is made to the pc value, it generally points to the last comp leted instruction, altho ugh that instruction will no t be re-executed. the nop instruction is executed instead, and instruction fetch and execution resumes at location pc+4. for ctl, the internal state bits should be restored to their original value. the irstatus bits should be cleared if the pc was adjusted. if no pc adjustment was performed, emulation firmware should determine whether irstat2?5 should be cleared to avoid re-entry into debug mode for an instruction breakpoint request. on exiting debug mode with go+exit, if one of these bits is set, debug mode is re-entered before any further instruction execution. program counter register (pc) the pc is a 32-bit register that stores the value of the program counter that was present when the chip entered debug mode. it is affected by the operations performed during debug mode and must be restored by the external command controller when the cpu returns to normal mode. pc normally points to the instru ction contained in the ir portion of cpuscr. if debug firmware wishes to redirect program flow to an arbitrary location, the pc and ir should be initialized to correspond to the first instruction to be executed on resumption of normal processing. alternatively, the ir may be set to a nop and the pc set to point to the location before the location at which it is desired to redirect flow to. on exiting debug mode the nop is executed, and instruction fetch and execution resumes at pc+4. write-back bus register (wbbr (lower) and wbbr (upper)) wbbr provides a way to pass operand information between the cpu and the external command controller. whenever the external command controller needs to read the contents of a register or memory location, it forces the chip to execute an instruction that brings that information to wbbr. wbbr lower holds the 32-bit result of mo st instructions including load data returned for a load or load with update instruction. fo r spe instructions that generate 64-bit results, wbbr lower holds the low-order 32 bits of the result. wbbr upper holds the updated effective ad dress calculated by a load with updat e instruction. for spe instructions that generate 64-bit results, wbbr upper holds the high-order 32 bits of the result. it is undefined for other instructions. as an example, to read the lower 32 bits of processor register r1, an ori r1,r1,0 instruction is executed, and the result value of the instruction is latched into wbbr lower . the contents of wbbr lower can then be delivered serially to the external command controller. to update a processor resource, this register is initia lized with a data value to be written, and an ori instruction is executed that uses this value as a substitute data value. the control state register ffra bit forces the value of the wbbr lower to be substituted for the normal rs
debug support UM0434 324/391 source value of the ori instruction, thus allowing updates to processor registers to be performed. (refer to chapter : control state register (ctl) on page 321 ,? for more details.). wbbr lower and wbbr upper are generally undefined on instructions that do not write back a result and, due to control issues, are not defined on lmw or branch instructions either. to read and write the entire 64 bits of a gpr, both wbbr lower and wbbr upper are used. for reads, an evslwi r n ,r n ,0 may be used. for writes, the same instruction may be used, but the ctl[ffra] bit must be set as well. note: msr[spe] must be set in order for th ese operations to be performed properly. machine state register (msr) the msr is a 32-bit register used to read/write the machine state register (msr). whenever the external command controller needs to save or modify the contents of the machine state register, this register is used. this register is affected by the operations performed during debug mode and must be restored by the external command controller when returning to normal mode. chapter 4: register model on page 38 ,? further describes the msr. 11.5.9 instruction address fifo buffer (pc fifo) to assist debugging and keep track of program flow, a first-in-first-out (fifo) buffer stores the addresses of the last eight instruction change-of-flow destinations that were fetched. these include exception vectoring to an exception handler and returns, as well as pipeline refills due to execution of the isync instruction. the pc fifo stores the addresses of the last eight instruction change-of-flow addresses that were actually taken. the fifo is implemented as a circular buffer containing eight 32- bit registers and one 3-bit counter. all the registers have the same address, but any read access to the fifo address causes the counter to increment, making it point to the next fifo register. the registers are serially available to the external command controller through the common fifo address. figure 71 shows the block diagram of the pc fifo.
UM0434 debug support 325/391 figure 71. once pc fifo the fifo is not affected by the operations performed during a debug session except for the fifo pointer increment when reading the fifo. when entering debug mode, the fifo counter is pointing to the fifo register containing the address of the oldest of the eight change-of-flow prefetches. when ocmd [rs] is loaded with the value corresponding to the pc fifo (010 1101), the current pointer value is captured into a temporary register. this temporary value (not the actual fifo counter) is incremented as fifo reads are performed. the first fifo read obtains the oldest address and the following fifo read returns the other addresses from the oldest to the newest (the order of execution). updates to the fifo are frozen whenever the ocmd register contains a command whose rs[0?6] field points to the pc fifo (010 1101) to allow firmware to read the contents of the pc fifo without placing the cpu into debug mode. after completing all accesses to the pc pc fifo register 0 tdo tck pc fifo register 1 pc fifo register 2 pc fifo register 3 pc fifo register 4 instruction fetch address circular buffer pointer pc fifo shift register pc fifo register 5 pc fifo register 6 pc fifo register 7
debug support UM0434 326/391 fifo, another ocmd value that does not select the pc fifo should be entered to allow the pc fifo to resume updating. to ensure fifo coherence, a complete set of eight reads of the fifo should be performed because each read increments the temporary fifo pointer, thus making it point to the next location. after eight reads the pointer points to the same location it pointed to before starting the read procedure. the temporary counter value captures the actual counter each time the ocmd rs field transitions to the value corresponding to the pc fifo (010 1101). the fifo pointer is reset to entry 0 when either j_trst_b or m_por is set. 11.5.10 reserved registers the reserved registers are used to control various test control logic. these registers are not intended for customer use. to preclude device and/or system damage, these registers should not be accessed. 11.6 watchpoint support the core supports the generation and signaling of watchpoints when operating in internal debug mode (dbcr0[idm] = 1) or in external debug mode (dbcr0[edm] = 1). watchpoints are indicated with a dedicated set of interface signals. the jd_watchpoint[0:7] output signals are used to indicate that a watchpoint has occurred. each debug address compare function (iac1?iac4, dac1 and dac2) and debug counter event (dcnt1 and dcnt2) can trigger a wa tchpoint output. the dbcr1, dbcr2, and dbcr3 control fields are used to configure watchpoints, regardless of whether events are enabled in dbcr0. watchpoints may occur whenever an associated event would have been posted in the debug status register if enabled. no explicit enable bits are provided for watchpoints; they are always enabled by definition (except during a debug session). if not desired, the base address values for these events may be programmed to an unused system address. msr[de] has no effect on watchpoint generation. external logic may monitor the assertion of these signals for debugging purposes. watchpoints are signaled in the clock cycle following the occurrence of the actual event. the nexus3 module also monitors assertion of these signals for various development control purposes. table 209. watchpoint output signal assignments signal name type description jd_watchpt[0] iac1 instruction address compare 1 watchpoint. set whenever an iac1 compare occurs regardless of whether iac1 compares are enabled to set dbsr status. jd_watchpt[1] iac2 instruction address compare 2 watchpoint. set whenever an iac2 compare occurs regardless of whether iac2 compares are enabled to set dbsr status. jd_watchpt[2] iac3 instruction address compare 3 watchpoint. set whenever an iac3 compare occurs regardless of whether iac3 compares are enabled to set dbsr status. jd_watchpt[3] iac4 instruction address compare 4 watchpoint. set whenever an iac4 compare occurs regardless of whether iac4 compares are enabled to set dbsr status.
UM0434 debug support 327/391 11.7 mmu and cache operation during debug normal operation of the mmu may be modified during a debug session using the once ocr. a debug session begins when the cpu initially enters debug mode and ends when a once command with go+exit is executed, releasing the cpu for normal operation. if desired during a debug session, the debug firmware may disable the translation process and may substitute default values for the access protection (ux, ur, uw, sx, sr, sw) bits, and values obtained from the once control register and page attribute (vle, w, i, m, g, e) bits normally provided by a matching tlb entry. in addition, no address translation is performed; instead, a 1:1 mapping of effective-to-real addresses is performed. when disabled during a debug session, tlb miss or tlb-related dsi conditions cannot occur. if the debugger desires to use the normal translation process, the mmu may be left enabled in the once ocr, and no rmal translation (including th e possibility of a tlb miss or dsi) remains in effect. the ocrdmdis, dw, di, dm, dg, and de control bits are used when debug mode is entered. refer to the bit definitions in the ocr (see chapter : once cont rol register (ocr) on page 315 ,? for more detail). these substituted page attribute bits control cache operation on accesses initiated during debug. no address translation is performed; instead, a 1:1 mapping between effective and real addresses is performed. 11.8 enabling, using, and exiting external debug mode: example the following steps show one possible scenario for a debugger wishing to use the external debug facilities. this simplified flow shows basi c operations and does not cover all potential methods in depth. enable external debug mode and initialize debug registers: 1. to enable once operation, the debugger should ensure that the jd_en_once is set. 2. write a value to ocr in which ocr[dr] and ocr[wkup ] are set. the tap controller must step through the proper states as outlined earlier. this step places the cpu in a jd_watchpt[4] dac1 (1) data address compare 1 watchpoint. set whenever a dac1 compare occurs regardless of whether dac1 compares are enabled to set dbsr status. jd_watchpt[5] dac2 (1) data address compare 2 watchpoint. set whenever a dac2 compare occurs regardless of whether dac2 compares are enabled to set dbsr status. j d_watchpt[6] dcnt1 debug counter 1 watchpoint. set whenever debug counter 1 decrements to zero regardless of whether dcnt1 co mpares are enabled to set dbsr status. jd_watchpt[7] dcnt2 debug counter 2 watchpoint. set whenever debug counter 2 decrements to zero regardless of whether dcnt2 co mpares are enabled to set dbsr status. 1. if the corresponding event is completely disabled in dbcr0, either load-type or store-type data accesses are allowed to generate watchpoints, otherwise watc hpoints are generated only for the enabled conditions. table 209. watchpoint output signal assignments (continued) signal name type description
debug support UM0434 328/391 debug state where it is halted and awaiting single-step commands or a release to normal mode. 3. scan out the osr value to determine that the cpu clock is running and the cpu has entered debug state. this can be done in conjunction with a cpuscr read. the osr is shifted out during the shift-ir state. the cpuscr is shifted out during the shift-dr state. the debugger should save the scanned-out value of cpuscr for later restoration. 4. select the dbcr0 register and update it with dbcr0[edm] set. 5. clear the dbsr status bits. 6. write appropriate values to the dbcr0?dbcr3, iac, dac, and dbcnt registers. note: the initial write to dbcr0 on ly affects the edm bit, so the remaining portion of the register must now be initialized, keeping the edm bit set. at this point the system is ready to begin debug operations. depending on the desired operation, different steps must occur. 1. optionally set the ocr[dmdis] control bit to ensure that no tlb misses occur while performing the debug operations. 2. optionally ensure that the values ente red into the msr portion of the cpuscr during the following steps cause interrupts to be disabled (clearing msr[ee] and msr[ce]). this ensures that external interrupt sources do not cause single-step errors. to single-step the cpu: 1. the debugger scans in either a new or a previously saved value of the cpuscr (with appropriate modification of the pc and ir as described in chapter : control state register (ctl) on page 321 ? ) with a go+noexit once command value. 2. the debugger scans out the osr with no register selected, go cleared, and determines that the pcu has re-entered the debug state and that no err condition occurred. to return the cpu to normal operation (without disabling external debug mode): 1. ocr[dmdis] and ocr[dr] should be cleared, leaving ocr[wkup] set. 2. the debugger restores the cpuscr with a previously saved value of the cpuscr (with appropriate modification of the pc and ir as described in chapter : control state register (ctl) on page 321 ? ), with a go+exit once command value. 3. ocr[wkup] may then be cleared. to exit external debug mode: 1. the debugger should place the cpu in the debug state through the ocr[dr] with ocr[wkup] set, scanning ou t and saving the cpuscr. 2. the debugger should write to dbcr0?dbcr3 as needed, likely clearing every enable except dbcr0[edm]. 3. the debugger should write the dbsr to a cleared state. 4. the debugger should rewrite the dbcr0 with all bits including edm cleared. 5. the debugger should clear ocr[dr]. 6. the debugger restores the cpuscr with the previously saved value of the cpuscr (with appropriate modification of the pc and ir as described in chapter : control state register (ctl) on page 321 ? ) with a go+exit once command value. 7. ocr[wkup] may then be cleared. note: these steps are only examples rather than an exact template for debugger operations.
UM0434 nexus3 module 329/391 12 nexus3 module the e200z3 nexus3 module pr ovides real-time developmen t capabilities for e200z3 processors in compliance with the ieee-isto nexus 5001-2003 standard. this module provides development support capabilities witho ut requiring the use of address and data pins for internal visibility. a portion of the pin interface (the jtag port) is also shared with the once/nexus1 unit. the ieee-isto 5001-2003 standard defines an extensible au xiliary port which is used in conjunction with the jtag port in e200z3 processors. 12.1 introduction 12.1.1 general description this chapter defines the auxiliary pin fu nctions, transfer protocols and standard development features of a class 3 device in compliance with the ieee-isto ne xus 5001- 2003 standard. the development features supported are program trace, data trace, watchpoint messaging, ownership trace, and read/write access through the jtag interface. the nexus3 module also supports two class 4 features: watchpoint triggering, and processor overrun control. 12.1.2 terms and definitions table 210 contains a set of terms and definitions associated with the nexus3 module. table 210. terms and definitions term description ieee-isto 5001 consortium and standard for r eal-time embedded system design. world wide web documentation at the nexus 5001? forum website. auxiliary port refers to nexus auxiliary port. us ed as auxiliary port to the ieee 1149.1 jtag interface. branch trace messaging (btm) visibility of addresses for take n branches and exceptions, and the number of sequential instructions executed between each taken branch. data read message (drm) external visibility of data reads to memory-mapped resources. data write message (dwm) external visibility of data writes to memory-mapped resources. data trace messaging (dtm) external visibility of how data flows through the embedded system. this may include drm and/or dwm. jtag compliant device complying to ieee 1149.1 jtag standard. jtag ir and dr sequence jtag instruction register (ir) scan to load an opcode value for selecting a development register. the jtag ir corresponds to the once command register (ocmd). the select ed development register is then accessed through a jtag data register (dr) scan.
nexus3 module UM0434 330/391 12.1.3 feature list the nexus3 module is comp liant with class 3 of the ieee-isto 5001-2003 standard. the following features are implemented: program trace through branch trace messaging (btm). displays program flow discontinuities, direct and indirect branches, and exceptions, allowing the development tool to interpolate what transpires between the discontinuities. thus static code may be traced. data trace by means of data write messaging (dwm) and data read messaging (drm). drm and dwm provide the capability for the development tool to trace reads and/or writes to selected internal memory resources. ownership trace by me ans of ownership trace messaging (otm). facilitates ownership trace by providing visibility of which proce ss id or operating system task is activated. an ownership trace message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow. run-time access to embedded processor registers and memory map through the jtag port. this allows for enhanced download/upload capabilities. watchpoint messaging th rough the auxiliary pins watchpoint trigger enable of program and/or data trace messaging auxiliary interface for hi gher data input/output: ? configurable, min/max, message data out pins, nex_mdo[n:0] ? one or two message start/end out pins, nex_mseo_b[1:0] ? one read/write ready pin, nex_rdy_b ? one watchpoint event pin, nex_evto_b ? one event in pin, nex_evti_b ? one message clock out (mcko) pin nexus1 the e200z3 (once) debug module. this module integrated with each e200z3 processor provides all static , core-halted, debug functionality. this module complies with class 1 of the i eee-isto 5001 standard. ownership trace message (otm) visibility of process/function that is currently executing. public messages messages on the auxiliary pins for meeting common visibility and controllability requirements. soc system-on-a-chip (soc) signifies all of the modules on a single die. this generally includes one or more processors with associated peripherals, interfaces, and memory modules. standard the phrase ?according to the standard? is used to indicate the ieee- isto 5001 standard. transfer code (tcode) message header that identifies the num ber and/or size of packets to be transferred and how to interpret each of the packets. watchpoint a data or instruction breakpoint that does not cause the processor to halt. instead, a pin is used to signal that the condition occurred. a watchpoint message is also generated. table 210. terms and definitions (continued) term description
UM0434 nexus3 module 331/391 registers for program trace, data trace, ownership trace, and watchpoint trigger all features controllable and configurable through the jtag port note: configuration of the message data out pins is controlled by the port control register at the soc level in multiple nexus implementations. for single nexus implementations, this configuration is controlled by dc1 within the e200z3 nexus3 module. in either implementation, full port mode (fpm?maximum number of mdo pins) or reduced port mode (rpm?minimum number of mdo pins ) is supported. this setting should not be changed while the system is running. the configuration of the message start/end out pins, 1 or 2, is determined at the soc integration level. this opti on is hard-wired based on soc bandwidth requirements. figure 72 shows the functional block diagram. figure 72. nexus3 functional block diagram nex_mseo0_ b nex_mcko core virtual bus ahb system bus nexus3 block nexus1 block (within core cpu) nex_mdo[n:0] j_tdo j_tdi j_tms j_tclk j_trst_b nex_evto_b nex_rdy_b nex_evti_b nex_mseo1_ b n+1 nex_aux_req[1 :0] npc_aux_gra nt 2 note: the nex_aux_req[1:0], npc_aux_grant and nex_aux_busy signals are used for inter-module nex_aux_bus y communication in a multiple nexus environment. they are not pins on the soc. ext_multi_nex_s el registers dma registers once debug breakpoint/ watchpoint control memory control control/status t registers instruction snoop i/o logic data snoop dma (r/w) message queues
nexus3 module UM0434 332/391 12.2 enabling nexus3 operation the nexus module is enabled by loadin g a single instruction, nexus3-access , into the jtag instruction register/once ocmd register . for the e200z3 nexus3 module, the ocmd value is 0b00_0111_1100. once enabled, the module is ready to accept control input through the jtag/once pins. the nexus module is disabled when the jtag state machine reaches the test-logic-reset state. this state can be reached by the assertion of the j_trst_b pin or by cycling through the state machine using the j_tms pin. the nexus module can also be disabled if a power-on reset (por) event occurs. if the nexus3 module is disabled, no trace output is provided, and the module disables auxiliary port output pins, nex_mdo[n:0] , nex_mseo[1:0] , and nex_mcko . nexus registers are not available for reads or writes. note: see nexus 3 integration guide for details on ieee-isto 5001 compliance output pins & multiple nexus modu le configurations. 12.3 tcodes supported the nexus3 pins allow for flexible transfer operations through public messages. a tcode defines the transfer format, the number and/or size of the packets to be transferred, and the purpose of each packet. the ieee-isto 5001-2003 standard defines a set of public messages. the nexus3 block supports the public tcodes seen in table 211 . each message contains multiple packets transmitted in the order shown in the table. table 211. public tcodes supported message name minimum packet size (bits) maximum packet size (bits) packet type packet description debug status 6 6 fixed tcode number = 0 (0x00) 44fixed source processor identifier (multiple nexus configuration) 8 8 fixed debug status register (ds[31?24]) ownership trace message 6 6 fixed tcode number = 2 (0x02) 44fixed source processor identifier (multiple nexus configuration) 32 32 fixed task/process id tag program trace?direct branch message 6 6 fixed tcode number = 3 (0x03) 44fixed source processor identifier (multiple nexus configuration) 1 8 variable number of sequential instructions executed since last taken branch
UM0434 nexus3 module 333/391 program trace?indirect branch message 6 6 fixed tcode number = 4 (0x04) 44fixed source processor identifier (multiple nexus configuration) 18variable number of sequential instructions executed since last taken branch 132variable unique part of target address for taken branches/exceptions data trace?data write message 6 6 fixed tcode number = 5 (0x05) 44fixed source processor identifier (multiple nexus configuration) 3 3 fixed data size. refer to table 215 . 1 32 variable unique portion of the data write address 1 64 variable data write value(s). see data trace section for details. data trace?data read message 6 6 fixed tcode number = 6 (0x06) 44fixed source processor identifier (multiple nexus configuration) 3 3 fixed data size. refer to table 215 . 1 32 variable unique portion of the data read address 1 64 variable data read value(s). see data trace section for details. error message 6 6 fixed tcode number = 8 (0x08) 44fixed source processor identifier (multiple nexus configuration) 5 5 fixed error code program trace?direct branch message with synchronization 6 6 fixed tcode number = 11 (0x0b) 44fixed source processor identifier (multiple nexus configuration) 18variable number of sequential instructions executed since last taken branch 1 32 variable full target address (leading zeros truncated) program trace?indirect branch message with synchronization 6 6 fixed tcode number = 12 (0x0c) 44fixed source processor identifier (multiple nexus configuration) 18variable number of sequential instructions executed since last taken branch 1 32 variable full target address (leading zeros truncated) table 211. public tcodes supported (continued) message name minimum packet size (bits) maximum packet size (bits) packet type packet description
nexus3 module UM0434 334/391 data trace?data write message with synchronization 6 6 fixed tcode number = 13 (0x0d) 44fixed source processor identifier (multiple nexus configuration) 3 3 fixed data size. refer to table 215 . 1 32 variable full access address (leading zeros truncated) 1 64 variable data write value(s). see data trace section for details. data trace?data read message with synchronization 6 6 fixed tcode number = 14 (0x0e) 44fixed source processor identifier (multiple nexus configuration) 3 3 fixed data size. refer to table 215 . 1 32 variable full access address (leading zeros truncated) 1 64 variable data read value(s). see data trace section for details. watchpoint message 6 6 fixed tcode number = 15 (0x0f) 44fixed source processor identifier (multiple nexus configuration) 8 8 fixed number indicating watchpoint source(s) resource full message 6 6 fixed tcode number = 27 (0x1b) 44fixed source processor identifier (multiple nexus configuration) 44fixed resource code. refer to table 213 . indicates which resource is the cause of this message. 132variable branch/predicate instruction history (see chapter 12.7.1: branch trace messaging (btm) on page 350 ? ) program trace?indirect branch history message 6 6 fixed tcode number = 28 (0x1c). see note below. 44fixed source processor identifier (multiple nexus configuration) 18variable number of sequential instructions executed since last taken branch 132variable unique part of target address for taken branches/exceptions 132variable branch/predicate instruction history (see chapter 12.7.1: branch trace messaging (btm) on page 350 ? ). table 211. public tcodes supported (continued) message name minimum packet size (bits) maximum packet size (bits) packet type packet description
UM0434 nexus3 module 335/391 table 212 shows error code encodings used when reporting an error through the nexus3 error message. program trace?indirect branch history message with synchronization 6 6 fixed tcode number = 29 (0x1d). see note below. 44fixed source processor identifier (multiple nexus configuration) 18variable number of sequential instructions executed since last taken branch 1 32 variable full target address (leading zero (0) truncated) 132variable branch/predicate instruction history (see chapter 12.7.1: branch trace messaging (btm) on page 350 ? ). program trace? program correlation message 6 6 fixed tcode number = 33 (0x21) 44fixed source processor identifier (multiple nexus configuration) 44fixed event correlated with program flow. refer to table 214 . 18variable number of sequential instructions executed since last taken branch 132variable branch/predicate instruction history (see chapter 12.7.1: branch trace messaging (btm) on page 350 ? ). table 211. public tcodes supported (continued) message name minimum packet size (bits) maximum packet size (bits) packet type packet description table 212. error code encodings (tcode = 8) error code (ecode) description 00000 ownership trace overrun 00001 program trace overrun 00010 data trace overrun 00011 read/write access error 00101 invalid access opcode (nexus register unimplemented) 00110 watchpoint overrun 00111 program trace or data trace and ownership trace overrun 01000 program trace or data trace or ow nership trace and watchpoint overrun 01001?10111 reserved 11000 btm lost due to collision with higher priority message 11001?11111 reserved
nexus3 module UM0434 336/391 table 213 shows the encodings used for resource codes for certain messages. table 214 shows the event code encodings used for certain messages. table 215 shows the data trace size encodings used for certain messages. note: program trace can be implemented using either branch history/predicate instruction messages, or traditional direct/indirect branch messages, and the user can select between the two types of program trace. the advantages of each are discussed in chapter 12.7.1: branch trace messaging (btm) on page 350 .? if the branch history method is selected, the shaded tcodes above will not be messaged out. 12.4 nexus3 programmer?s model this section describes the nexus3 programme rs model. nexus3 registers are accessed using the jtag/once port in compliance with ieee 1149.1. see chapter 12.5: nexus3 register access through jtag/once on page 348 ,? for details on nexus3 register access. nexus3 registers and output signals are number ed using bit 0 as the least significant bit. this bit ordering is consist ent with the ordering defined by the ieee-isto 5001 standard. table 213. resource code encodings (tcode = 27) resource code (rcode) description 0000 program trace instruction counter reached 255 and was reset. 0001 program trace, branch/predicate instructio n history. this type of packet is terminated by a stop bit set after the last history bit. table 214. event code encodings (tcode = 33) event code (evcode) description 0000 entry into debug mode 0001 entry into low power mode (cpu only) 0010?1111 reserved 1110 entry into a vle page from a non-vle page 1111 entry into a non-vle page from a vle page table 215. data trace size encodings (tcode = 5, 6, 13, or 14) dtm size encodi ng transfer size 000 byte 001 half-word (2 bytes) 010 word (4 bytes) 011 double-word (8 bytes) 100 string (3 bytes) 101?111 reserved
UM0434 nexus3 module 337/391 table 216 shows the register map for the nexus3 module. 12.4.1 client select control register (csc) the csc register determines which nexus clie nt is under development. this register is present at the top-level soc nexus3 contro ller to select an on-chip nexus3 units table 217 shows the csc register. table 216. nexus3 register map nexus register nexus access opcode read/write read address write address client select control (csc) (1) 1. the csc and pcr registers are shown in this table as part of the nexus programmer?s model. they are only present at the top level soc nexus3 controller in a multiple nexus implementation, not in the e200z3 nexus3 module. the soc?s csc register is rea dable through nexus3, but the pcr is shown here for reference only. 2 pcr_index is a parameter determined by the soc. refer to the reference manual for the device integrating the e200z3 core for more information on how this parameter is implemented for each nexus module. 0x1 r 0x02 ? port configuration register (pcr) (1) pcr_index 2 r/w ? ? development control1 (dc1) 0x2 r/w 0x04 0x05 development control2 (dc2) 0x3 r/w 0x06 0x07 development status (ds) 0x4 r 0x08 ? read/write access control/status (rwcs) 0x7 r/w 0x0e 0x0f read/write access address (rwa) 0x9 r/w 0x12 0x13 read/write access data (rwd) 0xa r/w 0x14 0x15 watchpoint trigger (wt) 0xb r/w 0x16 0x17 data trace control (dtc) 0xd r/w 0x1a 0x1b data trace start address1 (dtsa1) 0xe r/w 0x1c 0x1d data trace start address2 (dtsa2) 0xf r/w 0x1e 0x1f data trace end address1 (dtea1) 0x12 r/w 0x24 0x25 data trace end address2 (dtea2) 0x13 r/w 0x26 0x27 reserved 0x14?0x3f ? 0x28?0x7e 0x29?0x7f table 217. client select control register 7430 field ? cs reset all zeros r/w read only number 0x1
nexus3 module UM0434 338/391 12.4.2 port configurat ion register (pcr) the port configuration register (pcr) shown in table 219 controls the basic port functions for all nexus modules in a multiple nexus en vironment. this includes clock control and auxiliary port width. all bits in this register are writable only once a fter system reset. note: the csc and pcr registers exist in a separa te module at the soc leve l in a multiple nexus environment. if the e200z3 ne xus3 module is the only nexus module, these registers are not implemented and the e200z3 nexus3-defined development control register 1 (dc1) is used to control nexus port functionality. table 218. csc field descriptions bits name description 7?4 ? reserved, should be cleared. 3?0 csc client select control 0xx = nexus client (soc level) table 219. port configuration register 31 30 29 28 26 25 0 field opc ? mck_en mck_div ? reset all zeros r/w read/write number pcr_index table 220. pcr field descriptions bits name description 31 opc output port mode control 0 reduced port mode configuration (minimum number of nex_mdo[n:0] pins defined by soc) 1 full port mode configuratio n (maximum number of nex_mdo[n:0] pins defined by soc) 30 ? reserved 29 mck_en mcko clock enable. see note below. 0 nex_mcko is disabled 1 nex_mcko is enabled 28?26 mck_div mcko clock divide ratio 000 nex_mcko is 1x processor clock freq. 001 nex_mcko is 1/2x processor clock freq. 010 reserved (default to 1/2x processor clock freq.) 011 nex_mcko is 1/4x processor clock freq. 100?110 reserved (default to 1/2x processor clock freq.) 111 nex_mcko is 1/8x processor clock freq. 25?0 ? reserved
UM0434 nexus3 module 339/391 12.4.3 development control register 1, 2 (dc1, dc2) the development control registers are used to control the basic development features of the nexus3 module. development cont rol register 1 is shown in table 221 and its fields are described in table 219 . table 221. development control register 1 (dc1) 31 30 29 28 27 26 25 24 23 8 7 5 4 3 2 0 field opc mck_div eoc ? ptm wen ? ovc eic tm reset all zeros r/w read/write number 0x2 table 222. dc1 field descriptions bits name description 31 opc output port mode control 0 reduced port mode configuration (minimum number of nex_mdo[n:0] pins defined by soc) 1 full port mode configuration (maximum number of nex_mdo[n:0] pins defined by soc) 30?29 mck_div mcko clock divide ratio. see note below. 00 nex_mcko is 1x processor clock freq. 01 nex_mcko is 1/2x processor clock freq. 10 nex_mcko is 1/4x processor clock freq. 11 nex_mcko is 1/8x processor clock freq. 28?27 eoc evto control 00 nex_evto_b upon occurrence of watchpoints (configured in dc2) 01 nex_evto_b upon entry into debug mode 10 nex_evto_b upon timestamping event 11 reserved 26 ? reserved 25 ptm program trace method 0 program trace uses traditional branch messages. 1 program trace uses branch history messages. 24 wen watchpoint trace enable 0 watchpoint messaging disabled 1 watchpoint messaging enabled 23?8 ? reserved 7?5 ovc overrun control 000 generate overrun messages 001?010 reserved 011 delay processor for btm/dtm/otm overruns 1xx reserved
nexus3 module UM0434 340/391 note: opc and mck_div must be modified only during system reset or debug mode to ensure correct output port and output clock functionality. it is also recommended that all other bits of dc1 be modified only in one of these two modes. development control register 2 is shown in table 223 and its fields are described in table 224 . the eoc bits in dc1 must be programmed to trigger evto on watchpoint occurrence for the ewc bits to have any effect. 12.4.4 development status register (ds) the development status registe shown in table 225 is used to report system debug status. when debug mode is entered or exited, or an soc- or e200z3-defined low-power mode is 4?3 eic evti control 00 nex_evti_b is used for synchronization (program trace/data trace) 01 nex_evti_b is used for debug request 1xreserved 2?0 tm trace mode 000no trace 1xxprogram trace enabled x1xdata trace enabled xx1ownership trace enabled table 222. dc1 field descriptions (continued) bits name description table 223. development control register 2 (dc2) 31 24 23 0 field ewc ? reset all zeros r/w read/write number 0x3 table 224. dc2 field descriptions bits name description 31?24 ewc evto watchpoint configuration 00000000no watchpoints trigger nex_evto_b 1xxxxxxxwatchpoint #0 (iac1 from nexus1) triggers nex_evto_b x1xxxxxxwatchpoint #1 (iac2 from nexus1) triggers nex_evto_b xx1xxxxxwatchpoint #2 (iac3 from nexus1) triggers nex_evto_b xxx1xxxxwatchpoint #3 (iac4 from nexus1) triggers nex_evto_b xxxx1xxxwatchpoint #4 (dac1 from nexus1) triggers nex_evto_b xxxxx1xxwatchpoint #5 (dac2 from nexus1) triggers nex_evto_b xxxxxx1xwatchpoint #6 (dcnt1 from nexus1) triggers nex_evto_b xxxxxxx1watchpoint #7 (dcnt2 from nexus1) triggers nex_evto_b 23?0 ? reserved
UM0434 nexus3 module 341/391 entered, a debug status message is transmitted with ds[31?25]. the external tool can read this register at any time. 12.4.5 read/write access cont rol/status register (rwcs) the read write access control/status register, shown in table 227 , provides control for read/write access. read/write access provides dma-like access to memory-mapped resources on the ahb system bus ei ther while the processor is halted, or during runtime. rwcs also provides read/write access status information; see table 229 . table 225. development status register (ds) 31 30 28 27 26 25 24 0 field dbg lpc lpc chk ? reset all zeros r/w read?only number 0x4 table 226. ds field descriptions bits name description 31 dbg e200z3 cpu debug mode status 0 cpu not in debug mode 1 cpu in debug mode ( jd_debug_b signal asserted) 30?28 lps e200z3 system low power mode status 000 normal (run) mode xx1 doze mode ( p_doze signal asserted) x1x nap mode ( p_nap signal asserted) 1xx sleep mode ( p_sleep signal asserted) 27?26 lpc e200z3 cpu low power mode status 00 normal (run) mode 01 cpu in halted state ( p_halted signal asserted) 10 cpu in stopped state ( p_stopped signal asserted) 11 reserved 25 chk e200z3 cpu checkstop status 0 cpu not in checkstop state 1 cpu in checkstop state ( p_chkstop signal asserted) 24?0 ? reserved, should be cleared. table 227. read write access control/status register (rwcs) 31 30 29 2726 242322 21 20 1615 2 1 0 field ac rw sz map pr ? cnt err dv reset all zeros r/w read/write number 0x7
nexus3 module UM0434 342/391 table 229 details the status bit encodings. 12.4.6 read/write access data register (rwd) the read/write access data register, shown in table 230 , provides the data to/from system bus memory-mapped locations when initiating a read or a write access. table 228. rwcs field descriptions bits name description 31 ac access control 0 end access 1 start access 30 rw read/write select 0 read access 1 write access 29?27 sz word size 000 8-bit (byte) 001 16-bit (half-word) 010 32-bit (word) 011 64-bit (double word?only in burst mode) 100?111 reserved (default to word) 26?24 map map select 000 primary memory map 001?111 reserved 23?22 pr read/write access priority 00 lowest access priority 01 reserved (default to lowest priority) 10 reserved (default to lowest priority) 11 highest access priority 21?16 ? reserved 15?2 cnt access control count. number of accesses of word size sz 1 err read/write access error. see table 229 . 0 dv read/write access data valid. see table 229 . table 229. read/write access status bit encodings read action write action err dv read access has not completed. writ e access completed without error 0 0 read access error has occurred. w rite access error has occurred 1 0 read access completed without error write access has not completed 0 1 not allowed not allowed 1 1
UM0434 nexus3 module 343/391 read/write accesses to the ahb require that the debug firmware properly retrieve/place the data in the rwd. table 231 shows the proper placement of data into the rwd. note that double-word transfers require two passes through rwd. table 232 shows the mapping of rwd bytes to byte lanes of ahb read & write data buses. table 230. read/write access data register 31 0 field read/write data reset all zeros r/w read/write number 0x9 table 231. rwd data placement for transfers transfer sizeand byte offset rwa(2?0) rwcs[sz] rwd 31?24 23?16 15?8 7?0 byte x x x 0 0 0 ? ? ? x half x x 0 0 0 1 ? ? x x word x 0 0 0 1 0 x x x x doubleword 0 0 0 0 1 1 first rwd pass (low order data) x x x x second rwd pass (high order data) x x x x "x" indicates byte lanes with valid data ??? indicates byte lanes which will contain unused data. table 232. rwd byte lane data placement transfer sizeand byte offset rwa(2:0) rwd 31?24 23?16 15?8 7?0 byte @000 0 0 0 ? ? ? ahb[7 ? 0] byte @001 0 0 1 ? ? ? ahb[15 ? 8] byte @010 0 1 0 ? ? ? ahb[23 ? 16] byte @011 0 1 1 ? ? ? ahb[31 ? 24] byte @100 1 0 0 ? ? ? ahb[39 ? 32] byte @101 1 0 1 ? ? ? ahb[47 ? 40] byte @110 1 1 0 ? ? ? ahb[55 ? 48] byte @111 1 1 1 ? ? ? ahb[63 ? 56] half @000 0 0 0 ? ? ahb[15 ? 8] ahb[7 ? 0] half @010 0 1 0 ? ? ahb[31 ? 24] ahb[23 ? 16] half @100 1 0 0 ? ? ahb[47 ? 40] ahb[39 ? 32]
nexus3 module UM0434 344/391 12.4.7 read/write access address register (rwa) the read/write access address register, shown in table 233 , provides the system bus address to be accessed when initiating a read or a write access. 12.4.8 watchpoint tr igger register (wt) the watchpoint trigger register, shown in table 234 , allows the watchpoints defined within the e200z3 nexus1 logic to trigger actions. these watchpoints can control program and/or data trace enable and disable. the wt bits can be used to produce an address related window for triggering trace messages. half @110 1 1 0 ? ? ahb[63 ? 56] ahb[55 ? 48] word @000 0 0 0 ahb[31 ? 24] ahb[23 ? 16] ahb[15 ? 8] ahb[7 ? 0] word @100 1 0 0 ahb[63 ? 56] ahb[55 ? 48] ahb[47 ? 40] ahb[39 ? 32] doubleword @000 0 0 0 ? ? ? ? first rwd pass ahb[31 ? 24] ahb[23 ? 16] ahb[15 ? 8] ahb[7 ? 0] second rwd pass ahb[63 ? 56] ahb[55 ? 48] ahb[47 ? 40] ahb[39 ? 32] ??? indicates byte lanes which will contain unused data. table 232. rwd byte lane data placement (continued) transfer sizeand byte offset rwa(2:0) rwd 31?24 23?16 15?8 7?0 table 233. read/write access address register 31 0 field read/write data reset all zeros r/w read/write number 0xa table 234. watchpoint trigger register 31 2928 2625 2322 2019 0 field pts pte dts dte ? reset all zeros r/w read/write number 0xb
UM0434 nexus3 module 345/391 table 235 details the watchpoint trigger register fields. note: the wt bits only control program/data trace if the tm bits within dc1 have not already been set to enable program and data trace respectively. table 235. wt field descriptions bits name description 31?29 pts program trace start control 000 trigger disabled 001 use watchpoint #0 (iac1 from nexus1) 010 use watchpoint #1 (iac2 from nexus1) 011 use watchpoint #2 (iac3 from nexus1) 100 use watchpoint #3 (iac4 from nexus1) 101 use watchpoint #4 (dac1 from nexus1) 110 use watchpoint #5 (dac2 from nexus1) 111 use watchpoint #6 or #7 (dcnt1 or dcnt2 from nexus1) 28?26 pte program trace end control 000 trigger disabled 001 use watchpoint #0 (iac1 from nexus1) 010 use watchpoint #1 (iac2 from nexus1) 011 use watchpoint #2 (iac3 from nexus1) 100 use watchpoint #3 (iac4 from nexus1) 101 use watchpoint #4 (dac1 from nexus1) 110 use watchpoint #5 (dac2 from nexus1) 111 use watchpoint #6 or #7 (dcnt1 or dcnt2 from nexus1) 25?23 dts data trace start control 000 trigger disabled 001 use watchpoint #0 (iac1 from nexus1) 010 use watchpoint #1 (iac2 from nexus1) 011 use watchpoint #2 (iac3 from nexus1) 100 use watchpoint #3 (iac4 from nexus1) 101 use watchpoint #4 (dac1 from nexus1) 110 use watchpoint #5 (dac2 from nexus1) 111 use watchpoint #6 or #7 (dcnt1 or dcnt2 from nexus1) 22?20 dte data trace end control 000 trigger disabled 001 use watchpoint #0 (iac1 from nexus1) 010 use watchpoint #1 (iac2 from nexus1) 011 use watchpoint #2 (iac3 from nexus1) 100 use watchpoint #3 (iac4 from nexus1) 101 use watchpoint #4 (dac1 from nexus1) 110 use watchpoint #5 (dac2 from nexus1) 111 use watchpoint #6 or #7 (dcnt1 or dcnt2 from nexus1) 19?0 ? reserved, should be cleared
nexus3 module UM0434 346/391 12.4.9 data trace control register (dtc) the data trace control register controls whether dtm messages are restricted to reads, writes, or both for a user programmable address range. there are two data trace channels controlled by the dtc for the nexus3 module. each channel can also be programmed to trace data accesses or instruction accesses. table 236 shows dtc. table 237 details the data trace control register fields. table 236. data trace control register 31 30 29 28 27 8 7 6 5 4 3 2 1 0 field rwt1 rwt2 ? rc1 rc2 ? di1 ? reset all zeros r/w read/write numbe r 0xd table 237. dtc field descriptions bits name description 31?30 rwt1 read/write trace 1 00 no trace enabled x1 enable data read trace 1x enable data write trace 29?28 rwt2 read/write trace 2 00 no trace enabled x1 enable data read trace 1x enable data write trace 27?8 ? reserved, should be cleared. 7 rc1 range control 1 0 condition trace on address within range 1 condition trace on address outside of range 6 rc2 range control 2 0 condition trace on address within range 1 condition trace on address outside of range 5?4 ? reserved, should be cleared. 3di1 data access/instruction access trace 1 0 condition trace on data accesses 1 condition trace on instruction accesses 2?0 ? reserved, should be cleared.
UM0434 nexus3 module 347/391 12.4.10 data trace start address 1 and 2 registers (dtsa1 and dtsa2) the data trace start address registers, shown in table 238 , define the start addresses for each trace channel. 12.4.11 data trace end address registers 1 and 2 (dtea1 and dtea2) the data trace end address registers, shown in table 239 , define the end addresses for each trace channel. table 240 shows the range that is selected for da ta trace for various cases of dtsa being less than, greater than, or equal to dtea. note: dtsa must be less than dtea to guarantee correct data write/read traces. data trace ranges are inclusive of the dtsa and dtea add resses for range control settings indicating within range, and are exclusive of the dtsa an d dtea addresses or range control settings indicating outside of range. table 238. data trace start address registers 31 0 field data trace start address reset all zeros r/w read/write number dtsa1: 0xe; dtsa2: 0xf table 239. data trace end address registers 31 0 field data trace end address reset all zeros r/w read/write number dtea1: 0x12; dtea2: 0x13 table 240. data trace?address range options programmed values range contro l bit value range selected dtsa < dtea 0 the address range lies between the values specified by dtsa and dtea. (dtsa -> <- dtea) 1 the address range lies outside the values specified by dtsa and dtea. (<-dtsa dtea->) dtsa > dtea n/a invalid range?no trace dtsa = dtea n/a invalid range?no trace
nexus3 module UM0434 348/391 12.5 nexus3 register access through jtag/once access to nexus3 register re sources is enabled by loading a single instruction, nexus3- access, into the jtag instruction register/onc e ocmd register. for the nexus3 block, the ocmd value is 0b00_0111_1100. once the nexus3-access instruction has been loaded, the jtag/once port allows tool/target communications with all nexus3 registers according to the register map in table 216 . reading/writing of a nexus3 register then requires two passes through the data-scan path of the jtag state machine 12 (see chapter 12.15: ieee 1149.1 (jtag) rd/wr sequences on page 379 ? ). 1. the first pass through the dr selects the nexus3 register to be accessed by providing an index (see table 216 ), and the direction, read/write. this is achieved by loading an 8-bit value into the jtag data register (dr). this register has the format shown in table 241 . 2. the second pass through the dr then shifts the data in or out of the jtag port, least significant bit first. a) during a read access, data is latched from the selected nexus register when the jtag state machine passes through the capture-dr state. b) during a write access, data is latched into the selected nexus register when the jtag state machine passes through the update-dr state. 12.6 ownership trace this section details the ownership trace features of the nexus3 module. 12.6.1 overview ownership trace provides a macroscopic view , such as task flow reconstruction, when debugging software is written in a high-level or object-oriented language. it offers the highest level of abstraction for tracking operating system software execution. this is especially useful when the developer is not interested in debugging at lower levels. table 241. nexus3 register access through jtag/once (example) (7 bits) (1 bit) nexus register index r/w reset value: 0x00 table 242. nexus register example field description nexus register index selected from values in table 216 read/write (r/w) 0 read 1 write
UM0434 nexus3 module 349/391 12.6.2 ownership trace messaging (otm) ownership trace information is messaged by m eans of the auxiliary port using otm. for e200z3 processors, there are two distinct methods for providing task/process id data. some e200 processors contain a book e?defined process id register within the cpu while others may not. within nexus, task/process id data is handled in one of the following two ways in order to maintain ieee-isto 5001 compliance. 1. if the process id register exists, it is updated by the operating system software to provide task/process id information. the contents of this register are replicated on the pins of the processor and connected to nexus. the process id register value can be accessed using the mfspr / mtspr instructions. see chapter 4.16.5: process id register (pid0) on page 96 .? 2. if the process id register does not exis t, the user base address register (uba) is implemented within nexus. the uba can be accessed by means of the jtag/once port and contains the address of the ownership trace register (otr). the memory- mapped otr is updated by the operating system software to provide task/process id information. note: the e200z3 includes a process id register (pid0), thus the uba functionality is not implemented. there are two conditions that cause an ownership trace message: 1. when new information is updated in the otr register or process id register by the e200z3 processor, the data is latched within nexus and is messaged out through the auxiliary port, allowing development tools to trace ownership flow. 2. when the periodic otm message counter expires after 255 queued messages without an otm, an otm is sent. the data is sent from either the latched otr data or the latched process id data. this allows proce ssors using virtual memory to be regularly updated with the latest process id. ownership trace information is messaged out in the format shown in table 243 . 12.6.3 otm error messages an error message occurs when the message queue is full and a new message cannot be queued. the fifo discards incoming messages until it has completely emptied the queue. once the queue is emptied, an error message is queued. the error encoding indicates which types of messages attempted to be queued while the fifo was being emptied. if only an otm message attempts to enter the queue while the queue is being emptied, the error message only incorporates the otm error encoding 00000. if both otm and either btm or dtm (that is, otm and btm or otm and dtm) messages attempt to enter the queue, the error message incorporates the otm and program or data trace error encoding 00111. if a watchpoint also attempts to be queued while the fifo is being emptied, then the error message incorporates error encoding 01000. table 243. ownership trace message format (32 bits) (4 bits) (6 bits) task/process id tag source process tcode (000010) fixed length = 42 bits
nexus3 module UM0434 350/391 note: dc1[ovc] can be set to delay the cpu in order to alleviate, but not eliminate, potential overrun situations. error information is messaged out in the format shown in table 244 . 12.6.4 otm flow ownership trace messages are generated when the operating system writes to the e200z3 process id register (pid0) or the memory-mapped ownership trace register (otr). the following flow describes the otm process: the process id register is a system control register. it is internal to the core processor and can be accessed by using ppc instructions. the contents of this register are replicated on the pins of the processor and connected to nexus. writes to the e200z3 internal process id regi ster will pulse a write signal to nexus. the data value written into the process id register is latched and formed into the ownership trace message that is queued to be transmitted. process id register reads do not cause ownership trace messages to be transmitted by the nexus 3 module. 12.7 program trace this section details the program trace mechanism supported by nexus3 for the e200z3 processor. program trace is implemented using branch trace messaging (btm) as required by the class 3 ieee-isto 5001-2003 standard definition. branch trace messaging for e200z3 processors is accomplished by snooping the e200z3 virtual address bus, between the cpu and mmu, attribute signals, and cpu status p_pstat[0:5] . 12.7.1 branch trace messaging (btm) traditional branch trace messaging facilitates program trace by providing the following types of information: messaging for taken direct branches includes how many sequential instructions were executed since the last taken branch or exception. direct or indirect branches not taken are counted as sequential instructions. messaging for taken indirect branches and exceptions includes how many sequential instructions were executed since the last taken branch or exception and the unique portion of the branch target address or exception vector address. branch history messaging fac ilitates program trace by prov iding the following information: messaging for taken indirect branches and exceptions includes how many sequential instructions were executed since the last predicate instruction, taken indirect branch, or exception, the unique portion of the branch target address or exception vector address, and a branch/predicate instruction history field. each bit in the history field represents a direct branch or predicated instruction where a value of one indicates taken and a value table 244. error message format (5 bits) (4 bits) (6 its) error code (00000, 00111, or 01000) source process tcode (001000) fixed length = 15 bits
UM0434 nexus3 module 351/391 of zero indicates not taken. certain instructions ( evsel ) generate a pair of predicate bits that are both reported as consecutive bits in the history field. e200z3 indirect branch message instructions (book e) table 245 shows the types of instructions and events that cause indirect branch messages or branch history messages to be encoded. e200z3 direct branch message instructions (book e) table 246 shows the types of instructions that cause direct branch messages or that toggle a bit in the instruction history buffer to be messaged out in a resource full message or branch history message. btm using branch history messages traditional btm can accurately track the number of sequential instructions between branches, but cannot accurately indicate which instructions were conditionally executed and which were not. branch history messaging solves this problem by providing a predicated instruction history field in each indirect branch message. each bit in the history represents a predicated instruction or direct branch, or a not-taken indirect branch. a value of one indicates the conditional instruction was executed or the direct branch was taken. a value of zero indicates the conditional instruction was not executed or the direct branch was not taken. certain instructions ( evsel ) generate a pair of predicate bits that are both reported as consecutive bits in the history field. branch history messagin g facilitates program trace by prov iding the informat ion described in chapter : e200z3 indirect branch message instructions (book e) on page 351 ? : branch history messages solve predicated instruction tracking and save bandwidth because only indirect branches cause messages to be queued. btm using traditional program trace messages program tracing can utilize either branch hist ory messages (dc1[ptm] = 1) or traditional direct/indirect branch messages (dc1[ptm] = 0). table 245. indirect branch message sources source of indirect bran ch message instructions taken branch relative to a register value bcctr , bcctrl , bclr , bclrl, se_bctr, se_bctrl, se_blr, se_blrl system call/trap exceptions taken sc , se_sc , tw , twi return from interrupts/exceptions rfi , rfci , rfdi , se_rfi , se_rfci , se_rfdi table 246. direct branch message sources source of direct branch message instructions taken direct branch instructions b , ba , bl , bla , bc , bca , bcl , bcla, se_b. se_bc, se_bl, e_b, e_bc, e_bl, e_bcl, isync, se_isync instruction synchronize isync, se_isync
nexus3 module UM0434 352/391 branch history saves bandwidth and keeps consistency between methods of program trace, yet may lose temporal order between btm messages and other types of messages. since direct branches are not messaged, but are instead included in the history field of the indirect branch history message, other types of messages may enter the fifo between branch history messages. the development tool cannot determine the ordering of events that occurred with respect to direct branches simply by the order in which messages are sent out. traditional btm messages maintain their temp oral ordering because each event that can cause a message to be queued enters the fifo in the order it occurred and is messaged out maintaining that order. 12.7.2 btm message formats the e200z3 nexus3 block supports three types of traditional btm messages: direct, indirect, and synchronized messages. it supports two types of branch history btm messages: indirect branch history, and indirect branch history with synchronized messages. debug status messages and error messages are also supported. indirect branch messages (history) indirect branches include all taken branches whose destination is determined at run time, interrupts, and exceptions. if dc1[ptm] is set, indirect branch information is messaged out in the format shown in table 247 : indirect branch messages (traditional) if dc1[ptm] is cleared, indirect branch information is messaged out in the format shown in table 248 : direct branch messages (traditional) direct branches, conditional or unconditional, ar e all taken branches whose destinations are fixed in the instruction opcode. direct branch information is messaged out in the format shown in table 249 : table 247. indirect branch message (history) format (1?32 bits) (1?32 bits) (1?8 bits) (4 bits) (6 bits) branch history relative address sequence count source proces s tcode (011100 ) maximum length = 82 bit; minimum length = 13 bits table 248. indirect branch message format (1?32 bits) (1?8 bits) (4 bits) (6 bits) relative address sequence count source process tcode (000100) maximum length = 50 bits; minimum length = 12 bits
UM0434 nexus3 module 353/391 note: when dc1[ptm] is set, direct branch mess ages are not transmitted. instead, each direct branch or predicated instruction toggles a bit in the history buffer. resource full messages the resource full message is used in conjunction with the branch history messages. the resource full message is generated when the internal branch/predicate history buffer is full. if synchronization is needed at the time this message is generated, the synchronization is delayed until the next branch trace message that is not a resource full message. for history buffer overflow, the resource full message transmits a resource code (rcode) of 0b0001 and the current contents of the history buffer, including the stop bit, are transmitted in the resource data (rdata) field. this history information can be concatenated by the development tool with the branch/predicate history information from subsequent messages to obtain the complete branch/predic ate history between indirect changes of flow. for instruction counter overflow, the resource full message transmits an rcode of 0b0000 and a value of 0xff is transmitted in the rdata field, indicating that 255 sequential instructions have been executed since the last change of flow or, if program trace is in history mode, since the last instruction that recorded history information table 250 shows the rcode encodings and rdata information used for resource full messages. debug status messages debug status messages report low-power mode and debug status. debug status messages are enabled when nexus 3 is enabled. entering/exiting debug mode as well as entering a low-power mode triggers a debug status message, indicating the value of the most significant byte in the development status register. debug status information is sent out in the format shown in table 251 : table 249. direct branch message format (1?8 bits) (4 bits) (6 bits) sequence count source process tcode (000011) maximum length = 18 bits; minimum length = 11 bits figure 73. resource full message format (1?32 bits) (4 bits) (4 bits) (6 bits) branch history rcode (0001) source process tcode (011011) maximum length = 46 bits; minimum length = 15 bits table 250. rcode encoding rcode rdata field description 0000 0xff program trace instruction counter reached 255 and was reset. 0001 branch history. this type of packet is terminated by a stop bit set after the last history bit. program trace, branch/predicate instruction history full.
nexus3 module UM0434 354/391 program correlation messages program correlation messages (pcms) are used to correlate events to the program flow that may not be associated with the instruction st ream. the following events will result in a pcm when program trace is enabled: when the cpu enters debug mode, a pcm is generated. the instruction count and history information provided by the pcm can be used to determine the last sequence of instructions executed prior to debug mode entry. when the cpu enters a low power mode in which instructions are no longer executed, a pcm is generated. the instruction count and history information provided by the pcm can be used to determine the last sequence of instructions executed prior to low- power mode entry. whenever program trace is disabled by any means, a pcm is generated. the instruction count and history information provided by the pcm can be used to determine the last sequence of instructions executed prior to disabling program trace. a second pcm is generated on this event if there has been an execution mode switch into or out of a sequence of vle instructions. this vle state information allows the development tool to interpret any preceding instruction count or history information in the proper context. whenever the cpu crosses a page boundary that results in an execution mode switch into or out of a sequence of vle instructions, a pcm is generated. the pcm effectively breaks up any running instruction count and history information between the two modes of operation so that the instruction count and history information can be processed by the development tool in the proper context. when using program trace in history mode, when a direct branch results in an execution mode switch into or out of a sequence of vle instructions, a pcm is generated. the pcm effectively breaks up any running history information between the two modes of operation so that the history information can be processed by the development tool in the proper context. program correlation is messaged out in the format shown in table 252 : btm overflow error messages an error message occurs when the message queue is full and a new message cannot be queued. the fifo discards incoming messages until it has completely emptied the queue. once emptied, an error message is queued. the error encoding indicates which types of messages attempted to be queued while the fifo was being emptied. table 251. debug status message format (8 bits) (4 bits) (6 bits) 31?24 source process tcode (000000) fixed length = 18 bits table 252. program correlation message format (1?32 bits) (1?8 bits) (4 bits) (4 bits) (6 bits) branch history sequence count ecod e source process tcode (1000 01) maximum length = 54 bits; minimum length = 16 bits
UM0434 nexus3 module 355/391 if only a program trace message attempts to enter the queue while it is being emptied, the error message incorporates the program trace only error encoding, 00001. if both otm and program trace messages attempt to enter the queue, the error message incorporates the otm and program trace error encoding 00111. if a watchpoint also attempts to be queued while the fifo is being emptied, the error message incorporates error encoding 01000. note: dc1[ovc] can be set to dela y the cpu in order to alleviate, but not eliminate, potential overrun situations. error information is messaged out in the format shown in table 253 : program trace synchronization messages a program trace direct/indirect branch with synchronization message is messaged using the auxiliary port, provided program trace is en abled, for the followi ng conditions (see table 256 ): initial program trace message upon the first direct/indirect branch after exit from system reset or whenever program trace is enabled upon direct/indirect branch after returning from a cpu low-power state upon direct/indirect branch after returning from debug mode upon direct/indirect branch after occurrence of queue overrun, which can be caused by any trace message upon direct/indirect branch after the periodic program trace counter has expired, indicating 255 without-synchronization prog ram trace messages ha ve occurred since the last with-synchronization message occurred upon direct/indirect branch after assertion of the event-in ( nex_evti_b ) signal, if the eic bits within the dc1 register have enabled this feature upon direct/indirect branch after the sequential instruction counter has expired, indicating 255 instructions have occurred between branches upon direct/indirect branch after a btm message was lost due to an attempted access to a secure memory location (for socs with security) upon direct/indirect branch after a btm me ssage was lost due to a collision entering the fifo between the btm message and either a watchpoint message or an ownership trace message if the nexus3 module is enabled at reset, a nex_evti_b assertion initiates a program trace direct/indirect branch with synchronization message if program trace is enabled upon the first direct/indirect branch. the format for program trace direct/indirect branch with synchronization messages is shown in table 254 : table 253. error message format (5 bits) (4 bits) (6 bits) error code (1) 1. must be one of 00001, 00111, or 01000. source process tcode (001000) fixed length = 15 bits
nexus3 module UM0434 356/391 the formats for program trace direct/indirect branch with synchronized messages and indirect branch history with synchronized messages are shown in table 255 : exceptions resulting in program trace synchronization are summarized in table 256 . table 254. direct/indirect branch wi th synchronization message format (1?32 bits) (1?8 bits) (4 bits) (6 bits) full target address sequence count source process tocode (001011 or 001100) maximum length = 50 bits; minimum length = 12 bits table 255. indirect branch history with synchronization message format (1?32 bits) (1?32 bits) (1?8 bits) (4 bits) (6 bits) branch history full target address sequence count source process tcode (011101) maximum length = 82 bit; minimum length = 13 bits table 256. program trace exception summary exception condition exception handling system reset negation at the negation of jtag reset, j_trst_b , queue pointers, counters, state machines, and registers within the nexus3 module are reset. upon the first branch out of system reset, if program trace is enabled, the first program trace message is a direct/indirect branch wit h synchronization message. program trace enabled the first program trace message, after program trace has been enabled, is a synchronization message. exit from low power/debug upon exit from a low-power mode or debug mode, the next direct/indirect branch is converted to a direct/indirect branch with synchronization message. queue overrun an error message occurs when the message queue is full and a new message cannot be queued. the fifo discards message s until it has completely emptied the queue. once emptied, an error message is queued. the error encoding indicates which types of messages attempted to be queued while the fifo was being emptied. the next btm message in the queue is a direct/indirect branch with synchronization message. periodic program trace synchronization a forced synchronization occurs periodically after 255 program trace messages have been queued. a direct/indirect branch with synchronization message is queued. the periodic program trace message counter then resets. event in if the nexus module is enabled, assorting nex_evti_b initiates a direct/indirect branch with synchronization message upon the next direct/indirect branch, if program trace is enabled and the eic bits of the dc1 register have enabled this feature. sequential instruction count overflow when the sequential instruction counter reaches its maximum count (up to 255 sequential instructions may be executed), a forced synchronization occurs. the sequential counter then resets. a program trace direct/indirect branch with synchronization message is queued upon execution of the next branch.
UM0434 nexus3 module 357/391 12.7.3 btm operation enabling program trace both types of branch trace messaging can be enabled in one of two ways: setting dc1[tm] to enable program trace using wt[pts] to enable program trace on watchpoint hits. e200z3 watchpoints are configured within the cpu. relative addressing the relative address feature is compliant with the ieee-isto 5001-2003 standard recommendations and is designed to reduce the number of bits transmitted for addresses of indirect branch messages. the address transmitted is relative to the target address of the instruction that triggered the previous indirect branch or synchronized message. it is generated by xoring the new address with the previous address and then using only the results up to the most significant 1 bit in the result. to recreate this address, an xor of the most significant zero-padded message address with the previously decoded address gives the current address. for the example given in table 257 , assume the previous address (a1) = 0x0003fc01, and the new address (a2) = 0x0003f365. attempted access to secure memory for socs that implement security, any attempted branch to secure memory locations temporarily disables program trace and causes the corresponding btm to be lost. the following direct/indirect branch queues a direct/indirect branch with synchronization message. the count value within this message will be inaccurate since the re-enable of program trace is not necessarily aligned on an instruction boundary. collision priority all messages have the following priority: wpm
nexus3 module UM0434 358/391 execution mode indication in order for a development tool to properly interpret instruction count and history information, it must be aware of the execution mode context of that information. vle instructions will be inte rpreted differently from non-vle instructions. program trace messages provide the execution mode status in the least significant bit of the reconstructed address field. a value of zero indicates that preceding instruction count and history information should be interpreted in a non-vle context. a value of one indicates that the preceding instruction count and history information should be interpreted in a vle context. note that when a branch results in an execution mode switch, the program trace message resulting from that branch will indicate the previous execution state. the new state will not be signaled until the next program trace message. in some cases, a program correlation message is generated to indicate execution mode status. refer to chapter : program correlation messages on page 354 ,? for more information on these cases. branch/predicate instruction history (hist) if dc1[ptm] is set, btm messaging uses the branch history format. the branch history (hist) packet in these messages provides a history of direct branch execution used for reconstructing program flow. this packet is implemented as a left-shifting shift register. the register is always pre-loaded with a value of one. this bit acts as a stop bit so that the development tools can determine which bit is the end of the history information. the pre- loaded bit itself is not part of the history but is transmitted with the packet. a value of one is shifted into the history buffer on a taken branch, conditional or unconditional, and on any instruction whose predicate condition executed as true. a value of zero is shifted into the history buffer on any instruction whose predicate condition executed as false, as well as on branches not taken. th is includes indirect as well as direct branches not taken. for the evsel instruction, two bits are shifted in, corresponding to the low element shifted in first, and the high element shifted in second. sequential instruction count (i-cnt) the i-cnt packet is present in all btm messag es. for traditional branch messages, i-cnt represents the number of sequential instructions, or non-taken branches, in between direct/indirect branch messages. table 257. relative address generation and re-creation example message generation a1 0000 0000 0000 0011 1111 1100 0000 0001 a2 0000 0000 0000 0011 1111 0011 0110 0101 a1
UM0434 nexus3 module 359/391 for branch history messages, i-cnt represents the number of instructions executed since the last taken/non-taken direct branch, predicate instruction, last taken/not-taken indirect branch, or exception. branch instructions that trigger message generation are included in the i-cnt. instructions that generate history bits are not included in the i-cnt. the sequential instruction counter overflows when its value reaches 255 and is reset to 0. the next btm message (corresponding to the 256th or later instruction) is converted to a synchronization type message. program trace queueing nexus3 implements a programmable depth queue (a minimum of 32 entries is recommended) for queuing all messages. messages that enter the queue are transmitted through the auxiliary pins in the order in which they are queued. note: if multiple trace messages need to be queu ed at the same time, watchpoint messages have the highest priority: (wpm
nexus3 module UM0434 360/391 figure 76. program trace?direct branch (traditional) and error messages figure 77. program trace?indirect branch with synchronization message 12.8 data trace this section deals with the data trace mechanism supported by the nexus3 module. data trace is implemented by means of data writ e messaging (dwm) and data read messaging (drm) in accordance with the ieee-isto 5001-2003 standard. 12.8.1 data trace messaging (dtm) data trace messaging for the e200z3 is accomp lished by snooping the e200z3 virtual data bus between the cpu and mmu, and storing the information for qualifying access, based on enabled features and matching target addresses. the nexus3 module traces all data accesses that meet the selected range and attributes. note: data trace is only performed on the e200z3 virtual data bus. th is allows for data visibility for e200z3 processors that incorporate a data ca che. only e200z3 cpu-in itiated accesses are traced. no dma accesses to the ahb system bus are traced. data trace messaging can be enabled in one of two ways: setting dc1[tm] to enable data trace. using wt[dts] to enable data trace on watchpoint hits. e200z3 watchpoints are configured within the nexus1 module. direct branch error 11 00 00 00 00 11 00 00 10 00 00 00 01 dbm: tcode = 3 source processor = 0000 number of sequential instructions = 3 error: tcode = 8 source processor = 0000 error code = 1 (queue overrun?btm only) 00 00 mcko mseo_b mdo[1:0] 00 11 00 00 00 11 10 11 00 11 10 10 11 tcode = 12 source processor = 0000 number of sequential instructions = 3 full target address = 0xdeadface 11 01 11 10 10 10 11 01 11 00 mcko mseo_b mdo[1:0]
UM0434 nexus3 module 361/391 12.8.2 dtm message formats the nexus3 block supports five types of dtm messages: data write, data read, data write synchronization, data read synch ronization, and error messages. data write messages the data write message contains the data write value and the address of the write access, relative to the previous data trace message. data write message information is messaged out in the format shown in table 258 : data read messages the data read message contains the data read value and the address of the read access, relative to the previous data trace message. data read message information is messaged out in the format shown in table 259 : note: for e200z3-based cpus, the double-word encoding, p_tsiz = 0, indicates a double-word access and is sent out as a single data tr ace message with a single 64-bit data value. the debug/development tool needs to distin guish between the two cases based on the family of e200z3 processors. dtm overflow error messages an error message occurs when the message queue is full and a new message cannot be queued. the fifo discards incoming messages until it has completely emptied the queue. once emptied, an error message is queued. the error encoding indicates which types of messages attempted to be queued while the fifo was being emptied. if only a dtm attempts to enter the queue while it is being emptied, the error message incorporates the data trace only error encoding 00010. if both otm and dtm attempt to enter the queue, the error message incorporates the otm and data trace error encoding, 00111. if a watchpoint also attempts to be queued while the fifo is being emptied, the error message incorporates error encoding, 01000. note: dc1[ovc] can be set to dela y the cpu in order to alleviate, but not eliminate, potential overrun situations. error information is messaged out in the format shown in table 260 : table 258. data write message format (1?64 bits) (1?32 bits) (3 bits) (4 bits) (6 bits) data value(s) relative address data size source process tcode (000101) maximum length = 109 bits; minimum length = 15 bits table 259. data read message format (1?64 bits) (1?32 bits) (3 bits) (4 bits) (6 bits) data value(s) relative address data size source process tcode (000110) maximum length = 109 bits; minimum length = 15 bits
nexus3 module UM0434 362/391 data trace synchronization messages a data trace write/read with synchronizatio n message is messaged through th e auxiliary port, provided data trace is enabled, for the following conditions (see table 262 ): initial data trace message after exit from system reset or whenever data trace is enabled upon returning from a cpu low-power state upon returning from debug mode after occurrence of queue overrun (can be caused by any trace message), provided data trace is enabled after the periodic data trace counter has expired, indicating 255 data trace messages have occurred without synchronization sinc e the last with-synchronization message occurred upon assertion of the event-in nex_evti_b pin, the first data trace message is a synchronization message if the eic bits of the dc1 register have enabled this feature. upon data trace write/read after the previous dtm message was lost due to an attempted access to a secure memory location (for soc?s with security) upon data trace write/ read after the previo us dtm message was lost due to a collision entering the fifo between the dtm message and any of the following: ? watchpoint message ? ownership trace message ? branch trace message data trace synchronization messages provide the full address, without leading zeros, and ensure that development tools fully synchroniz e with data trace regularly. synchronization messages provide a reference address for subsequent dtms, in which only the unique portion of the data trace address is transmitted. the format for data trace write/read with synchronization messages is as follows: exception conditions that result in data trace synchronization are summarized in table 262 . table 260. error message format (5 bits) (4 bits) (6 bits) error code (00010/00111/01000 sour ce process tcode (001000) fixed length = 15 bits table 261. data write/read with synchronization message format (1?64 bits) (1?32 bits) (3 bits) (4 bits) (6 bits) data value full address data size source process tcode (001101 or 001110) maximum length = 109 bit; minimum length = 15 bits
UM0434 nexus3 module 363/391 12.8.3 dtm operation dtm queueing nexus3 implements a programmable depth queue (a minimum of 32 entries is recommended) for queuing all messages. messages that enter the queue are transmitted through the auxiliary pins in the order in which they are queued. note: if multiple trace messages need to be queued simultaneously, watchpoint messages have the highest priority: wpm
nexus3 module UM0434 364/391 relative addressing the relative address feature is compliant with the ieee-isto 5001-2003 standard recommendations and is designed to reduce the number of bits transmitted for addresses of data trace messages. refer to chapter : relative addressing on page 357 ,? for details. data trace windowing data write/read messages are enabled by the rwt1 n field in the data trace control register, dtc, for each dtm channel. data trace windowing is achieved through the address range defined by the dtea and dtsa registers and by dtc[rc1 n ]. all e200z3-initiated read/write accesses that fall inside or outside these address ranges, as programmed, are candidates to be traced. data access/instruction access data tracing the nexus3 module is capable of tracing both instruction access data or data access data. each trace window can be configured for either type of data trace by setting the di1 n field within the data trace control register for each dtm channel. e200z3 bus cycle special cases note: for a misaligned access that crosses a 64-bit boundary, the access is broken into two accesses. if both accesses are within the data trace range, two dtms are sent: one with a size encoding indicating the size of the orig inal access, that is, word, and one with a size encoding for the portion that cross ed the boundary, that is, 3 bytes see table 109: invalid instruction forms on page 123 for examples of misaligned accesses. note: an stm (store) to the cache?s store buffer within the data trace range initiates a dtm message. if the corresponding memory acce ss causes an error, a checkstop condition occurs. the debug/development tool should use this indication to invalidate the previous dtm. table 263. e200z3 bus cycle cases special case action e200z3 bus cycle aborted cycle ignored e200z3 bus cycle with data error (tea ) data trace message discarded e200z3 bus cycle completed without e rror cycle captured and transmitted e200z3 (ahb) bus cycle initia ted by nexus3 cycle ignored e200z3 bus cycle is an instruction fetch cycle ignored e200z3 bus cycle accesses mi saligned data (across 64-bit boundary)?both first and second transactions within data trace range first and second cycle captured and two dtms transmitted e200z3 bus cycle accesses mi saligned data (across 64-bit boundary)?first transaction within data trace range; second transaction out of data trace range first cycle captured and transmitted; second cycle ignored e200z3 bus cycle accesses mi saligned data (across 64-bit boundary)?first transaction out of data trace range; second transaction within data trace range first cycle ignored; second cycle captured and transmitted
UM0434 nexus3 module 365/391 12.8.4 data trace timing diagrams (8 mdo/2 mseo configuration) figure 78. data trace?data write message figure 79. data trace?data read with synchronization message figure 80. error message (data trace only encoded) 12.9 watchpoint support this section details the watchpoint features of the nexus3 module. 12.9.1 overview the nexus3 module provides watchpoint messaging by means of the auxiliary pins, as defined by the ieee-isto 5001-2003 standard. nexus3 is not compliant with class 4 breakpoint/watchpoint requirements defined in the standard. the breakpoint/watchpoint control register is not implemented. 10101000 00000101 00010100 11101111 11 00 00 01 00 tcode = 5 source processor = 0000 data size = 010 (half word) relative address = 0xa5 write data = 0xbeef 11 10111110 mcko mseo_b[1:0] mdo[7:0] 11000000 00001110 01011001 11010001 11 00 tcode = 14 source processor = 0000 data size = 000 (byte) full access address = 0x01468ace write data = 0x5c 00101000 01 00000000 11 01011100 mcko mseo_b[1:0] mdo[7:0] 00001000 00001000 11 00 11 tcode = 8 source processor = 0000 error code = 2 (queue overrun - dtm only) xxxxxxxx xx mcko mseo_b[1:0] mdo[7:0]
nexus3 module UM0434 366/391 12.9.2 watchpoint messaging enabling watchpoint messaging is done by sett ing the watchpoint enable bit in the dc1 register. setting the individual watchpoint sources is supported through the e200z3 nexus1 module. the e200z3 nexus1 module is capable of setting multiple address and/or data watchpoints. please refer to chapter 11: debug support on page 296 ,? for details on watchpoint initialization. when these watchpoints occur, a watchpoint event signal from the nexus1 module causes a message to be sent to the queue to be messaged out. this message includes the watchpoint number indicating which watchpoint caused the message. the occurrence of any of the e200z3-defined watchpoints can be programmed to assert the event out, nex_evto_b , pin for one period of the output clock, nex_mcko ; see table 271 for details on nex_evto_b . watchpoint information is messaged out in the format shown in table 264 : table 264. watchpoint message format. 12.9.3 watchpoint error message an error message occurs when the message queue is full and a new message cannot be queued. the fifo discards messages until it has completely emptied the queue. once emptied, an error message is queued. the error encoding indicates which types of messages attempted to be queued while the fifo was being emptied. if only a watchpoint message attempts to enter the queue while it is being emptied, the error message incorporates the watchpoint-only error encoding, 00110. if an otm and/or program trace and/or data trace message also at tempts to enter the queue while it is being emptied, the error message incorporates error encoding 01000. note: dc1[ovc] can be set to delay the cpu in order to alleviate, but not eliminate, potential overrun situations. (8 bit) (4 bits) (6 bits) watchpoint source source process tcode (001111) fixed length = 18 bits table 265. watchpoint source encoding watchpoint source (8-bits) watchpoint description 0000_0001 e200z3 watchpoint #0 (iac1 from nexus1) 0000_0010 e200z3 watchpoint #1 (iac2 from nexus1) 0000_0100 e200z3 watchpoint #2 (iac3 from nexus1) 0000_1000 e200z3 watchpoint #3 (iac4 from nexus1) 0001_0000 e200z3 watchpoint #4 (dac1 from nexus1) 0010_0000 e200z3 watchpoint #5 (dac2 from nexus1) 0100_0000 e200z3 watchpoint #6 (dcnt1 from nexus1) 1000_0000 e200z3 watchpoint #7 (dcnt2 from nexus1)
UM0434 nexus3 module 367/391 error information is messaged out in the format, shown in table 266 : 12.9.4 watchpoint timing diagram (2 mdo/1 mseo configuration) figure 81. watchpoint message and watchpoint error message 12.10 nexus3 read/write access to memory-mapped resources the read/write access feature allows access to memory-mapped resources through the jtag/once port. the read/write mechanism supports single as well as block reads and writes to e200z3 ahb resources. the nexus3 module is capable of accessing resources on the e200z3 system bus, ahb, with multiple configurable priority levels. memory-mapped registers and other non-cached memory can be accessed through the standard memory map settings. all accesses are set up and initiated by the read/write access control/status register, rwcs, as well as rwa and rwd. using rwcs, rwa and rwd, memory-mapped e200z3 ahb resources can be accessed through nexus3. the following sections describe the steps that are required to access memory-mapped resources. note: read/write access can only access memory-mapped resources when system reset is de- asserted and clocks are running. misaligned accesses are not supported in the e200z3 nexus3 module. 12.10.1 single write access note: in the first three steps, the registers are initialized using the acce ss method outlined in chapter 12.5: nexus3 register access through jtag/once on page 348 .? table 266. error message format (5 bits) (4 bits) (6 bits) error code (00110/01000 source process tcode (001000) fixed length = 15 bits watchpoint error 11 11 00 00 10 00 00 00 10 00 00 10 01 wpm: tcode = 15 source processor = 00 watchpoint number = 2 error: tcode = 8 source processor = 00 error code = 6 (queue overrun?wpm only) 00 p_mcko p_mseo_b p_mdo[1:0]
nexus3 module UM0434 368/391 1. initialize rwa using the nexus register index of 0x9; see table 216 . configure as shown below: ? write address = 0x nnnn_nnnn (write address) 2. initialize rwcs using the nexus register index of 0x7; see table 216 . configure the fields as shown in table 267 : note: access count (cnt) of 0x0000 or 0x0001 performs a single access. 3. initialize rwd using the nexus register index of 0xa; see table 216 . configure as shown below: ? write data = 0x nnnn_nnnn (write data) 4. the nexus block then arbitrates for the ahb system bus and transfers the data value from the data buffer rwd register to the memory-mapped address in rwa. when the access has completed without error (err=0), nexus asserts the nex_rdy_b signal (see table 271 for detail on nex_rdy_b ) and clears rwcs[dv]. this indicates that the device is ready for the next access. note: only the nex_rdy_b signal and the dv a nd err fields within rwcs provide read/write access status to the external development tool. 12.10.2 block write access (non-burst mode) 1. for a non-burst block write access, follow steps 1, 2, and 3 outlined in chapter 12.10.1: single write access on page 367 ,? to initialize the registers, but use a value greater than one (0x0001) for rwcs[cnt]. 2. the nexus block then arbitrates for the ahb system bus and transfers the first data value from the rwd register to the memory-mapped address in rwa. when the transfer has completed without error (err = 0), the address from the rwa register is incremented to the next word size (specified in rwcs[sz]), and the number from the cnt field is decremented. nexus then asserts the nex_rdy_b pin. this indicates that the device is ready for the next access. 3. repeat step 3 in chapter 12.10.1: single write access on page 367 ,? until the internal cnt value is zero. when this occurs, rwcs[dv] is cleared to indicate the end of the block write access. table 267. single write access field settings field setting ac (access control) 1 (i ndicates start access) map (map select) 000 (primary memory map) pr (access priority) 00 (lowest priority) rw (read/write) 1 (write access) sz (word size) 0 nn (32-bit, 16-bit, 8-bit) cnt (access count) 0x0000 or 0x0001 (single access)
UM0434 nexus3 module 369/391 12.10.3 block write access (burst mode) 1. for a burst block write access, follow steps 1 and 2 outlined in chapter 12.10.1: single write access on page 367 ,? to initialize the registers, using a value of four (double-word) for rwcs[cnt] and an rwcs[sz] value of 0b011, indicating 64-bit access. 2. initialize the burst data buffer (rwd register) through the access method outlined in chapter 12.5: nexus3 register access through jtag/once on page 348 ,? using the nexus register index of 0xa; see table 216 . 3. repeat step 2 until all double-word values are written to the buffer. note: the data values must be shifted in 32 bits at a time, least significant bit first (that is, double- word write = two word writes to rwd). 4. the nexus block then arbitrates for the ahb system bus and transfers the burst data values from the data buffer to the ahb beginning from the memory mapped address in rwa. for each access within the burst, the address from the rwa register is incremented to the next double-word size (as specified in rwcs[sz]), modulo the length of the burst, and the number from the cnt field is decremented. 5. when the entire burst transfer has completed without error (err=0), nexus3 then asserts the nex_rdy_b pin, and rwcs[dv] is cleared to indicate the end of the block write access. note: the actual rwa and rwcs[cnt] values ar e not changed when executing a block write access, burst or non-burst. the original values can be read by the external development tool at any time. 12.10.4 single read access 1. initialize rwa with the ac cess method outlined in chapter 12.5: nexus3 register access through jtag/once on page 348 ,? using the nexus register index of 0x9; see table 216 . configure as shown below: ? read address = 0x nnnn_nnnn (read address) 2. initialize rwcs with the a ccess method outlined in chapter 12.5: nexus3 register access through jtag/once on page 348 ,? using the nexus register index of 0x7; see table 216 . configure the bits as shown in table 268 : note: access count (cnt) of 0x0000 or 0x0001 performs a single access. 3. the nexus block then arbitrates for the ahb system bus and the read data is transferred from the ahb to the rwd register. when the transfer is completed without error (err=0), nexus asserts the nex_rdy_b pin (see table 271 for details on table 268. single read access parameter settings parameter settings access control (ac) 1 (to indicate start access) map select (map) 000 (primary memory map) access priority (pr) 00 (lowest priority) read/write (rw) 0 (read access) word size (sz) 0 nn (32-bit, 16-bit, 8-bit) access count (cnt) 0x0000 or 0x0001(single access)
nexus3 module UM0434 370/391 nex_rdy_b ) and sets rwcs[dv]. this indicates that the device is ready for the next access. 4. the data can then be read from rwd with the access method outlined in chapter 12.5: nexus3 register access th rough jtag/once on page 348 ,? using the nexus register index of 0xa; see table 216 . note: only the nex_rdy_b signal and the dv and e rr bits within rwcs provide read/write access status to the external development tool. 12.10.5 block read a ccess (non-burst mode) 1. for a non-burst block read access, follow steps 1 and 2 outlined in chapter 12.10.4: single read access on page 369 ,? to initialize the registers, but using a value greater than one (0x0001) for rwcs[cnt]. 2. the nexus block then arbitrates for the ahb system bus, and the read data is transferred from the ahb to the rwd register. when the transfer has completed without error (err = 0), the address from rwa is incremented to the next word size (specified in the sz field), and the number from the cnt field is decremented. nexus then asserts the nex_rdy_b pin. this indicates that the device is ready for the next access. 3. the data can then be read from rwd with the access method outlined in chapter 12.5: nexus3 register access th rough jtag/once on page 348 ,? using the nexus register index of 0xa, see table 216 . 4. repeat steps 3 and 4 in chapter 12.10.4: single read access on page 369 ,? until the cnt value is zero. when this occurs, rwcs[dv] is set to indicate the end of the block read access. 12.10.6 block read access (burst mode) 1. for a burst block read access, follow steps 1 and 2 outlined in chapter 12.10.4: single read access on page 369 ,? to initialize the registers, using a value of four (double- words) for the cnt field and an sz field indicating 64-bit access in rwcs. 2. the nexus block then arbitrates for the ahb system bus and the burst read data is transferred from the ahb to the data buffer (rwd register). for each access within the burst, the address from the rwa register is incremented to the next double-word, specified in the sz field, and the number from the cnt field is decremented. 3. when the entire burst transfer has completed without error (err=0), nexus then asserts the nex_rdy_b pin, and rwcs[dv] is set to indicate the end of the block read access. 4. the data can then be read from the burst data buffer (rwd register) with the access method outlined in chapter 12.5: nexus3 register access through jtag/once on page 348 ,? using the nexus register index of 0xa; see table 216 . 5. repeat step 3 until all double-word values are read from the buffer. note: the data values must be shifted out 32-bits at a time, least significant bit first, that is double- word read = two word reads from rwd. note: the actual rwa and cnt values within rwcs are not changed when executing a block read access, burst or non-burst. the original values can be read by the external development tool at any time.
UM0434 nexus3 module 371/391 12.10.7 error handling the nexus3 module handles vari ous error conditions as described in the following sections. ahb read/write error all address and data errors that occur on read/write accesses to the e200z3 ahb system bus return a transfer error encoding on the p_hresp[1:0] signals. if this occurs, the following steps are taken: 1. the access is terminated without retrying, and rwcs[ac] is cleared. 2. rwcs[err] is set. 3. the error message is sent, tcode = 8, indicating read/write error. access termination the following cases are defined for sequences of the read/write protocol that differ from those described in the above sections. 1. if rwcs[ac] is set to start read/write accesses and invalid values are loaded into rwd or rwa, an ahb access error may occur. this is handled as described above. 2. if a block access is in progress, all cycles are not completed, and the rwcs register is written. the original block access is terminated at the boundary of the nearest completed access. a) if rwcs[ac] is set, the next read/write access begins and the rwd can be writtento/readfrom. b) if rwcs[ac] is cleared, the read/write access is terminated at the nearest completed access. this method can be used to break block accesses or terminate them early. read/write access error message the read/write access error message is sent out when an ahb system bus access error, read or write, has occurred. error information is messaged out in the format shown in table 269 : 12.11 nexus3 pin interface this section details the nexus3 pins and pin protocol. the nexus3 pin interface provides the function of transmitting messages from the message queue to the external tools. it is also responsible for handshaking with the message queue. 12.11.1 pins implemented the nexus3 module implements one nex_evti_b and either one nex_mseo_b or two nex_mseo_b[1:0] . it also implements a configurable number of nex_mdo[n:0] pins, table 269. error message format (5 bits) (4 bits) (6 bits) error code (00011) source process tcode (001000) fixed length = 15 bits
nexus3 module UM0434 372/391 nex_rdy_b pin, nex_evto_b pin, and one clock output pin, nex_mcko . the output pins are synchronized to the nexus3 output clock, nex_mcko . all nexus3 input functionality is controlled through the jtag/once port, in compliance with ieee 1149.1. (see chapter 12.5: nexus3 register access through jtag/once on page 348 ,? for details.) the jtag pins are incorporated as i/o to the e200z3 processor and are further described in chapter 11.5.2: jtag/once signals on page 308 .? the auxiliary pins are used to send and receive mess ages and are de scribed in table 271 . table 270. jtag pins for nexus3 jtag pin i/o description of jtag pins (included in e200z3 nexus1) j_tdo o test data output. j_tdo is the serial output for test instructions and data. it is three-statable and is actively driven in the shift-ir and shift-dr controller states. it changes on the falling edge of j_tclk . j_tdi i test data input. j_tdi receives serial test in struction and data. tdi is sampled on the rising edge of j_tclk . j_tms i test mode select. input pin used to sequence the once controller state machine. j_tms is sampled on the rising edge of j_tclk . j_tclk i test clock. input pin used to synchroni ze the test logic and control register access through the jtag/once port. j_trst_b i test reset. input pin used to asyn chronously initialize the jtag/once controller. table 271. nexus3 auxiliary pins auxiliary pin i/o descripti on of auxiliary pins nex_mcko o message clock out. a free running output clock to development tools for timing of nex_mdo[n:0] and nex_mseo_b[1:0] pin functions. nex_mcko is programmable through the dc1 register. nex_mdo[n?0] o message data out. used for otm, btm, and dtm. external latching of nex_mdo[n:0] occurs on the rising edge of the nexus3 clock ( nex_mcko ). nex_mseo_b[1?0] o message start/end out. indicate when a message on the nex_mdo[n:0] pins has started, when a variable length packet has ended, and when the message has ended. external latching of nex_mseo_b[1?0] occurs on the rising edge of the nexus3 clock ( nex_mcko ). one- or two-pin mseo f unctionality is determined at integration time according to the soc implementation nex_rdy_b o ready. used to indicate to the external tool that the nexus block is ready for the next read/write access. if nexus is enabled, this signal is asserted upon successful completion (without error) of an ahb system bus transfer (nexus read or wr ite) and is held asserted until the jtag/once state machine reaches the capture_dr state. upon exit from system reset or if nexus is disabled, nex_rdy_b remains de- asserted.
UM0434 nexus3 module 373/391 the nexus auxiliary port arbitration pins are us ed when the nexus3 module is implemented in a multiple nexus soc that shares a single auxiliary out put port. the arbitration is controlled by an soc-leve l nexus port control module (npc). refer to chapter 12.13: auxiliary port arbitration on page 376 ,? for details on nexus port arbitration. 12.11.2 pin protocol the protocol for the e200z3 pr ocessor transmitting messages th rough the auxiliary pins is accomplished with the mseo pin function outlined in table 273 . both single- and dual-pin cases are shown. nex_mseo_b[1:0] is used to signal the end of variable-length packets, and not fixed length packets. nex_mseo_b[1:0] is sampled on the rising edge of the nexus3 clock, nex_mcko . nex_evto_b o event out. an output whose assertion indicates that one of two events has occurred based on the bits in dc1[eoc]. nex_evto_b is held asserted for 1 cycle of nex_mcko : ? one (or more) watchpoints has occurred (from nexus1) and eoc = 00 ? debug mode was entered ( jd_debug_b asserted from nexus1) and eoc = 01 nex_evti_b i event in. an input whose assertion initiates one of two events based on dc1[eic] (if the nexus module is enabled at reset): ? program trace and data trace synchronization messages (provided program trace and data trace are enabled and eic = 00). ? debug request to e200z3 nexus1 module (provided eic = 01 and this feature is implemented). table 272. nexus port arbitration signals nexus port arbitration pins input/ output description of arbitration pins nex_aux_req[1:0] o nexus auxiliary request. output signals indicating to an soc level nexus arbiter a request for access to the shared nexus auxiliary port in a multiple nexus implementation. the priority encodings are determined by how many messages are currently in the message queues, see table 274 ). nex_aux_busy o nexus auxiliary busy. an output signal to an soc level nexus arbiter indicating that the nexus3 module is currently transmitting its message after being granted the nexus auxiliary port. npc_aux_grant i nexus auxiliary grant. an input from the soc level nexus port controller (npc) indicating that the auxiliary port has been granted to the nexus3 module to transmit its message. ext_multi_nex_sel i multiple nexus select. a static signal indica ting that the nexus3 module is implemented within a multiple nexus environment. if set, port control and arbitration is controlled by the soc-level arbitration module (npc). table 271. nexus3 auxiliary pins (continued) auxiliary pin i/o descripti on of auxiliary pins
nexus3 module UM0434 374/391 figure 82. state diagram for single pin mseo transfers note that the end message state does not contain valid data on nex_mdo[n:0] . also, it is not possible to have two consecutive end packet messages. this implies the minimum packet size for a variable length packet is 2x the number of nex_mdo[n:0] pins. this ensures that a false end-of-message state is not enter ed by emitting two consecutive 1s on nex_mseo_b before the actual end of message. figure 83 shows the state diagram for dual-pin mseo transfers. table 273. mseo pin(s) protocol nex_mseo_b function single nex_mseo_b data (serial) dual nex_mseo_b[1:0] data start of message 1?1?0 11?00 end of message 0?1?1?(more ones) 00 (or 01)?11?(more ones) end of variable length packet 0?1?0 00?01 message transmission 0s 00s idle (no message) 1s 11s normal transfer nex_mseo_b=1 nex_mseo_b=1 nex_mseo_b=0 nex_mseo_b=0 nex_mseo_b=1 nex_mseo_b=1 nex_mseo_b=0 nex_mseo_b=0 nex_mseo_b=0 nex_mseo_b=1 not allowed end packet idle mdo: invalid stage message end message mdo: invalid
UM0434 nexus3 module 375/391 figure 83. dual-pin mseo transfers the dual-pin mseo option is more robust than the single-pin option. termination of the current message may immediately be followed by the start of the next message on consecutive clocks. an extra clock to end the message is not necessary as with the one mseo pin option. the dual-pin option also allows for consecutive end packet states. this can be an advantage when small, variable sized packets are transferred. note: the end message state may also indicate the end of a variable-length packet as well as the end of the message when using the dual-pin option. 12.12 rules for output messages e200z3-based class 3?compliant embedded processors must provide messages through the auxiliary port in a consis tent manner as described below: a variable-length packet within a message must end on a port boundary. a variable-length packet may start within a port boundary only when following a fixed- length packet. if two variable-length packets end and start on the same clock, it is impossible to know which bit is from the last packet and which bit is from the next packet. whenever a variable-length packet is sized such that it does not end on a port boundary, it is necessary to extend and zero-f ill the remaining bits after the highest order bit so that it can end on a port boundary. normal transfer end message nex_mseo_b[1:0]=11 nex_mseo_b[1:0]=11 nex_mseo_b[1:0]=00 nex_mseo_b[1:0]=00 nex_mseo_b[1:0]=01 n e x _ ms e o _ b [ 1 : 0 ] = 0 1 nex_mseo_b[1:0]=00 nex_mseo_b[1:0]=00 nex_mseo_b[1:0]=00 nex_mseo_b[1:0]=11 nex_mseo_b[1:0]=01 end packet n e x _ ms e o _ b [ 1 : 0 ] = 1 1 nex_mseo_b[1:0]=11 nex_mseo_b[1:0]=10 start message nex_mseo_b[1:0]=10 nex_mseo_b[1:0]=10 nex_mseo_b[1:0]=01 nex_mseo_b[1:0]=01 idle mdo: invalid
nexus3 module UM0434 376/391 for example, if the nex_mdo[n:0] port is 2 bits wide and the unique portion of an indirect address tcode is 5 bits, the remaining 1 bit of nex_mdo[n:0] must be packed with a zero. 12.13 auxiliary port arbitration in a multiple nexus environment, the nexus3 module must arbitrate for the shared nexus port at the soc level.the request scheme is implemented as a 2-bit request with various levels of priority. the priority levels are defined in table 274 below. the nexus3 module receives a 1-bit grant signal ( npc_aux_grant ) from the soc level arbiter. when a grant is received, the nexus3 module begins transmitting its message following the protocol outlined in chapter 12.11.2: pin protocol on page 373 .? the nexus3 module maintains control of the port, by asserting the nex_aux_busy signal, until the mseo state machine reaches the end message state. 12.14 examples the following are examples of program trace and data trace messages. table 275 shows an example of an indirect branch message with 2 mdo/1 mseo configuration. table 276 shows the same example with an 8 mdo/2 mseo configuration. note: during clock 12, the nex_mdo[n:0] pins are ignored in the single mseo case. table 274. mdo request encodings request level mdo request encoding(nex_a ux_req[1:0]) condition of queue no request 00 no message to send low priority 01 message queue less than half full ?10reserved high priority 11 message queue at least half full
UM0434 nexus3 module 377/391 t0 and s0 are the least significant bits, where tx = tcode number (fixed); sx = source processor (fixed); ix = number of instructions (v ariable); ax = unique portion of the address (variable). t0 and s0 are the least significant bits, where tx = tcode number (fixed); sx = source processor (fixed); ix = number of instructions (v ariable); ax = unique portion of the address (variable). table 278 shows examples of direct branch messages: one with 2 mdo/1 mseo, and one with 8 mdo/2 mseo. table 275. indirect branch message example (2 mdo/1 mseo) clock nex_mdo[1:0] nex_mseo_b state 0xx 1 idle (or end of last message) 1t1t0 0 start message 2t3t2 0 normal transfer 3t5t4 0 normal transfer 4s1s0 0 normal transfer 5s3s2 0 normal transfer 6i1i0 0 normal transfer 7i3i2 0 normal transfer 8i5i4 1 end packet 9a1a0 0 normal transfer 10 a3 a2 0 normal transfer 11 a5 a4 0 normal transfer 12 a7 a6 1 end packet during clock 12, the nex_mdo[n:0] pins are ignored in the single-mseo case. 13 0 0 1 end message 14 t1 t0 0 start message table 276. indirect branch message example (8 mdo/2 mseo) clock nex_mdo[7:0] nex_mseo_b[1:0] state 0 xxxxxxxx 1 1 idle (or end of last message) 1 s1s0t5t4t3t2t1t0 0 0 start message 2 i5i4i3i2i1i0s3s2 0 1 end packet 3 a7a6a5a4a3a2a1a0 1 1 end packet/end message 4 s1s0t5t4t3t2t1t0 0 0 start message
nexus3 module UM0434 378/391 t0, a0 and s0 are the least significant bits, where tx = tcod e number (fixed); sx = source pr ocessor (fixed); zx = data size (fixed); ax = unique portion of address (variable) ; dx = write data (variable-8,16 or 32-bit). t0 and s0 are the least significant bits , where tx = tcode number (fixed); sx = s ource processor (fixed); ix = number of instructions (variable); ax = uni que portion of the address (variable). table 279 shows an example of a data write message with 8 mdo/1 mseo configuration, and table 280 shows the same dwm with 8 mdo/2 mseo configuration. t0, a0 and s0 are the least significant bits, where tx = tcod e number (fixed); sx = source pr ocessor (fixed); zx = data size (fixed); ax = unique portion of address (variable) ; dx = write data (variable-8,16 or 32-bit). table 277. direct branch message example (2 mdo/1 mseo) clock nex_mdo[1:0] nex_mseo_b state 0 x x 1 idle (or end of last message) 1 t1 t0 0 start message 2 t3 t2 0 normal transfer 3 t5 t4 0 normal transfer 4 s1 s0 0 normal transfer 5 s3 s2 0 normal transfer 6 i1 i0 1 end packet 7 0 0 1 end message table 278. direct branch message example (8 mdo / 2 mseo) clock nex_mdo[7:0] nex_mseo_b[1:0] state 0 x x x x x x x x 1 1 idle (or end of last message) 1 s1s0t5t4t3t2t1t0 0 0 start message 2 0 0 0 0 i1 i0 s3 s2 1 1 end packet/end message 3 s1s0t5t4t3t2t1t0 0 0 start message table 279. data write message example (8 mdo/1 mseo) clock nex_mdo[7:0] nex_mseo_b state 0 x x x x x x x x 1 idle (or end of last message) 1 s1s0t5t4t3t2t1t0 0 start message 2 a2a1a0z2z1z0s3s2 1 end packet 3 d7d6d5d4d3d2d1d0 0 normal transfer 4 00000000 1 end packet 5 00000000 1 end message table 280. data write message example (8 mdo/2 mseo) clock nex_mdo[7:0] nex_mseo_b[1:0] state 0 x x x x x x x x 1 1 idle (or end of last message)
UM0434 nexus3 module 379/391 t0, a0 and s0 are the least significant bits, where tx = tcod e number (fixed); sx = source pr ocessor (fixed); zx = data size (fixed); ax = unique portion of address (variable) ; dx = write data (variable-8,16 or 32-bit). 12.15 ieee 1149.1 (jtag) rd/wr sequences this section contains examples of jtag/once sequences used to access resources. 12.15.1 jtag sequence for accessing internal nexus registers table 281 shows the jtag/once sequence for accessing internal nexus3 registers. 12.15.2 jtag sequence for read acce ss of memory-mapped resources table 282 shows the jtag sequence for read-accessing memory-mapped resources. 1 s1s0t5t4t3t2t1t0 0 0 start message 2 a2 a1 a0 z2 z1 z0 s3 s2 0 1 end packet 3 d7d6d5d4d3d2d1d0 1 1 end packet/end message table 280. data write message example (8 mdo/2 mseo) (continued) clock nex_mdo[7:0] nex_mseo_b[1:0] state table 281. accessing internal nexus3 registers through jtag/once step tms pin description 1 1 idle?select?dr_scan 2 0 select?dr_scan?capture-dr (nexus comma nd register value loaded in shifter) 3 0 capture-dr?shift-dr 40 (7) tck clocks issued to shift in direction ( rd/wr) bit and first 6 bits of nexus register address 5 1 shift-dr?exit1?dr (7th bit of nexus reg. shifted in) 6 1 exit1-dr?update-dr (nexus shifter is transferred to nexus command register) 7 1 update-dr?select-dr_scan 8 0 select-dr_scan?capture-dr (register value is transferred to nexus shifter) 9 0 capture-dr?shift-dr 10 0 (31) tck clocks issued to transfer register value to tdo pin while shifting in tdi value 11 1 shift-dr?exit1?dr (msb of value is shifted in/out of shifter) 12 1 exit1-dr?update?dr (if access is write, shifter is transferred to register) 13 0 update-dr?run-test/idle (transfer complet e?nexus controller to register select state) table 282. accessing memory-mapped resources (reads) step tclk clocks description 1 13 nexus command = write to read/write access address register (rwa) 2 37 write rwa (initialize starting read address?data input on tdi)
nexus3 module UM0434 380/391 12.15.3 jtag sequence for write access of memory-mapped resources table 283 shows the jtag sequence for write-accessing memory-mapped resources. 3 13 nexus command = write to read/wri te control/status register (rwcs) 4 37 write rwcs (initialize read access mode and cnt value?data input on tdi) 5 ? wait for falling edge of nex_rdy_b pin 6 13 nexus command = read read/write access data register (rwd) 7 37 read rwd (data output on tdo) 8 ? if cnt > 0, go back to step 5 table 282. accessing memory-mapped resources (reads) (continued) step tclk clocks description table 283. accessing memory-mapped resources (writes) step tclk clocks description 1 13 nexus command = write to read/write access control/status register (rwcs) 2 37 write rwcs (initialize write access mode and cnt value?data input on tdi) 3 13 nexus command = write to read/write address register (rwa) 4 37 write rwa (initialize starting write address?data input on tdi) 5 13 nexus command = read read/write access data register (rwd) 6 37 write rwd (data output on tdo) 7 ? wait for falling edge of nex_rdy_b pin 8 ? if cnt > 0, go back to step #5
UM0434 glossary 381/391 13 glossary the glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. some of the terms and definitions included in the glossary are reprinted from ieee standard 754-1985, ieee standard for binary floating-point arithmetic , copyright ?1985 by the institute of electrical and electronics engineers, inc. with the permission of the ieee. a architecture. a detailed specification of requirement s for a processor or computer system. it does not specify details of how the proces sor or computer system must be implemented; instead it provides a template for a family of compatible implementations . asynchronous interrupt. interrupts that are caused by events external to the processor?s execution. in this document, the term asynchronous interrupt is used interchangeably with the word interrupt . atomic access. a bus access that attempts to be part of a read-write operation to the same address uninterrupted by any other access to that address (the term refers to the fact that the transactions are indivisible). the powerpc architecture implements atomic accesses through the lwarx / stwcx. instruction pair. b biased exponent. an exponent whose range of values is shifted by a constant (bias). typically a bias is provided to allow a range of positive values to express a range that includes both positive and negative values. big-endian. a byte-ordering method in memory where the address n of a word corresponds to the most-significant byte . in an addressed memory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the most-significant byte . see little-endian . boundedly undefined. a characteristic of certain operation results that are not rigidly prescribed by the powerpc architecture. boundedly- undefined results for a given operation may vary among implementations and between execution attempts in the same implementation. although the architecture does not prescribe the exact behavior for when results are allowed to be boundedly undefined , the results of executing instruct ions in contexts where results are allowed to be boundedly undefined are constrained to ones that could have been achieved by executing an arbitrary sequence of defined instructions, in valid form, starting in the state the machine was in before attempting to execute the given instruction. branch prediction. the process of guessing whet her a branch will be taken. such predictions can be correct or incorrect; the term ?predicted? as it is used here does not imply that the prediction is correct (successful). the powerpc architecture defines a means for static branch prediction as part of the instruction encoding. branch resolution. the determination of whether a branch is taken or not taken. a branch is said to be resolved when the processor can determine which instruction path to take. if the branch is resolved as predicted, the instructions following the predicted branch that may have been speculatively executed can complete (see completion ). if the branch is not resolved as predicted, instructions on the mispredicted path, and any results of speculative execution, are purged from the pipeline and fetching continues from the nonpredicted path.
glossary UM0434 382/391 c cache. high-speed memory containing recently a ccessed data or instru ctions (subset of main memory). cache block. a small region of contiguous memory that is copied from memory into a cache . the size of a cache block may vary among processors; the maximum block size is one page . in powerpc processors, cache coherency is maintained on a cache-block basis. note that the term cache block is often used interchangeably with ?cache line.? cache coherency. an attribute wherein an accurate and common view of memory is provided to all devices that share the same memory system. caches are coherent if a processor performing a read from its cache is supplied with data corresponding to the most recent value written to memory or to another processor?s cache. cache flush. an operation that removes from a cache any data from a specified address range. this operation ensures that any modified data within the specified address range is written back to main memory. this operation is generated typically by a data cache block flush ( dcbf ) instruction. caching-inhibited. a memory update policy in which the cache is bypassed and the load or store is performed to or from main memory. cast out. a cache block that must be written to memory when a cache miss causes a cache block to be replaced. changed bit. one of two page history bits found in each page table entry (pte). the processor sets the changed bit if any store is performed into the page . see also page access history bits and referenced bit . clean. an operation that causes a cache block to be written to memory, if modified, and then left in a valid, unmodified state in the cache. clear. to cause a bit or bit field to register a value of zero. see also set . completion. completion occurs when an instruction has finished executing, written back any results, and is removed from the completion queue (cq). when an instruction completes, it is guaranteed that this instruction and all previous instructions can cause no interrupts. context synchronization. an operation that ensures that all instructions in execution complete past the point where they can produce an interrupt , that all instructions in execution complete in the context in which they began execution, and that all subsequent instructions are fetched and executed in the new context. context synchronization may result from executing specific instructions (such as isync or rfi ) or when certain events occur (such as an interrupt ). copy-back operation. a cache operation in which a cache line is copied back to memory to enforce cache coherency. copy-back operations consist of snoop push-out operations and cache cast-out operations. d denormalized number. a nonzero floating-point number whose exponent has a reserved value, usually the format's minimum, and whose ex plicit or implicit lead ing significand bit is zero.
UM0434 glossary 383/391 e effective address (ea). the 32-bit address specified for a load, store, or an instruction fetch. this address is then submitted to the mmu for translation to either a physical memory address or an i/o address. exception. a condition that, if enabled, generates an interrupt. execution synchronization. a mechanism by which all instructions in execution are architecturally complete before beginning execution (appearing to begin execution) of the next instruction. similar to context synchronization but doesn't force the contents of the instruction buffers to be deleted and refetched. exponent. in the binary representation of a floating-point number, the exponent is the component that normally signifies the integer power to which the value two is raised in determining the value of the represented number. see also biased exponent . f fall-through (branch fall-through). a not-taken branch. fetch. retrieving instructions from either the cache or main memory and placing them into the instruction queue. finish. finishing occurs in the last cycle of executio n. in this cycle, the cq entry is updated to indicate that the instruction has finished executing. flush. an operation that causes a cache block to be invalidated and the data, if modified, to be written to memory. fraction. in the binary representation of a floating-point number, the field of the significand that lies to the right of its implied binary point. g general-purpose register (gpr). any of the 32 registers in the general-purpose register file. these registers provide the source operands and destination results for all integer data manipulation instructions. integer load instructions move data from memory to gprs and store instructions move data from gprs to memory. guarded. the guarded attribute pertains to out-of-order execution. when a page is designated as guarded, instructions and data cannot be accessed out-of-order. h harvard architecture. an architectural model featuring separate caches and other memory management resources for instructions and data. hashing. an algorithm used in the page table search process. i ieee 754. a standard written by the institute of electrical and electronics engineers that defines operations and representations of binary floating-point numbers. illegal instructions. a class of instructions that are not implemented for a particular powerpc processor. these include instructions not defined by the powerpc architecture. in
glossary UM0434 384/391 addition, for 32-bit implementations, instructions that are defined only for 64-bit implementations are considered to be illegal instructions. for 64-bit implementations instructions that are defined only for 32-bit implementations are considered to be illegal instructions. implementation. a particular processor that conforms to the powerpc architecture, but may differ from other architecture-compliant implementations for example in design, feature set, and implementation of optional features. the powerpc architecture has many different implementations. imprecise interrupt. a type of synchronous interrupt that is allowed not to adhere to the precise interrupt model (see precise interrupt ). the powerpc archit ecture allows only floating-point exceptions to be handled imprecisely. instruction queue. a holding place for instructions fetched from the current instruction stream. integer unit. the functional unit in the processor responsible for executing all integer instructions. in-order. an aspect of an operation that adheres to a sequential model. an operation is said to be performed in-order if, at the time that it is performed, it is known to be required by the sequential execution model. see out-of-order . instruction latency. the total number of clock cycles necessary to execute an instruction and make ready the results of that instruction. interrupt. a condition encountered by the processor that requires special, supervisor-level processing. interrupt handler. a software routine that executes when an interrupt is taken. normally, the interrupt handler corrects the condition that caused the interrupt, or performs some other meaningful task (that may include aborting the program that caused the interrupt). k kill. an operation that causes a cache block to be invalidated without writing any modified data to memory. l latency. the number of clock cycles necessary to execute an instruction and make ready the results of that execution for a subsequent instruction. l2 cache. see secondary cache . least-significant bit (lsb). the bit of least value in an address, register, field, data element, or instruction encoding. least-significant byte (lsb). the byte of least value in an address, register, data element, or instruction encoding. little-endian. a byte-ordering method in memory where the address n of a word corresponds to the least-significant byte . in an addressed memory word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3 being the most-significant byte . see big-endian .
UM0434 glossary 385/391 m mantissa. the decimal part of a logarithm. memory access ordering. the specific order in which the processor performs load and store memory accesses and the order in which those accesses complete. memory-mapped accesses. accesses whose addresses use the page or block address translation mechanisms provided by the mmu and that occur externally with the bus protocol defined for memory. memory coherency. an aspect of caching in which it is ensured that an accurate view of memory is provided to all devices that share system memory. memory consistency. refers to agreement of levels of memory with respect to a single processor and system memory (for example, on-chip cache, secondary cache, and system memory). memory management unit (mmu). the functional unit that is capable of translating an effective (logical) address to a physical address, providing protection mechanisms, and defining caching methods. most-significant bit (msb). the highest-order bit in an address, registers, data element, or instruction encoding. most-significant byte (msb). the highest-order byte in an address, registers, data element, or instruction encoding. n nan. an abbreviation for not a number; a symbolic entity encoded in floating-point format. there are two types of nans?signaling nans and quiet nans. no-op. no-operation. a single-cycle operation that does not affect registers or generate bus activity. normalization. a process by which a floating-point value is manipulated such that it can be represented in the format for the appropriate precision (single- or double-precision). for a floating-point value to be representable in the single- or double-precision format, the leading implied bit must be a 1. o optional. a feature, such as an instruction, a register, or an interrupt, that is defined by the powerpc architecture but not required to be implemented. out-of-order. an aspect of an operation that allows it to be performed ahead of one that may have preceded it in the sequential model, for example, speculative operations. an operation is said to be performed out-of-order if, at the time that it is performed, it is not known to be required by the sequential execution model. see in-order . out-of-order execution. a technique that allows instructions to be issued and completed in an order that differs from their sequence in the instruction stream. overflow. an condition that occurs during arithmetic operations when the result cannot be stored accurately in the destination register(s). for example, if two 32-bit numbers are multiplied, the result may not be representable in 32 bits. because 32-bit registers cannot represent this sum, an overflow condition occurs.
glossary UM0434 386/391 p page. a region in memory. the oea defines a page as a 4-kbyte area of memory, aligned on a 4-kbyte boundary. page access history bits. the changed and referenced bits in the pte keep track of the access history within the page. the referenced bit is set by the mmu whenever the page is accessed for a read or write operation. the changed bit is set when the page is stored into. see changed bit and referenced bit . page fault. a page fault is a condition that occurs when the processor attempts to access a memory location that does not reside within a page not currently resident in physical memory . on powerpc processors, a page fault inte rrupt condition occurs when a matching, valid page table entry (pte[v] = 1) cannot be located. page table. a table in memory is comprised of page table entries , or ptes. it is further organized into eight ptes per pteg (page table entry group). the number of ptegs in the page table depends on the size of the page table (as specified in the sdr1 register). physical memory. actual memory that can be accessed through system memory bus. pipelining. a technique that breaks operations, such as instruction processing or bus transactions, into smaller distinct stages or tenures (respectively) so that a subsequent operation can begin before the previous one has completed. precise interrupts. a category of interrupt for which the pipeline can be stopped so instructions that preceded the faulting instruction can complete and subsequent instructions can be flushed and redispatched after interrupt handling has completed. see imprecise interrupts . primary opcode. the most-significant 6 bits (bits 0?5) of the instruction encoding that identifies the type of instruction. program order. the order of instructions in an executing program. more specifically, this term is used to refer to the original order in which program instructions are fetched into the instruction queue from the cache. protection boundary. a boundary between protection domains . q quiesce. to come to rest. the processor is said to quiesce when an interrupt is taken or a sync instruction is executed. the instruction stream is stopped at the decode stage and executing instructions are allowed to complete to create a controlled context for instructions that may be affected by out-of-order, parallel execution. see context synchronization . quiet nan. a type of nan that can propagate through most arithmetic operations without signaling interrupts. a quiet nan is used to represent the results of certain invalid operations, such as invalid arithmetic operations on infinities or on nans, when invalid. see signaling nan . r record bit. bit 31 (or the rc bit) in the instruction encoding. when it is set, updates the condition register (cr) to reflect the result of the operation.
UM0434 glossary 387/391 referenced bit. one of two page history bits found in each page table entry . the processor sets the referenced bit whenever the page is accessed for a read or write. see also page access history bits . register indirect addressing. a form of addressing that specifies one gpr that contains the address for the load or store. register indirect with immediate index addressing. a form of addressing that specifies an immediate value to be added to the contents of a specified gpr to form the target address for the load or store. register indirect with index addressing. a form of addressing that specifies that the contents of two gprs be added together to yield the target address for the load or store. rename register. temporary buffers used by instructions that have finished execution but have not completed. reservation. the processor establishes a reservation on a cache block of memory space when it executes an lwarx instruction to read a memory semaphore into a gpr. reservation station. a buffer between the dispatch and execute stages that allows instructions to be dispatched even though the results of instructions on which the dispatched instruction may depend are not available. retirement. removal of the completed instruction from the cq. risc (reduced instruction set computing). an architecture characterized by fixed-length instructions with nonoverlapping functionality and by a separate set of load and store instructions that perform memory accesses. s secondary cache. a cache memory that is typically larger and has a longer access time than the primary cache. a secondary cache ma y be shared by multiple devices. also referred to as l2, or level-2, cache. set ( v ) . to write a nonzero value to a bit or bit field; the opposite of clear . the term ?set? may also be used to generally describe the updating of a bit or bit field. set ( n ) . a subdivision of a cache . cacheable data can be stored in a given location in one of the sets, typically corresponding to its lower-order address bits. because several memory locations can map to the same location, cached data is typically placed in the set whose cache block corresponding to that address was used least recently. see set-associative . set-associative. aspect of cache organization in which the cache space is divided into sections, called sets . the cache controller associates a particular main memory address with the contents of a particular set, or region, within the cache. shadowing. shadowing allows a register to be updated by instructions that are executed out of order without destroying machine state information. signaling nan. a type of nan that generates an invalid operation program interrupt when it is specified as arithmetic operands. see quiet nan . significand. the component of a binary floating-point number that consists of an explicit or implicit leading bit to the left of its implied binary point and a fraction field to the right. simplified mnemonics. assembler mnemonics that represent a more complex form of a common operation.
glossary UM0434 388/391 snooping. monitoring addresses driven by a bus master to detect the need for coherency actions. snoop push. response to a snooped transaction that hits a modified cache block. the cache block is written to memory and made available to the snooping device. split - transaction. a transaction with independent request and response tenures. split-transaction bus. a bus that allows address and data transactions from different processors to occur independently. stage. the term stage is used in two different senses, depending on whether the pipeline is being discussed as a physical entity or a sequence of events. in the latter case, a stage is an element in the pipeline during which certain actions are performed, such as decoding the instruction, performing an arithmetic operation, or writing back the results. typically, the latency of a stage is one processor clock cycle. some events, such as dispatch, write-back, and completion, happen instantaneously and may be thought to occur at the end of a stage. an instruction can spend multiple cycles in one stage. an integer multiply, for example, takes multiple cycles in the execute stage. when this occurs, subsequent instructions may stall. an instruction may also occupy more than one stage simultaneously, especially in the sense that a stage can be seen as a physical resource?for example, when instructions are dispatched they are assigned a place in the cq at the same time they are passed to the execute stage. they can be said to occupy both the complete and execute stages in the same clock cycle. stall. an occurrence when an instruction cannot proceed to the next stage. static branch prediction. mechanism by which software (for example, compilers) can hint to the machine hardware about the direction a branch is likely to take. store queue. holds store operations that have not been committed to memory, resulting from completed or retired instructions. superscalar. a superscalar processor is one that can dispatch multiple instructions concurrently from a conventional linear instruction stream. in a superscalar implementation, multiple instructions can be in the same stage at the same time. supervisor mode. the privileged operation state of a processor. in supervisor mode, software, typically the operating system, can access all control registers and can access the supervisor memory space, among other privileged operations. synchronization. a process to ensure that operations occur strictly in order . see context synchronization and execution synchronization . synchronous interrupt. an interrupt that is generated by the execution of a particular instruction or instruction sequence. there are two types of synchronous interrupts, precise and imprecise . system memory. the physical memory available to a processor. t tlb (translation lookaside buffer). a cache that holds recently-used page table entries . throughput. the number of instructions that are processed per clock cycle.
UM0434 glossary 389/391 u underflow. a condition that occurs during arithmetic operations when the result cannot be represented accurately in the destination register. for example, underflow can happen if two floating-point fractions are multiplied and the result requires a smaller exponent and/or mantissa than the single-precision format can provide. in other words, the result is too small to be represented accurately. user mode. the operating state of a processor used typically by application software. in user mode, software can access only certain control registers and can access only user memory space. no privileged operations can be performed. also referred to as problem state. v vea (virtual environment architecture). the level of the architecture that describes the memory model for an environment in which multiple devices can access memory, defines aspects of the cache model, defines cache control instructions, and defines the time-base facility from a user-level perspective. implementations that conform to the powerpc vea also adhere to the uisa, but may not necessarily adhere to the oea. virtual address. an intermediate address used in the translation of an effective address to a physical address. virtual memory. the address space created using the memory m anagement facilities of the processor. program access to virtual memory is possible only when it coincides with physical memory . w way. a location in the cache that holds a cache block, its tags and status bits. word. a 32-bit data element. write-back. a cache memory update policy in which processor write cycles are directly written only to the cache. external memory is updated only indirectly, for example, when a modified cache block is cast out to make room for newer data. write-through. a cache memory update policy in which all processor write cycles are written to both the cache and memory.
revision history UM0434 390/391 14 revision history table 284. document revision history date revision changes 25-may-2007 1 initial release. 29-nov-2013 2 u pdated disclai mer.
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